1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * adis16400.c support Analog Devices ADIS16400/5
4*4882a593Smuzhiyun * 3d 2g Linear Accelerometers,
5*4882a593Smuzhiyun * 3d Gyroscopes,
6*4882a593Smuzhiyun * 3d Magnetometers via SPI
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Copyright (c) 2009 Manuel Stahl <manuel.stahl@iis.fraunhofer.de>
9*4882a593Smuzhiyun * Copyright (c) 2007 Jonathan Cameron <jic23@kernel.org>
10*4882a593Smuzhiyun * Copyright (c) 2011 Analog Devices Inc.
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <linux/irq.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/mutex.h>
17*4882a593Smuzhiyun #include <linux/device.h>
18*4882a593Smuzhiyun #include <linux/kernel.h>
19*4882a593Smuzhiyun #include <linux/spi/spi.h>
20*4882a593Smuzhiyun #include <linux/slab.h>
21*4882a593Smuzhiyun #include <linux/sysfs.h>
22*4882a593Smuzhiyun #include <linux/list.h>
23*4882a593Smuzhiyun #include <linux/module.h>
24*4882a593Smuzhiyun #include <linux/debugfs.h>
25*4882a593Smuzhiyun #include <linux/bitops.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <linux/iio/iio.h>
28*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
29*4882a593Smuzhiyun #include <linux/iio/buffer.h>
30*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
31*4882a593Smuzhiyun #include <linux/iio/imu/adis.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define ADIS16400_STARTUP_DELAY 290 /* ms */
34*4882a593Smuzhiyun #define ADIS16400_MTEST_DELAY 90 /* ms */
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define ADIS16400_FLASH_CNT 0x00 /* Flash memory write count */
37*4882a593Smuzhiyun #define ADIS16400_SUPPLY_OUT 0x02 /* Power supply measurement */
38*4882a593Smuzhiyun #define ADIS16400_XGYRO_OUT 0x04 /* X-axis gyroscope output */
39*4882a593Smuzhiyun #define ADIS16400_YGYRO_OUT 0x06 /* Y-axis gyroscope output */
40*4882a593Smuzhiyun #define ADIS16400_ZGYRO_OUT 0x08 /* Z-axis gyroscope output */
41*4882a593Smuzhiyun #define ADIS16400_XACCL_OUT 0x0A /* X-axis accelerometer output */
42*4882a593Smuzhiyun #define ADIS16400_YACCL_OUT 0x0C /* Y-axis accelerometer output */
43*4882a593Smuzhiyun #define ADIS16400_ZACCL_OUT 0x0E /* Z-axis accelerometer output */
44*4882a593Smuzhiyun #define ADIS16400_XMAGN_OUT 0x10 /* X-axis magnetometer measurement */
45*4882a593Smuzhiyun #define ADIS16400_YMAGN_OUT 0x12 /* Y-axis magnetometer measurement */
46*4882a593Smuzhiyun #define ADIS16400_ZMAGN_OUT 0x14 /* Z-axis magnetometer measurement */
47*4882a593Smuzhiyun #define ADIS16400_TEMP_OUT 0x16 /* Temperature output */
48*4882a593Smuzhiyun #define ADIS16400_AUX_ADC 0x18 /* Auxiliary ADC measurement */
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define ADIS16350_XTEMP_OUT 0x10 /* X-axis gyroscope temperature measurement */
51*4882a593Smuzhiyun #define ADIS16350_YTEMP_OUT 0x12 /* Y-axis gyroscope temperature measurement */
52*4882a593Smuzhiyun #define ADIS16350_ZTEMP_OUT 0x14 /* Z-axis gyroscope temperature measurement */
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define ADIS16300_PITCH_OUT 0x12 /* X axis inclinometer output measurement */
55*4882a593Smuzhiyun #define ADIS16300_ROLL_OUT 0x14 /* Y axis inclinometer output measurement */
56*4882a593Smuzhiyun #define ADIS16300_AUX_ADC 0x16 /* Auxiliary ADC measurement */
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define ADIS16448_BARO_OUT 0x16 /* Barometric pressure output */
59*4882a593Smuzhiyun #define ADIS16448_TEMP_OUT 0x18 /* Temperature output */
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* Calibration parameters */
62*4882a593Smuzhiyun #define ADIS16400_XGYRO_OFF 0x1A /* X-axis gyroscope bias offset factor */
63*4882a593Smuzhiyun #define ADIS16400_YGYRO_OFF 0x1C /* Y-axis gyroscope bias offset factor */
64*4882a593Smuzhiyun #define ADIS16400_ZGYRO_OFF 0x1E /* Z-axis gyroscope bias offset factor */
65*4882a593Smuzhiyun #define ADIS16400_XACCL_OFF 0x20 /* X-axis acceleration bias offset factor */
66*4882a593Smuzhiyun #define ADIS16400_YACCL_OFF 0x22 /* Y-axis acceleration bias offset factor */
67*4882a593Smuzhiyun #define ADIS16400_ZACCL_OFF 0x24 /* Z-axis acceleration bias offset factor */
68*4882a593Smuzhiyun #define ADIS16400_XMAGN_HIF 0x26 /* X-axis magnetometer, hard-iron factor */
69*4882a593Smuzhiyun #define ADIS16400_YMAGN_HIF 0x28 /* Y-axis magnetometer, hard-iron factor */
70*4882a593Smuzhiyun #define ADIS16400_ZMAGN_HIF 0x2A /* Z-axis magnetometer, hard-iron factor */
71*4882a593Smuzhiyun #define ADIS16400_XMAGN_SIF 0x2C /* X-axis magnetometer, soft-iron factor */
72*4882a593Smuzhiyun #define ADIS16400_YMAGN_SIF 0x2E /* Y-axis magnetometer, soft-iron factor */
73*4882a593Smuzhiyun #define ADIS16400_ZMAGN_SIF 0x30 /* Z-axis magnetometer, soft-iron factor */
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun #define ADIS16400_GPIO_CTRL 0x32 /* Auxiliary digital input/output control */
76*4882a593Smuzhiyun #define ADIS16400_MSC_CTRL 0x34 /* Miscellaneous control */
77*4882a593Smuzhiyun #define ADIS16400_SMPL_PRD 0x36 /* Internal sample period (rate) control */
78*4882a593Smuzhiyun #define ADIS16400_SENS_AVG 0x38 /* Dynamic range and digital filter control */
79*4882a593Smuzhiyun #define ADIS16400_SLP_CNT 0x3A /* Sleep mode control */
80*4882a593Smuzhiyun #define ADIS16400_DIAG_STAT 0x3C /* System status */
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /* Alarm functions */
83*4882a593Smuzhiyun #define ADIS16400_GLOB_CMD 0x3E /* System command */
84*4882a593Smuzhiyun #define ADIS16400_ALM_MAG1 0x40 /* Alarm 1 amplitude threshold */
85*4882a593Smuzhiyun #define ADIS16400_ALM_MAG2 0x42 /* Alarm 2 amplitude threshold */
86*4882a593Smuzhiyun #define ADIS16400_ALM_SMPL1 0x44 /* Alarm 1 sample size */
87*4882a593Smuzhiyun #define ADIS16400_ALM_SMPL2 0x46 /* Alarm 2 sample size */
88*4882a593Smuzhiyun #define ADIS16400_ALM_CTRL 0x48 /* Alarm control */
89*4882a593Smuzhiyun #define ADIS16400_AUX_DAC 0x4A /* Auxiliary DAC data */
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun #define ADIS16334_LOT_ID1 0x52 /* Lot identification code 1 */
92*4882a593Smuzhiyun #define ADIS16334_LOT_ID2 0x54 /* Lot identification code 2 */
93*4882a593Smuzhiyun #define ADIS16400_PRODUCT_ID 0x56 /* Product identifier */
94*4882a593Smuzhiyun #define ADIS16334_SERIAL_NUMBER 0x58 /* Serial number, lot specific */
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun #define ADIS16400_ERROR_ACTIVE (1<<14)
97*4882a593Smuzhiyun #define ADIS16400_NEW_DATA (1<<14)
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* MSC_CTRL */
100*4882a593Smuzhiyun #define ADIS16400_MSC_CTRL_MEM_TEST (1<<11)
101*4882a593Smuzhiyun #define ADIS16400_MSC_CTRL_INT_SELF_TEST (1<<10)
102*4882a593Smuzhiyun #define ADIS16400_MSC_CTRL_NEG_SELF_TEST (1<<9)
103*4882a593Smuzhiyun #define ADIS16400_MSC_CTRL_POS_SELF_TEST (1<<8)
104*4882a593Smuzhiyun #define ADIS16400_MSC_CTRL_GYRO_BIAS (1<<7)
105*4882a593Smuzhiyun #define ADIS16400_MSC_CTRL_ACCL_ALIGN (1<<6)
106*4882a593Smuzhiyun #define ADIS16400_MSC_CTRL_DATA_RDY_EN (1<<2)
107*4882a593Smuzhiyun #define ADIS16400_MSC_CTRL_DATA_RDY_POL_HIGH (1<<1)
108*4882a593Smuzhiyun #define ADIS16400_MSC_CTRL_DATA_RDY_DIO2 (1<<0)
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* SMPL_PRD */
111*4882a593Smuzhiyun #define ADIS16400_SMPL_PRD_TIME_BASE (1<<7)
112*4882a593Smuzhiyun #define ADIS16400_SMPL_PRD_DIV_MASK 0x7F
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* DIAG_STAT */
115*4882a593Smuzhiyun #define ADIS16400_DIAG_STAT_ZACCL_FAIL 15
116*4882a593Smuzhiyun #define ADIS16400_DIAG_STAT_YACCL_FAIL 14
117*4882a593Smuzhiyun #define ADIS16400_DIAG_STAT_XACCL_FAIL 13
118*4882a593Smuzhiyun #define ADIS16400_DIAG_STAT_XGYRO_FAIL 12
119*4882a593Smuzhiyun #define ADIS16400_DIAG_STAT_YGYRO_FAIL 11
120*4882a593Smuzhiyun #define ADIS16400_DIAG_STAT_ZGYRO_FAIL 10
121*4882a593Smuzhiyun #define ADIS16400_DIAG_STAT_ALARM2 9
122*4882a593Smuzhiyun #define ADIS16400_DIAG_STAT_ALARM1 8
123*4882a593Smuzhiyun #define ADIS16400_DIAG_STAT_FLASH_CHK 6
124*4882a593Smuzhiyun #define ADIS16400_DIAG_STAT_SELF_TEST 5
125*4882a593Smuzhiyun #define ADIS16400_DIAG_STAT_OVERFLOW 4
126*4882a593Smuzhiyun #define ADIS16400_DIAG_STAT_SPI_FAIL 3
127*4882a593Smuzhiyun #define ADIS16400_DIAG_STAT_FLASH_UPT 2
128*4882a593Smuzhiyun #define ADIS16400_DIAG_STAT_POWER_HIGH 1
129*4882a593Smuzhiyun #define ADIS16400_DIAG_STAT_POWER_LOW 0
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* GLOB_CMD */
132*4882a593Smuzhiyun #define ADIS16400_GLOB_CMD_SW_RESET (1<<7)
133*4882a593Smuzhiyun #define ADIS16400_GLOB_CMD_P_AUTO_NULL (1<<4)
134*4882a593Smuzhiyun #define ADIS16400_GLOB_CMD_FLASH_UPD (1<<3)
135*4882a593Smuzhiyun #define ADIS16400_GLOB_CMD_DAC_LATCH (1<<2)
136*4882a593Smuzhiyun #define ADIS16400_GLOB_CMD_FAC_CALIB (1<<1)
137*4882a593Smuzhiyun #define ADIS16400_GLOB_CMD_AUTO_NULL (1<<0)
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun /* SLP_CNT */
140*4882a593Smuzhiyun #define ADIS16400_SLP_CNT_POWER_OFF (1<<8)
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun #define ADIS16334_RATE_DIV_SHIFT 8
143*4882a593Smuzhiyun #define ADIS16334_RATE_INT_CLK BIT(0)
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun #define ADIS16400_SPI_SLOW (u32)(300 * 1000)
146*4882a593Smuzhiyun #define ADIS16400_SPI_BURST (u32)(1000 * 1000)
147*4882a593Smuzhiyun #define ADIS16400_SPI_FAST (u32)(2000 * 1000)
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun #define ADIS16400_HAS_PROD_ID BIT(0)
150*4882a593Smuzhiyun #define ADIS16400_NO_BURST BIT(1)
151*4882a593Smuzhiyun #define ADIS16400_HAS_SLOW_MODE BIT(2)
152*4882a593Smuzhiyun #define ADIS16400_HAS_SERIAL_NUMBER BIT(3)
153*4882a593Smuzhiyun #define ADIS16400_BURST_DIAG_STAT BIT(4)
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun struct adis16400_state;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun struct adis16400_chip_info {
158*4882a593Smuzhiyun const struct iio_chan_spec *channels;
159*4882a593Smuzhiyun const struct adis_data adis_data;
160*4882a593Smuzhiyun const int num_channels;
161*4882a593Smuzhiyun const long flags;
162*4882a593Smuzhiyun unsigned int gyro_scale_micro;
163*4882a593Smuzhiyun unsigned int accel_scale_micro;
164*4882a593Smuzhiyun int temp_scale_nano;
165*4882a593Smuzhiyun int temp_offset;
166*4882a593Smuzhiyun /* set_freq() & get_freq() need to avoid using ADIS lib's state lock */
167*4882a593Smuzhiyun int (*set_freq)(struct adis16400_state *st, unsigned int freq);
168*4882a593Smuzhiyun int (*get_freq)(struct adis16400_state *st);
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun /**
172*4882a593Smuzhiyun * struct adis16400_state - device instance specific data
173*4882a593Smuzhiyun * @variant: chip variant info
174*4882a593Smuzhiyun * @filt_int: integer part of requested filter frequency
175*4882a593Smuzhiyun * @adis: adis device
176*4882a593Smuzhiyun * @avail_scan_mask: NULL terminated array of bitmaps of channels
177*4882a593Smuzhiyun * that must be enabled together
178*4882a593Smuzhiyun **/
179*4882a593Smuzhiyun struct adis16400_state {
180*4882a593Smuzhiyun struct adis16400_chip_info *variant;
181*4882a593Smuzhiyun int filt_int;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun struct adis adis;
184*4882a593Smuzhiyun unsigned long avail_scan_mask[2];
185*4882a593Smuzhiyun };
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun /* At the moment triggers are only used for ring buffer
188*4882a593Smuzhiyun * filling. This may change!
189*4882a593Smuzhiyun */
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun enum {
192*4882a593Smuzhiyun ADIS16400_SCAN_SUPPLY,
193*4882a593Smuzhiyun ADIS16400_SCAN_GYRO_X,
194*4882a593Smuzhiyun ADIS16400_SCAN_GYRO_Y,
195*4882a593Smuzhiyun ADIS16400_SCAN_GYRO_Z,
196*4882a593Smuzhiyun ADIS16400_SCAN_ACC_X,
197*4882a593Smuzhiyun ADIS16400_SCAN_ACC_Y,
198*4882a593Smuzhiyun ADIS16400_SCAN_ACC_Z,
199*4882a593Smuzhiyun ADIS16400_SCAN_MAGN_X,
200*4882a593Smuzhiyun ADIS16400_SCAN_MAGN_Y,
201*4882a593Smuzhiyun ADIS16400_SCAN_MAGN_Z,
202*4882a593Smuzhiyun ADIS16400_SCAN_BARO,
203*4882a593Smuzhiyun ADIS16350_SCAN_TEMP_X,
204*4882a593Smuzhiyun ADIS16350_SCAN_TEMP_Y,
205*4882a593Smuzhiyun ADIS16350_SCAN_TEMP_Z,
206*4882a593Smuzhiyun ADIS16300_SCAN_INCLI_X,
207*4882a593Smuzhiyun ADIS16300_SCAN_INCLI_Y,
208*4882a593Smuzhiyun ADIS16400_SCAN_ADC,
209*4882a593Smuzhiyun ADIS16400_SCAN_TIMESTAMP,
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
213*4882a593Smuzhiyun
adis16400_show_serial_number(struct file * file,char __user * userbuf,size_t count,loff_t * ppos)214*4882a593Smuzhiyun static ssize_t adis16400_show_serial_number(struct file *file,
215*4882a593Smuzhiyun char __user *userbuf, size_t count, loff_t *ppos)
216*4882a593Smuzhiyun {
217*4882a593Smuzhiyun struct adis16400_state *st = file->private_data;
218*4882a593Smuzhiyun u16 lot1, lot2, serial_number;
219*4882a593Smuzhiyun char buf[16];
220*4882a593Smuzhiyun size_t len;
221*4882a593Smuzhiyun int ret;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun ret = adis_read_reg_16(&st->adis, ADIS16334_LOT_ID1, &lot1);
224*4882a593Smuzhiyun if (ret)
225*4882a593Smuzhiyun return ret;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun ret = adis_read_reg_16(&st->adis, ADIS16334_LOT_ID2, &lot2);
228*4882a593Smuzhiyun if (ret)
229*4882a593Smuzhiyun return ret;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun ret = adis_read_reg_16(&st->adis, ADIS16334_SERIAL_NUMBER,
232*4882a593Smuzhiyun &serial_number);
233*4882a593Smuzhiyun if (ret)
234*4882a593Smuzhiyun return ret;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun len = snprintf(buf, sizeof(buf), "%.4x-%.4x-%.4x\n", lot1, lot2,
237*4882a593Smuzhiyun serial_number);
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun return simple_read_from_buffer(userbuf, count, ppos, buf, len);
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun static const struct file_operations adis16400_serial_number_fops = {
243*4882a593Smuzhiyun .open = simple_open,
244*4882a593Smuzhiyun .read = adis16400_show_serial_number,
245*4882a593Smuzhiyun .llseek = default_llseek,
246*4882a593Smuzhiyun .owner = THIS_MODULE,
247*4882a593Smuzhiyun };
248*4882a593Smuzhiyun
adis16400_show_product_id(void * arg,u64 * val)249*4882a593Smuzhiyun static int adis16400_show_product_id(void *arg, u64 *val)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun struct adis16400_state *st = arg;
252*4882a593Smuzhiyun uint16_t prod_id;
253*4882a593Smuzhiyun int ret;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun ret = adis_read_reg_16(&st->adis, ADIS16400_PRODUCT_ID, &prod_id);
256*4882a593Smuzhiyun if (ret)
257*4882a593Smuzhiyun return ret;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun *val = prod_id;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun return 0;
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun DEFINE_DEBUGFS_ATTRIBUTE(adis16400_product_id_fops,
264*4882a593Smuzhiyun adis16400_show_product_id, NULL, "%lld\n");
265*4882a593Smuzhiyun
adis16400_show_flash_count(void * arg,u64 * val)266*4882a593Smuzhiyun static int adis16400_show_flash_count(void *arg, u64 *val)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun struct adis16400_state *st = arg;
269*4882a593Smuzhiyun uint16_t flash_count;
270*4882a593Smuzhiyun int ret;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun ret = adis_read_reg_16(&st->adis, ADIS16400_FLASH_CNT, &flash_count);
273*4882a593Smuzhiyun if (ret)
274*4882a593Smuzhiyun return ret;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun *val = flash_count;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun return 0;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun DEFINE_DEBUGFS_ATTRIBUTE(adis16400_flash_count_fops,
281*4882a593Smuzhiyun adis16400_show_flash_count, NULL, "%lld\n");
282*4882a593Smuzhiyun
adis16400_debugfs_init(struct iio_dev * indio_dev)283*4882a593Smuzhiyun static int adis16400_debugfs_init(struct iio_dev *indio_dev)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun struct adis16400_state *st = iio_priv(indio_dev);
286*4882a593Smuzhiyun struct dentry *d = iio_get_debugfs_dentry(indio_dev);
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun if (st->variant->flags & ADIS16400_HAS_SERIAL_NUMBER)
289*4882a593Smuzhiyun debugfs_create_file_unsafe("serial_number", 0400,
290*4882a593Smuzhiyun d, st, &adis16400_serial_number_fops);
291*4882a593Smuzhiyun if (st->variant->flags & ADIS16400_HAS_PROD_ID)
292*4882a593Smuzhiyun debugfs_create_file_unsafe("product_id", 0400,
293*4882a593Smuzhiyun d, st, &adis16400_product_id_fops);
294*4882a593Smuzhiyun debugfs_create_file_unsafe("flash_count", 0400,
295*4882a593Smuzhiyun d, st, &adis16400_flash_count_fops);
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun return 0;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun #else
301*4882a593Smuzhiyun
adis16400_debugfs_init(struct iio_dev * indio_dev)302*4882a593Smuzhiyun static int adis16400_debugfs_init(struct iio_dev *indio_dev)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun return 0;
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun #endif
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun enum adis16400_chip_variant {
310*4882a593Smuzhiyun ADIS16300,
311*4882a593Smuzhiyun ADIS16334,
312*4882a593Smuzhiyun ADIS16350,
313*4882a593Smuzhiyun ADIS16360,
314*4882a593Smuzhiyun ADIS16362,
315*4882a593Smuzhiyun ADIS16364,
316*4882a593Smuzhiyun ADIS16367,
317*4882a593Smuzhiyun ADIS16400,
318*4882a593Smuzhiyun ADIS16445,
319*4882a593Smuzhiyun ADIS16448,
320*4882a593Smuzhiyun };
321*4882a593Smuzhiyun
adis16334_get_freq(struct adis16400_state * st)322*4882a593Smuzhiyun static int adis16334_get_freq(struct adis16400_state *st)
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun int ret;
325*4882a593Smuzhiyun uint16_t t;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun ret = __adis_read_reg_16(&st->adis, ADIS16400_SMPL_PRD, &t);
328*4882a593Smuzhiyun if (ret)
329*4882a593Smuzhiyun return ret;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun t >>= ADIS16334_RATE_DIV_SHIFT;
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun return 819200 >> t;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun
adis16334_set_freq(struct adis16400_state * st,unsigned int freq)336*4882a593Smuzhiyun static int adis16334_set_freq(struct adis16400_state *st, unsigned int freq)
337*4882a593Smuzhiyun {
338*4882a593Smuzhiyun unsigned int t;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun if (freq < 819200)
341*4882a593Smuzhiyun t = ilog2(819200 / freq);
342*4882a593Smuzhiyun else
343*4882a593Smuzhiyun t = 0;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun if (t > 0x31)
346*4882a593Smuzhiyun t = 0x31;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun t <<= ADIS16334_RATE_DIV_SHIFT;
349*4882a593Smuzhiyun t |= ADIS16334_RATE_INT_CLK;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun return __adis_write_reg_16(&st->adis, ADIS16400_SMPL_PRD, t);
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
adis16400_get_freq(struct adis16400_state * st)354*4882a593Smuzhiyun static int adis16400_get_freq(struct adis16400_state *st)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun int sps, ret;
357*4882a593Smuzhiyun uint16_t t;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun ret = __adis_read_reg_16(&st->adis, ADIS16400_SMPL_PRD, &t);
360*4882a593Smuzhiyun if (ret)
361*4882a593Smuzhiyun return ret;
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun sps = (t & ADIS16400_SMPL_PRD_TIME_BASE) ? 52851 : 1638404;
364*4882a593Smuzhiyun sps /= (t & ADIS16400_SMPL_PRD_DIV_MASK) + 1;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun return sps;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun
adis16400_set_freq(struct adis16400_state * st,unsigned int freq)369*4882a593Smuzhiyun static int adis16400_set_freq(struct adis16400_state *st, unsigned int freq)
370*4882a593Smuzhiyun {
371*4882a593Smuzhiyun unsigned int t;
372*4882a593Smuzhiyun uint8_t val = 0;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun t = 1638404 / freq;
375*4882a593Smuzhiyun if (t >= 128) {
376*4882a593Smuzhiyun val |= ADIS16400_SMPL_PRD_TIME_BASE;
377*4882a593Smuzhiyun t = 52851 / freq;
378*4882a593Smuzhiyun if (t >= 128)
379*4882a593Smuzhiyun t = 127;
380*4882a593Smuzhiyun } else if (t != 0) {
381*4882a593Smuzhiyun t--;
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun val |= t;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun if (t >= 0x0A || (val & ADIS16400_SMPL_PRD_TIME_BASE))
387*4882a593Smuzhiyun st->adis.spi->max_speed_hz = ADIS16400_SPI_SLOW;
388*4882a593Smuzhiyun else
389*4882a593Smuzhiyun st->adis.spi->max_speed_hz = ADIS16400_SPI_FAST;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun return __adis_write_reg_8(&st->adis, ADIS16400_SMPL_PRD, val);
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun static const unsigned int adis16400_3db_divisors[] = {
395*4882a593Smuzhiyun [0] = 2, /* Special case */
396*4882a593Smuzhiyun [1] = 6,
397*4882a593Smuzhiyun [2] = 12,
398*4882a593Smuzhiyun [3] = 25,
399*4882a593Smuzhiyun [4] = 50,
400*4882a593Smuzhiyun [5] = 100,
401*4882a593Smuzhiyun [6] = 200,
402*4882a593Smuzhiyun [7] = 200, /* Not a valid setting */
403*4882a593Smuzhiyun };
404*4882a593Smuzhiyun
__adis16400_set_filter(struct iio_dev * indio_dev,int sps,int val)405*4882a593Smuzhiyun static int __adis16400_set_filter(struct iio_dev *indio_dev, int sps, int val)
406*4882a593Smuzhiyun {
407*4882a593Smuzhiyun struct adis16400_state *st = iio_priv(indio_dev);
408*4882a593Smuzhiyun uint16_t val16;
409*4882a593Smuzhiyun int i, ret;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun for (i = ARRAY_SIZE(adis16400_3db_divisors) - 1; i >= 1; i--) {
412*4882a593Smuzhiyun if (sps / adis16400_3db_divisors[i] >= val)
413*4882a593Smuzhiyun break;
414*4882a593Smuzhiyun }
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun ret = __adis_read_reg_16(&st->adis, ADIS16400_SENS_AVG, &val16);
417*4882a593Smuzhiyun if (ret)
418*4882a593Smuzhiyun return ret;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun ret = __adis_write_reg_16(&st->adis, ADIS16400_SENS_AVG,
421*4882a593Smuzhiyun (val16 & ~0x07) | i);
422*4882a593Smuzhiyun return ret;
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun /* Power down the device */
adis16400_stop_device(struct iio_dev * indio_dev)426*4882a593Smuzhiyun static int adis16400_stop_device(struct iio_dev *indio_dev)
427*4882a593Smuzhiyun {
428*4882a593Smuzhiyun struct adis16400_state *st = iio_priv(indio_dev);
429*4882a593Smuzhiyun int ret;
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun ret = adis_write_reg_16(&st->adis, ADIS16400_SLP_CNT,
432*4882a593Smuzhiyun ADIS16400_SLP_CNT_POWER_OFF);
433*4882a593Smuzhiyun if (ret)
434*4882a593Smuzhiyun dev_err(&indio_dev->dev,
435*4882a593Smuzhiyun "problem with turning device off: SLP_CNT");
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun return ret;
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun
adis16400_initial_setup(struct iio_dev * indio_dev)440*4882a593Smuzhiyun static int adis16400_initial_setup(struct iio_dev *indio_dev)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun struct adis16400_state *st = iio_priv(indio_dev);
443*4882a593Smuzhiyun uint16_t prod_id, smp_prd;
444*4882a593Smuzhiyun unsigned int device_id;
445*4882a593Smuzhiyun int ret;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun /* use low spi speed for init if the device has a slow mode */
448*4882a593Smuzhiyun if (st->variant->flags & ADIS16400_HAS_SLOW_MODE)
449*4882a593Smuzhiyun st->adis.spi->max_speed_hz = ADIS16400_SPI_SLOW;
450*4882a593Smuzhiyun else
451*4882a593Smuzhiyun st->adis.spi->max_speed_hz = ADIS16400_SPI_FAST;
452*4882a593Smuzhiyun st->adis.spi->mode = SPI_MODE_3;
453*4882a593Smuzhiyun spi_setup(st->adis.spi);
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun ret = adis_initial_startup(&st->adis);
456*4882a593Smuzhiyun if (ret)
457*4882a593Smuzhiyun return ret;
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun if (st->variant->flags & ADIS16400_HAS_PROD_ID) {
460*4882a593Smuzhiyun ret = adis_read_reg_16(&st->adis,
461*4882a593Smuzhiyun ADIS16400_PRODUCT_ID, &prod_id);
462*4882a593Smuzhiyun if (ret)
463*4882a593Smuzhiyun goto err_ret;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun if (sscanf(indio_dev->name, "adis%u\n", &device_id) != 1) {
466*4882a593Smuzhiyun ret = -EINVAL;
467*4882a593Smuzhiyun goto err_ret;
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun if (prod_id != device_id)
471*4882a593Smuzhiyun dev_warn(&indio_dev->dev, "Device ID(%u) and product ID(%u) do not match.",
472*4882a593Smuzhiyun device_id, prod_id);
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun dev_info(&indio_dev->dev, "%s: prod_id 0x%04x at CS%d (irq %d)\n",
475*4882a593Smuzhiyun indio_dev->name, prod_id,
476*4882a593Smuzhiyun st->adis.spi->chip_select, st->adis.spi->irq);
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun /* use high spi speed if possible */
479*4882a593Smuzhiyun if (st->variant->flags & ADIS16400_HAS_SLOW_MODE) {
480*4882a593Smuzhiyun ret = adis_read_reg_16(&st->adis, ADIS16400_SMPL_PRD, &smp_prd);
481*4882a593Smuzhiyun if (ret)
482*4882a593Smuzhiyun goto err_ret;
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun if ((smp_prd & ADIS16400_SMPL_PRD_DIV_MASK) < 0x0A) {
485*4882a593Smuzhiyun st->adis.spi->max_speed_hz = ADIS16400_SPI_FAST;
486*4882a593Smuzhiyun spi_setup(st->adis.spi);
487*4882a593Smuzhiyun }
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun err_ret:
491*4882a593Smuzhiyun return ret;
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun static const uint8_t adis16400_addresses[] = {
495*4882a593Smuzhiyun [ADIS16400_SCAN_GYRO_X] = ADIS16400_XGYRO_OFF,
496*4882a593Smuzhiyun [ADIS16400_SCAN_GYRO_Y] = ADIS16400_YGYRO_OFF,
497*4882a593Smuzhiyun [ADIS16400_SCAN_GYRO_Z] = ADIS16400_ZGYRO_OFF,
498*4882a593Smuzhiyun [ADIS16400_SCAN_ACC_X] = ADIS16400_XACCL_OFF,
499*4882a593Smuzhiyun [ADIS16400_SCAN_ACC_Y] = ADIS16400_YACCL_OFF,
500*4882a593Smuzhiyun [ADIS16400_SCAN_ACC_Z] = ADIS16400_ZACCL_OFF,
501*4882a593Smuzhiyun };
502*4882a593Smuzhiyun
adis16400_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)503*4882a593Smuzhiyun static int adis16400_write_raw(struct iio_dev *indio_dev,
504*4882a593Smuzhiyun struct iio_chan_spec const *chan, int val, int val2, long info)
505*4882a593Smuzhiyun {
506*4882a593Smuzhiyun struct adis16400_state *st = iio_priv(indio_dev);
507*4882a593Smuzhiyun struct mutex *slock = &st->adis.state_lock;
508*4882a593Smuzhiyun int ret, sps;
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun switch (info) {
511*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBBIAS:
512*4882a593Smuzhiyun ret = adis_write_reg_16(&st->adis,
513*4882a593Smuzhiyun adis16400_addresses[chan->scan_index], val);
514*4882a593Smuzhiyun return ret;
515*4882a593Smuzhiyun case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
516*4882a593Smuzhiyun /*
517*4882a593Smuzhiyun * Need to cache values so we can update if the frequency
518*4882a593Smuzhiyun * changes.
519*4882a593Smuzhiyun */
520*4882a593Smuzhiyun mutex_lock(slock);
521*4882a593Smuzhiyun st->filt_int = val;
522*4882a593Smuzhiyun /* Work out update to current value */
523*4882a593Smuzhiyun sps = st->variant->get_freq(st);
524*4882a593Smuzhiyun if (sps < 0) {
525*4882a593Smuzhiyun mutex_unlock(slock);
526*4882a593Smuzhiyun return sps;
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun ret = __adis16400_set_filter(indio_dev, sps,
530*4882a593Smuzhiyun val * 1000 + val2 / 1000);
531*4882a593Smuzhiyun mutex_unlock(slock);
532*4882a593Smuzhiyun return ret;
533*4882a593Smuzhiyun case IIO_CHAN_INFO_SAMP_FREQ:
534*4882a593Smuzhiyun sps = val * 1000 + val2 / 1000;
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun if (sps <= 0)
537*4882a593Smuzhiyun return -EINVAL;
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun mutex_lock(slock);
540*4882a593Smuzhiyun ret = st->variant->set_freq(st, sps);
541*4882a593Smuzhiyun mutex_unlock(slock);
542*4882a593Smuzhiyun return ret;
543*4882a593Smuzhiyun default:
544*4882a593Smuzhiyun return -EINVAL;
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun
adis16400_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)548*4882a593Smuzhiyun static int adis16400_read_raw(struct iio_dev *indio_dev,
549*4882a593Smuzhiyun struct iio_chan_spec const *chan, int *val, int *val2, long info)
550*4882a593Smuzhiyun {
551*4882a593Smuzhiyun struct adis16400_state *st = iio_priv(indio_dev);
552*4882a593Smuzhiyun struct mutex *slock = &st->adis.state_lock;
553*4882a593Smuzhiyun int16_t val16;
554*4882a593Smuzhiyun int ret;
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun switch (info) {
557*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
558*4882a593Smuzhiyun return adis_single_conversion(indio_dev, chan, 0, val);
559*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
560*4882a593Smuzhiyun switch (chan->type) {
561*4882a593Smuzhiyun case IIO_ANGL_VEL:
562*4882a593Smuzhiyun *val = 0;
563*4882a593Smuzhiyun *val2 = st->variant->gyro_scale_micro;
564*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
565*4882a593Smuzhiyun case IIO_VOLTAGE:
566*4882a593Smuzhiyun *val = 0;
567*4882a593Smuzhiyun if (chan->channel == 0) {
568*4882a593Smuzhiyun *val = 2;
569*4882a593Smuzhiyun *val2 = 418000; /* 2.418 mV */
570*4882a593Smuzhiyun } else {
571*4882a593Smuzhiyun *val = 0;
572*4882a593Smuzhiyun *val2 = 805800; /* 805.8 uV */
573*4882a593Smuzhiyun }
574*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
575*4882a593Smuzhiyun case IIO_ACCEL:
576*4882a593Smuzhiyun *val = 0;
577*4882a593Smuzhiyun *val2 = st->variant->accel_scale_micro;
578*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
579*4882a593Smuzhiyun case IIO_MAGN:
580*4882a593Smuzhiyun *val = 0;
581*4882a593Smuzhiyun *val2 = 500; /* 0.5 mgauss */
582*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
583*4882a593Smuzhiyun case IIO_TEMP:
584*4882a593Smuzhiyun *val = st->variant->temp_scale_nano / 1000000;
585*4882a593Smuzhiyun *val2 = (st->variant->temp_scale_nano % 1000000);
586*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
587*4882a593Smuzhiyun case IIO_PRESSURE:
588*4882a593Smuzhiyun /* 20 uBar = 0.002kPascal */
589*4882a593Smuzhiyun *val = 0;
590*4882a593Smuzhiyun *val2 = 2000;
591*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
592*4882a593Smuzhiyun default:
593*4882a593Smuzhiyun return -EINVAL;
594*4882a593Smuzhiyun }
595*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBBIAS:
596*4882a593Smuzhiyun ret = adis_read_reg_16(&st->adis,
597*4882a593Smuzhiyun adis16400_addresses[chan->scan_index], &val16);
598*4882a593Smuzhiyun if (ret)
599*4882a593Smuzhiyun return ret;
600*4882a593Smuzhiyun val16 = sign_extend32(val16, 11);
601*4882a593Smuzhiyun *val = val16;
602*4882a593Smuzhiyun return IIO_VAL_INT;
603*4882a593Smuzhiyun case IIO_CHAN_INFO_OFFSET:
604*4882a593Smuzhiyun /* currently only temperature */
605*4882a593Smuzhiyun *val = st->variant->temp_offset;
606*4882a593Smuzhiyun return IIO_VAL_INT;
607*4882a593Smuzhiyun case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
608*4882a593Smuzhiyun mutex_lock(slock);
609*4882a593Smuzhiyun /* Need both the number of taps and the sampling frequency */
610*4882a593Smuzhiyun ret = __adis_read_reg_16(&st->adis,
611*4882a593Smuzhiyun ADIS16400_SENS_AVG,
612*4882a593Smuzhiyun &val16);
613*4882a593Smuzhiyun if (ret) {
614*4882a593Smuzhiyun mutex_unlock(slock);
615*4882a593Smuzhiyun return ret;
616*4882a593Smuzhiyun }
617*4882a593Smuzhiyun ret = st->variant->get_freq(st);
618*4882a593Smuzhiyun mutex_unlock(slock);
619*4882a593Smuzhiyun if (ret)
620*4882a593Smuzhiyun return ret;
621*4882a593Smuzhiyun ret /= adis16400_3db_divisors[val16 & 0x07];
622*4882a593Smuzhiyun *val = ret / 1000;
623*4882a593Smuzhiyun *val2 = (ret % 1000) * 1000;
624*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
625*4882a593Smuzhiyun case IIO_CHAN_INFO_SAMP_FREQ:
626*4882a593Smuzhiyun mutex_lock(slock);
627*4882a593Smuzhiyun ret = st->variant->get_freq(st);
628*4882a593Smuzhiyun mutex_unlock(slock);
629*4882a593Smuzhiyun if (ret)
630*4882a593Smuzhiyun return ret;
631*4882a593Smuzhiyun *val = ret / 1000;
632*4882a593Smuzhiyun *val2 = (ret % 1000) * 1000;
633*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
634*4882a593Smuzhiyun default:
635*4882a593Smuzhiyun return -EINVAL;
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_IIO_BUFFER)
adis16400_trigger_handler(int irq,void * p)640*4882a593Smuzhiyun static irqreturn_t adis16400_trigger_handler(int irq, void *p)
641*4882a593Smuzhiyun {
642*4882a593Smuzhiyun struct iio_poll_func *pf = p;
643*4882a593Smuzhiyun struct iio_dev *indio_dev = pf->indio_dev;
644*4882a593Smuzhiyun struct adis16400_state *st = iio_priv(indio_dev);
645*4882a593Smuzhiyun struct adis *adis = &st->adis;
646*4882a593Smuzhiyun u32 old_speed_hz = st->adis.spi->max_speed_hz;
647*4882a593Smuzhiyun void *buffer;
648*4882a593Smuzhiyun int ret;
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun if (!(st->variant->flags & ADIS16400_NO_BURST) &&
651*4882a593Smuzhiyun st->adis.spi->max_speed_hz > ADIS16400_SPI_BURST) {
652*4882a593Smuzhiyun st->adis.spi->max_speed_hz = ADIS16400_SPI_BURST;
653*4882a593Smuzhiyun spi_setup(st->adis.spi);
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun ret = spi_sync(adis->spi, &adis->msg);
657*4882a593Smuzhiyun if (ret)
658*4882a593Smuzhiyun dev_err(&adis->spi->dev, "Failed to read data: %d\n", ret);
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun if (!(st->variant->flags & ADIS16400_NO_BURST)) {
661*4882a593Smuzhiyun st->adis.spi->max_speed_hz = old_speed_hz;
662*4882a593Smuzhiyun spi_setup(st->adis.spi);
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun if (st->variant->flags & ADIS16400_BURST_DIAG_STAT)
666*4882a593Smuzhiyun buffer = adis->buffer + sizeof(u16);
667*4882a593Smuzhiyun else
668*4882a593Smuzhiyun buffer = adis->buffer;
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun iio_push_to_buffers_with_timestamp(indio_dev, buffer,
671*4882a593Smuzhiyun pf->timestamp);
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun iio_trigger_notify_done(indio_dev->trig);
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun return IRQ_HANDLED;
676*4882a593Smuzhiyun }
677*4882a593Smuzhiyun #else
678*4882a593Smuzhiyun #define adis16400_trigger_handler NULL
679*4882a593Smuzhiyun #endif /* IS_ENABLED(CONFIG_IIO_BUFFER) */
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun #define ADIS16400_VOLTAGE_CHAN(addr, bits, name, si, chn) { \
682*4882a593Smuzhiyun .type = IIO_VOLTAGE, \
683*4882a593Smuzhiyun .indexed = 1, \
684*4882a593Smuzhiyun .channel = chn, \
685*4882a593Smuzhiyun .extend_name = name, \
686*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
687*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE), \
688*4882a593Smuzhiyun .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
689*4882a593Smuzhiyun .address = (addr), \
690*4882a593Smuzhiyun .scan_index = (si), \
691*4882a593Smuzhiyun .scan_type = { \
692*4882a593Smuzhiyun .sign = 'u', \
693*4882a593Smuzhiyun .realbits = (bits), \
694*4882a593Smuzhiyun .storagebits = 16, \
695*4882a593Smuzhiyun .shift = 0, \
696*4882a593Smuzhiyun .endianness = IIO_BE, \
697*4882a593Smuzhiyun }, \
698*4882a593Smuzhiyun }
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun #define ADIS16400_SUPPLY_CHAN(addr, bits) \
701*4882a593Smuzhiyun ADIS16400_VOLTAGE_CHAN(addr, bits, "supply", ADIS16400_SCAN_SUPPLY, 0)
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun #define ADIS16400_AUX_ADC_CHAN(addr, bits) \
704*4882a593Smuzhiyun ADIS16400_VOLTAGE_CHAN(addr, bits, NULL, ADIS16400_SCAN_ADC, 1)
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun #define ADIS16400_GYRO_CHAN(mod, addr, bits) { \
707*4882a593Smuzhiyun .type = IIO_ANGL_VEL, \
708*4882a593Smuzhiyun .modified = 1, \
709*4882a593Smuzhiyun .channel2 = IIO_MOD_ ## mod, \
710*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
711*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBBIAS), \
712*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
713*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
714*4882a593Smuzhiyun .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
715*4882a593Smuzhiyun .address = addr, \
716*4882a593Smuzhiyun .scan_index = ADIS16400_SCAN_GYRO_ ## mod, \
717*4882a593Smuzhiyun .scan_type = { \
718*4882a593Smuzhiyun .sign = 's', \
719*4882a593Smuzhiyun .realbits = (bits), \
720*4882a593Smuzhiyun .storagebits = 16, \
721*4882a593Smuzhiyun .shift = 0, \
722*4882a593Smuzhiyun .endianness = IIO_BE, \
723*4882a593Smuzhiyun }, \
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun #define ADIS16400_ACCEL_CHAN(mod, addr, bits) { \
727*4882a593Smuzhiyun .type = IIO_ACCEL, \
728*4882a593Smuzhiyun .modified = 1, \
729*4882a593Smuzhiyun .channel2 = IIO_MOD_ ## mod, \
730*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
731*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBBIAS), \
732*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
733*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
734*4882a593Smuzhiyun .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
735*4882a593Smuzhiyun .address = (addr), \
736*4882a593Smuzhiyun .scan_index = ADIS16400_SCAN_ACC_ ## mod, \
737*4882a593Smuzhiyun .scan_type = { \
738*4882a593Smuzhiyun .sign = 's', \
739*4882a593Smuzhiyun .realbits = (bits), \
740*4882a593Smuzhiyun .storagebits = 16, \
741*4882a593Smuzhiyun .shift = 0, \
742*4882a593Smuzhiyun .endianness = IIO_BE, \
743*4882a593Smuzhiyun }, \
744*4882a593Smuzhiyun }
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun #define ADIS16400_MAGN_CHAN(mod, addr, bits) { \
747*4882a593Smuzhiyun .type = IIO_MAGN, \
748*4882a593Smuzhiyun .modified = 1, \
749*4882a593Smuzhiyun .channel2 = IIO_MOD_ ## mod, \
750*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
751*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
752*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
753*4882a593Smuzhiyun .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
754*4882a593Smuzhiyun .address = (addr), \
755*4882a593Smuzhiyun .scan_index = ADIS16400_SCAN_MAGN_ ## mod, \
756*4882a593Smuzhiyun .scan_type = { \
757*4882a593Smuzhiyun .sign = 's', \
758*4882a593Smuzhiyun .realbits = (bits), \
759*4882a593Smuzhiyun .storagebits = 16, \
760*4882a593Smuzhiyun .shift = 0, \
761*4882a593Smuzhiyun .endianness = IIO_BE, \
762*4882a593Smuzhiyun }, \
763*4882a593Smuzhiyun }
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun #define ADIS16400_MOD_TEMP_NAME_X "x"
766*4882a593Smuzhiyun #define ADIS16400_MOD_TEMP_NAME_Y "y"
767*4882a593Smuzhiyun #define ADIS16400_MOD_TEMP_NAME_Z "z"
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun #define ADIS16400_MOD_TEMP_CHAN(mod, addr, bits) { \
770*4882a593Smuzhiyun .type = IIO_TEMP, \
771*4882a593Smuzhiyun .indexed = 1, \
772*4882a593Smuzhiyun .channel = 0, \
773*4882a593Smuzhiyun .extend_name = ADIS16400_MOD_TEMP_NAME_ ## mod, \
774*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
775*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_OFFSET) | \
776*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE), \
777*4882a593Smuzhiyun .info_mask_shared_by_type = \
778*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
779*4882a593Smuzhiyun .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
780*4882a593Smuzhiyun .address = (addr), \
781*4882a593Smuzhiyun .scan_index = ADIS16350_SCAN_TEMP_ ## mod, \
782*4882a593Smuzhiyun .scan_type = { \
783*4882a593Smuzhiyun .sign = 's', \
784*4882a593Smuzhiyun .realbits = (bits), \
785*4882a593Smuzhiyun .storagebits = 16, \
786*4882a593Smuzhiyun .shift = 0, \
787*4882a593Smuzhiyun .endianness = IIO_BE, \
788*4882a593Smuzhiyun }, \
789*4882a593Smuzhiyun }
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun #define ADIS16400_TEMP_CHAN(addr, bits) { \
792*4882a593Smuzhiyun .type = IIO_TEMP, \
793*4882a593Smuzhiyun .indexed = 1, \
794*4882a593Smuzhiyun .channel = 0, \
795*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
796*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_OFFSET) | \
797*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE), \
798*4882a593Smuzhiyun .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
799*4882a593Smuzhiyun .address = (addr), \
800*4882a593Smuzhiyun .scan_index = ADIS16350_SCAN_TEMP_X, \
801*4882a593Smuzhiyun .scan_type = { \
802*4882a593Smuzhiyun .sign = 's', \
803*4882a593Smuzhiyun .realbits = (bits), \
804*4882a593Smuzhiyun .storagebits = 16, \
805*4882a593Smuzhiyun .shift = 0, \
806*4882a593Smuzhiyun .endianness = IIO_BE, \
807*4882a593Smuzhiyun }, \
808*4882a593Smuzhiyun }
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun #define ADIS16400_INCLI_CHAN(mod, addr, bits) { \
811*4882a593Smuzhiyun .type = IIO_INCLI, \
812*4882a593Smuzhiyun .modified = 1, \
813*4882a593Smuzhiyun .channel2 = IIO_MOD_ ## mod, \
814*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
815*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
816*4882a593Smuzhiyun .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
817*4882a593Smuzhiyun .address = (addr), \
818*4882a593Smuzhiyun .scan_index = ADIS16300_SCAN_INCLI_ ## mod, \
819*4882a593Smuzhiyun .scan_type = { \
820*4882a593Smuzhiyun .sign = 's', \
821*4882a593Smuzhiyun .realbits = (bits), \
822*4882a593Smuzhiyun .storagebits = 16, \
823*4882a593Smuzhiyun .shift = 0, \
824*4882a593Smuzhiyun .endianness = IIO_BE, \
825*4882a593Smuzhiyun }, \
826*4882a593Smuzhiyun }
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun static const struct iio_chan_spec adis16400_channels[] = {
829*4882a593Smuzhiyun ADIS16400_SUPPLY_CHAN(ADIS16400_SUPPLY_OUT, 14),
830*4882a593Smuzhiyun ADIS16400_GYRO_CHAN(X, ADIS16400_XGYRO_OUT, 14),
831*4882a593Smuzhiyun ADIS16400_GYRO_CHAN(Y, ADIS16400_YGYRO_OUT, 14),
832*4882a593Smuzhiyun ADIS16400_GYRO_CHAN(Z, ADIS16400_ZGYRO_OUT, 14),
833*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(X, ADIS16400_XACCL_OUT, 14),
834*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(Y, ADIS16400_YACCL_OUT, 14),
835*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(Z, ADIS16400_ZACCL_OUT, 14),
836*4882a593Smuzhiyun ADIS16400_MAGN_CHAN(X, ADIS16400_XMAGN_OUT, 14),
837*4882a593Smuzhiyun ADIS16400_MAGN_CHAN(Y, ADIS16400_YMAGN_OUT, 14),
838*4882a593Smuzhiyun ADIS16400_MAGN_CHAN(Z, ADIS16400_ZMAGN_OUT, 14),
839*4882a593Smuzhiyun ADIS16400_TEMP_CHAN(ADIS16400_TEMP_OUT, 12),
840*4882a593Smuzhiyun ADIS16400_AUX_ADC_CHAN(ADIS16400_AUX_ADC, 12),
841*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(ADIS16400_SCAN_TIMESTAMP),
842*4882a593Smuzhiyun };
843*4882a593Smuzhiyun
844*4882a593Smuzhiyun static const struct iio_chan_spec adis16445_channels[] = {
845*4882a593Smuzhiyun ADIS16400_GYRO_CHAN(X, ADIS16400_XGYRO_OUT, 16),
846*4882a593Smuzhiyun ADIS16400_GYRO_CHAN(Y, ADIS16400_YGYRO_OUT, 16),
847*4882a593Smuzhiyun ADIS16400_GYRO_CHAN(Z, ADIS16400_ZGYRO_OUT, 16),
848*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(X, ADIS16400_XACCL_OUT, 16),
849*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(Y, ADIS16400_YACCL_OUT, 16),
850*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(Z, ADIS16400_ZACCL_OUT, 16),
851*4882a593Smuzhiyun ADIS16400_TEMP_CHAN(ADIS16448_TEMP_OUT, 12),
852*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(ADIS16400_SCAN_TIMESTAMP),
853*4882a593Smuzhiyun };
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun static const struct iio_chan_spec adis16448_channels[] = {
856*4882a593Smuzhiyun ADIS16400_GYRO_CHAN(X, ADIS16400_XGYRO_OUT, 16),
857*4882a593Smuzhiyun ADIS16400_GYRO_CHAN(Y, ADIS16400_YGYRO_OUT, 16),
858*4882a593Smuzhiyun ADIS16400_GYRO_CHAN(Z, ADIS16400_ZGYRO_OUT, 16),
859*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(X, ADIS16400_XACCL_OUT, 16),
860*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(Y, ADIS16400_YACCL_OUT, 16),
861*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(Z, ADIS16400_ZACCL_OUT, 16),
862*4882a593Smuzhiyun ADIS16400_MAGN_CHAN(X, ADIS16400_XMAGN_OUT, 16),
863*4882a593Smuzhiyun ADIS16400_MAGN_CHAN(Y, ADIS16400_YMAGN_OUT, 16),
864*4882a593Smuzhiyun ADIS16400_MAGN_CHAN(Z, ADIS16400_ZMAGN_OUT, 16),
865*4882a593Smuzhiyun {
866*4882a593Smuzhiyun .type = IIO_PRESSURE,
867*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
868*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
869*4882a593Smuzhiyun .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
870*4882a593Smuzhiyun .address = ADIS16448_BARO_OUT,
871*4882a593Smuzhiyun .scan_index = ADIS16400_SCAN_BARO,
872*4882a593Smuzhiyun .scan_type = {
873*4882a593Smuzhiyun .sign = 's',
874*4882a593Smuzhiyun .realbits = 16,
875*4882a593Smuzhiyun .storagebits = 16,
876*4882a593Smuzhiyun .endianness = IIO_BE,
877*4882a593Smuzhiyun },
878*4882a593Smuzhiyun },
879*4882a593Smuzhiyun ADIS16400_TEMP_CHAN(ADIS16448_TEMP_OUT, 12),
880*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(ADIS16400_SCAN_TIMESTAMP),
881*4882a593Smuzhiyun };
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun static const struct iio_chan_spec adis16350_channels[] = {
884*4882a593Smuzhiyun ADIS16400_SUPPLY_CHAN(ADIS16400_SUPPLY_OUT, 12),
885*4882a593Smuzhiyun ADIS16400_GYRO_CHAN(X, ADIS16400_XGYRO_OUT, 14),
886*4882a593Smuzhiyun ADIS16400_GYRO_CHAN(Y, ADIS16400_YGYRO_OUT, 14),
887*4882a593Smuzhiyun ADIS16400_GYRO_CHAN(Z, ADIS16400_ZGYRO_OUT, 14),
888*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(X, ADIS16400_XACCL_OUT, 14),
889*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(Y, ADIS16400_YACCL_OUT, 14),
890*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(Z, ADIS16400_ZACCL_OUT, 14),
891*4882a593Smuzhiyun ADIS16400_MAGN_CHAN(X, ADIS16400_XMAGN_OUT, 14),
892*4882a593Smuzhiyun ADIS16400_MAGN_CHAN(Y, ADIS16400_YMAGN_OUT, 14),
893*4882a593Smuzhiyun ADIS16400_MAGN_CHAN(Z, ADIS16400_ZMAGN_OUT, 14),
894*4882a593Smuzhiyun ADIS16400_AUX_ADC_CHAN(ADIS16300_AUX_ADC, 12),
895*4882a593Smuzhiyun ADIS16400_MOD_TEMP_CHAN(X, ADIS16350_XTEMP_OUT, 12),
896*4882a593Smuzhiyun ADIS16400_MOD_TEMP_CHAN(Y, ADIS16350_YTEMP_OUT, 12),
897*4882a593Smuzhiyun ADIS16400_MOD_TEMP_CHAN(Z, ADIS16350_ZTEMP_OUT, 12),
898*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(ADIS16400_SCAN_TIMESTAMP),
899*4882a593Smuzhiyun };
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun static const struct iio_chan_spec adis16300_channels[] = {
902*4882a593Smuzhiyun ADIS16400_SUPPLY_CHAN(ADIS16400_SUPPLY_OUT, 12),
903*4882a593Smuzhiyun ADIS16400_GYRO_CHAN(X, ADIS16400_XGYRO_OUT, 14),
904*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(X, ADIS16400_XACCL_OUT, 14),
905*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(Y, ADIS16400_YACCL_OUT, 14),
906*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(Z, ADIS16400_ZACCL_OUT, 14),
907*4882a593Smuzhiyun ADIS16400_TEMP_CHAN(ADIS16350_XTEMP_OUT, 12),
908*4882a593Smuzhiyun ADIS16400_AUX_ADC_CHAN(ADIS16300_AUX_ADC, 12),
909*4882a593Smuzhiyun ADIS16400_INCLI_CHAN(X, ADIS16300_PITCH_OUT, 13),
910*4882a593Smuzhiyun ADIS16400_INCLI_CHAN(Y, ADIS16300_ROLL_OUT, 13),
911*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(ADIS16400_SCAN_TIMESTAMP),
912*4882a593Smuzhiyun };
913*4882a593Smuzhiyun
914*4882a593Smuzhiyun static const struct iio_chan_spec adis16334_channels[] = {
915*4882a593Smuzhiyun ADIS16400_GYRO_CHAN(X, ADIS16400_XGYRO_OUT, 14),
916*4882a593Smuzhiyun ADIS16400_GYRO_CHAN(Y, ADIS16400_YGYRO_OUT, 14),
917*4882a593Smuzhiyun ADIS16400_GYRO_CHAN(Z, ADIS16400_ZGYRO_OUT, 14),
918*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(X, ADIS16400_XACCL_OUT, 14),
919*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(Y, ADIS16400_YACCL_OUT, 14),
920*4882a593Smuzhiyun ADIS16400_ACCEL_CHAN(Z, ADIS16400_ZACCL_OUT, 14),
921*4882a593Smuzhiyun ADIS16400_TEMP_CHAN(ADIS16350_XTEMP_OUT, 12),
922*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(ADIS16400_SCAN_TIMESTAMP),
923*4882a593Smuzhiyun };
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun static const char * const adis16400_status_error_msgs[] = {
926*4882a593Smuzhiyun [ADIS16400_DIAG_STAT_ZACCL_FAIL] = "Z-axis accelerometer self-test failure",
927*4882a593Smuzhiyun [ADIS16400_DIAG_STAT_YACCL_FAIL] = "Y-axis accelerometer self-test failure",
928*4882a593Smuzhiyun [ADIS16400_DIAG_STAT_XACCL_FAIL] = "X-axis accelerometer self-test failure",
929*4882a593Smuzhiyun [ADIS16400_DIAG_STAT_XGYRO_FAIL] = "X-axis gyroscope self-test failure",
930*4882a593Smuzhiyun [ADIS16400_DIAG_STAT_YGYRO_FAIL] = "Y-axis gyroscope self-test failure",
931*4882a593Smuzhiyun [ADIS16400_DIAG_STAT_ZGYRO_FAIL] = "Z-axis gyroscope self-test failure",
932*4882a593Smuzhiyun [ADIS16400_DIAG_STAT_ALARM2] = "Alarm 2 active",
933*4882a593Smuzhiyun [ADIS16400_DIAG_STAT_ALARM1] = "Alarm 1 active",
934*4882a593Smuzhiyun [ADIS16400_DIAG_STAT_FLASH_CHK] = "Flash checksum error",
935*4882a593Smuzhiyun [ADIS16400_DIAG_STAT_SELF_TEST] = "Self test error",
936*4882a593Smuzhiyun [ADIS16400_DIAG_STAT_OVERFLOW] = "Sensor overrange",
937*4882a593Smuzhiyun [ADIS16400_DIAG_STAT_SPI_FAIL] = "SPI failure",
938*4882a593Smuzhiyun [ADIS16400_DIAG_STAT_FLASH_UPT] = "Flash update failed",
939*4882a593Smuzhiyun [ADIS16400_DIAG_STAT_POWER_HIGH] = "Power supply above 5.25V",
940*4882a593Smuzhiyun [ADIS16400_DIAG_STAT_POWER_LOW] = "Power supply below 4.75V",
941*4882a593Smuzhiyun };
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun #define ADIS16400_DATA(_timeouts, _burst_len) \
944*4882a593Smuzhiyun { \
945*4882a593Smuzhiyun .msc_ctrl_reg = ADIS16400_MSC_CTRL, \
946*4882a593Smuzhiyun .glob_cmd_reg = ADIS16400_GLOB_CMD, \
947*4882a593Smuzhiyun .diag_stat_reg = ADIS16400_DIAG_STAT, \
948*4882a593Smuzhiyun .read_delay = 50, \
949*4882a593Smuzhiyun .write_delay = 50, \
950*4882a593Smuzhiyun .self_test_mask = ADIS16400_MSC_CTRL_MEM_TEST, \
951*4882a593Smuzhiyun .self_test_reg = ADIS16400_MSC_CTRL, \
952*4882a593Smuzhiyun .status_error_msgs = adis16400_status_error_msgs, \
953*4882a593Smuzhiyun .status_error_mask = BIT(ADIS16400_DIAG_STAT_ZACCL_FAIL) | \
954*4882a593Smuzhiyun BIT(ADIS16400_DIAG_STAT_YACCL_FAIL) | \
955*4882a593Smuzhiyun BIT(ADIS16400_DIAG_STAT_XACCL_FAIL) | \
956*4882a593Smuzhiyun BIT(ADIS16400_DIAG_STAT_XGYRO_FAIL) | \
957*4882a593Smuzhiyun BIT(ADIS16400_DIAG_STAT_YGYRO_FAIL) | \
958*4882a593Smuzhiyun BIT(ADIS16400_DIAG_STAT_ZGYRO_FAIL) | \
959*4882a593Smuzhiyun BIT(ADIS16400_DIAG_STAT_ALARM2) | \
960*4882a593Smuzhiyun BIT(ADIS16400_DIAG_STAT_ALARM1) | \
961*4882a593Smuzhiyun BIT(ADIS16400_DIAG_STAT_FLASH_CHK) | \
962*4882a593Smuzhiyun BIT(ADIS16400_DIAG_STAT_SELF_TEST) | \
963*4882a593Smuzhiyun BIT(ADIS16400_DIAG_STAT_OVERFLOW) | \
964*4882a593Smuzhiyun BIT(ADIS16400_DIAG_STAT_SPI_FAIL) | \
965*4882a593Smuzhiyun BIT(ADIS16400_DIAG_STAT_FLASH_UPT) | \
966*4882a593Smuzhiyun BIT(ADIS16400_DIAG_STAT_POWER_HIGH) | \
967*4882a593Smuzhiyun BIT(ADIS16400_DIAG_STAT_POWER_LOW), \
968*4882a593Smuzhiyun .timeouts = (_timeouts), \
969*4882a593Smuzhiyun .burst_reg_cmd = ADIS16400_GLOB_CMD, \
970*4882a593Smuzhiyun .burst_len = (_burst_len) \
971*4882a593Smuzhiyun }
972*4882a593Smuzhiyun
973*4882a593Smuzhiyun static const struct adis_timeout adis16300_timeouts = {
974*4882a593Smuzhiyun .reset_ms = ADIS16400_STARTUP_DELAY,
975*4882a593Smuzhiyun .sw_reset_ms = ADIS16400_STARTUP_DELAY,
976*4882a593Smuzhiyun .self_test_ms = ADIS16400_STARTUP_DELAY,
977*4882a593Smuzhiyun };
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun static const struct adis_timeout adis16334_timeouts = {
980*4882a593Smuzhiyun .reset_ms = 60,
981*4882a593Smuzhiyun .sw_reset_ms = 60,
982*4882a593Smuzhiyun .self_test_ms = 14,
983*4882a593Smuzhiyun };
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun static const struct adis_timeout adis16362_timeouts = {
986*4882a593Smuzhiyun .reset_ms = 130,
987*4882a593Smuzhiyun .sw_reset_ms = 130,
988*4882a593Smuzhiyun .self_test_ms = 12,
989*4882a593Smuzhiyun };
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun static const struct adis_timeout adis16400_timeouts = {
992*4882a593Smuzhiyun .reset_ms = 170,
993*4882a593Smuzhiyun .sw_reset_ms = 170,
994*4882a593Smuzhiyun .self_test_ms = 12,
995*4882a593Smuzhiyun };
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun static const struct adis_timeout adis16445_timeouts = {
998*4882a593Smuzhiyun .reset_ms = 55,
999*4882a593Smuzhiyun .sw_reset_ms = 55,
1000*4882a593Smuzhiyun .self_test_ms = 16,
1001*4882a593Smuzhiyun };
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun static const struct adis_timeout adis16448_timeouts = {
1004*4882a593Smuzhiyun .reset_ms = 90,
1005*4882a593Smuzhiyun .sw_reset_ms = 90,
1006*4882a593Smuzhiyun .self_test_ms = 45,
1007*4882a593Smuzhiyun };
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun static struct adis16400_chip_info adis16400_chips[] = {
1010*4882a593Smuzhiyun [ADIS16300] = {
1011*4882a593Smuzhiyun .channels = adis16300_channels,
1012*4882a593Smuzhiyun .num_channels = ARRAY_SIZE(adis16300_channels),
1013*4882a593Smuzhiyun .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE |
1014*4882a593Smuzhiyun ADIS16400_HAS_SERIAL_NUMBER,
1015*4882a593Smuzhiyun .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1016*4882a593Smuzhiyun .accel_scale_micro = 5884,
1017*4882a593Smuzhiyun .temp_scale_nano = 140000000, /* 0.14 C */
1018*4882a593Smuzhiyun .temp_offset = 25000000 / 140000, /* 25 C = 0x00 */
1019*4882a593Smuzhiyun .set_freq = adis16400_set_freq,
1020*4882a593Smuzhiyun .get_freq = adis16400_get_freq,
1021*4882a593Smuzhiyun .adis_data = ADIS16400_DATA(&adis16300_timeouts, 18),
1022*4882a593Smuzhiyun },
1023*4882a593Smuzhiyun [ADIS16334] = {
1024*4882a593Smuzhiyun .channels = adis16334_channels,
1025*4882a593Smuzhiyun .num_channels = ARRAY_SIZE(adis16334_channels),
1026*4882a593Smuzhiyun .flags = ADIS16400_HAS_PROD_ID | ADIS16400_NO_BURST |
1027*4882a593Smuzhiyun ADIS16400_HAS_SERIAL_NUMBER,
1028*4882a593Smuzhiyun .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1029*4882a593Smuzhiyun .accel_scale_micro = IIO_G_TO_M_S_2(1000), /* 1 mg */
1030*4882a593Smuzhiyun .temp_scale_nano = 67850000, /* 0.06785 C */
1031*4882a593Smuzhiyun .temp_offset = 25000000 / 67850, /* 25 C = 0x00 */
1032*4882a593Smuzhiyun .set_freq = adis16334_set_freq,
1033*4882a593Smuzhiyun .get_freq = adis16334_get_freq,
1034*4882a593Smuzhiyun .adis_data = ADIS16400_DATA(&adis16334_timeouts, 0),
1035*4882a593Smuzhiyun },
1036*4882a593Smuzhiyun [ADIS16350] = {
1037*4882a593Smuzhiyun .channels = adis16350_channels,
1038*4882a593Smuzhiyun .num_channels = ARRAY_SIZE(adis16350_channels),
1039*4882a593Smuzhiyun .gyro_scale_micro = IIO_DEGREE_TO_RAD(73260), /* 0.07326 deg/s */
1040*4882a593Smuzhiyun .accel_scale_micro = IIO_G_TO_M_S_2(2522), /* 0.002522 g */
1041*4882a593Smuzhiyun .temp_scale_nano = 145300000, /* 0.1453 C */
1042*4882a593Smuzhiyun .temp_offset = 25000000 / 145300, /* 25 C = 0x00 */
1043*4882a593Smuzhiyun .flags = ADIS16400_NO_BURST | ADIS16400_HAS_SLOW_MODE,
1044*4882a593Smuzhiyun .set_freq = adis16400_set_freq,
1045*4882a593Smuzhiyun .get_freq = adis16400_get_freq,
1046*4882a593Smuzhiyun .adis_data = ADIS16400_DATA(&adis16300_timeouts, 0),
1047*4882a593Smuzhiyun },
1048*4882a593Smuzhiyun [ADIS16360] = {
1049*4882a593Smuzhiyun .channels = adis16350_channels,
1050*4882a593Smuzhiyun .num_channels = ARRAY_SIZE(adis16350_channels),
1051*4882a593Smuzhiyun .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE |
1052*4882a593Smuzhiyun ADIS16400_HAS_SERIAL_NUMBER,
1053*4882a593Smuzhiyun .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1054*4882a593Smuzhiyun .accel_scale_micro = IIO_G_TO_M_S_2(3333), /* 3.333 mg */
1055*4882a593Smuzhiyun .temp_scale_nano = 136000000, /* 0.136 C */
1056*4882a593Smuzhiyun .temp_offset = 25000000 / 136000, /* 25 C = 0x00 */
1057*4882a593Smuzhiyun .set_freq = adis16400_set_freq,
1058*4882a593Smuzhiyun .get_freq = adis16400_get_freq,
1059*4882a593Smuzhiyun .adis_data = ADIS16400_DATA(&adis16300_timeouts, 28),
1060*4882a593Smuzhiyun },
1061*4882a593Smuzhiyun [ADIS16362] = {
1062*4882a593Smuzhiyun .channels = adis16350_channels,
1063*4882a593Smuzhiyun .num_channels = ARRAY_SIZE(adis16350_channels),
1064*4882a593Smuzhiyun .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE |
1065*4882a593Smuzhiyun ADIS16400_HAS_SERIAL_NUMBER,
1066*4882a593Smuzhiyun .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1067*4882a593Smuzhiyun .accel_scale_micro = IIO_G_TO_M_S_2(333), /* 0.333 mg */
1068*4882a593Smuzhiyun .temp_scale_nano = 136000000, /* 0.136 C */
1069*4882a593Smuzhiyun .temp_offset = 25000000 / 136000, /* 25 C = 0x00 */
1070*4882a593Smuzhiyun .set_freq = adis16400_set_freq,
1071*4882a593Smuzhiyun .get_freq = adis16400_get_freq,
1072*4882a593Smuzhiyun .adis_data = ADIS16400_DATA(&adis16362_timeouts, 28),
1073*4882a593Smuzhiyun },
1074*4882a593Smuzhiyun [ADIS16364] = {
1075*4882a593Smuzhiyun .channels = adis16350_channels,
1076*4882a593Smuzhiyun .num_channels = ARRAY_SIZE(adis16350_channels),
1077*4882a593Smuzhiyun .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE |
1078*4882a593Smuzhiyun ADIS16400_HAS_SERIAL_NUMBER,
1079*4882a593Smuzhiyun .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1080*4882a593Smuzhiyun .accel_scale_micro = IIO_G_TO_M_S_2(1000), /* 1 mg */
1081*4882a593Smuzhiyun .temp_scale_nano = 136000000, /* 0.136 C */
1082*4882a593Smuzhiyun .temp_offset = 25000000 / 136000, /* 25 C = 0x00 */
1083*4882a593Smuzhiyun .set_freq = adis16400_set_freq,
1084*4882a593Smuzhiyun .get_freq = adis16400_get_freq,
1085*4882a593Smuzhiyun .adis_data = ADIS16400_DATA(&adis16362_timeouts, 28),
1086*4882a593Smuzhiyun },
1087*4882a593Smuzhiyun [ADIS16367] = {
1088*4882a593Smuzhiyun .channels = adis16350_channels,
1089*4882a593Smuzhiyun .num_channels = ARRAY_SIZE(adis16350_channels),
1090*4882a593Smuzhiyun .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE |
1091*4882a593Smuzhiyun ADIS16400_HAS_SERIAL_NUMBER,
1092*4882a593Smuzhiyun .gyro_scale_micro = IIO_DEGREE_TO_RAD(2000), /* 0.2 deg/s */
1093*4882a593Smuzhiyun .accel_scale_micro = IIO_G_TO_M_S_2(3333), /* 3.333 mg */
1094*4882a593Smuzhiyun .temp_scale_nano = 136000000, /* 0.136 C */
1095*4882a593Smuzhiyun .temp_offset = 25000000 / 136000, /* 25 C = 0x00 */
1096*4882a593Smuzhiyun .set_freq = adis16400_set_freq,
1097*4882a593Smuzhiyun .get_freq = adis16400_get_freq,
1098*4882a593Smuzhiyun .adis_data = ADIS16400_DATA(&adis16300_timeouts, 28),
1099*4882a593Smuzhiyun },
1100*4882a593Smuzhiyun [ADIS16400] = {
1101*4882a593Smuzhiyun .channels = adis16400_channels,
1102*4882a593Smuzhiyun .num_channels = ARRAY_SIZE(adis16400_channels),
1103*4882a593Smuzhiyun .flags = ADIS16400_HAS_PROD_ID | ADIS16400_HAS_SLOW_MODE,
1104*4882a593Smuzhiyun .gyro_scale_micro = IIO_DEGREE_TO_RAD(50000), /* 0.05 deg/s */
1105*4882a593Smuzhiyun .accel_scale_micro = IIO_G_TO_M_S_2(3333), /* 3.333 mg */
1106*4882a593Smuzhiyun .temp_scale_nano = 140000000, /* 0.14 C */
1107*4882a593Smuzhiyun .temp_offset = 25000000 / 140000, /* 25 C = 0x00 */
1108*4882a593Smuzhiyun .set_freq = adis16400_set_freq,
1109*4882a593Smuzhiyun .get_freq = adis16400_get_freq,
1110*4882a593Smuzhiyun .adis_data = ADIS16400_DATA(&adis16400_timeouts, 24),
1111*4882a593Smuzhiyun },
1112*4882a593Smuzhiyun [ADIS16445] = {
1113*4882a593Smuzhiyun .channels = adis16445_channels,
1114*4882a593Smuzhiyun .num_channels = ARRAY_SIZE(adis16445_channels),
1115*4882a593Smuzhiyun .flags = ADIS16400_HAS_PROD_ID |
1116*4882a593Smuzhiyun ADIS16400_HAS_SERIAL_NUMBER |
1117*4882a593Smuzhiyun ADIS16400_BURST_DIAG_STAT,
1118*4882a593Smuzhiyun .gyro_scale_micro = IIO_DEGREE_TO_RAD(10000), /* 0.01 deg/s */
1119*4882a593Smuzhiyun .accel_scale_micro = IIO_G_TO_M_S_2(250), /* 1/4000 g */
1120*4882a593Smuzhiyun .temp_scale_nano = 73860000, /* 0.07386 C */
1121*4882a593Smuzhiyun .temp_offset = 31000000 / 73860, /* 31 C = 0x00 */
1122*4882a593Smuzhiyun .set_freq = adis16334_set_freq,
1123*4882a593Smuzhiyun .get_freq = adis16334_get_freq,
1124*4882a593Smuzhiyun .adis_data = ADIS16400_DATA(&adis16445_timeouts, 16),
1125*4882a593Smuzhiyun },
1126*4882a593Smuzhiyun [ADIS16448] = {
1127*4882a593Smuzhiyun .channels = adis16448_channels,
1128*4882a593Smuzhiyun .num_channels = ARRAY_SIZE(adis16448_channels),
1129*4882a593Smuzhiyun .flags = ADIS16400_HAS_PROD_ID |
1130*4882a593Smuzhiyun ADIS16400_HAS_SERIAL_NUMBER |
1131*4882a593Smuzhiyun ADIS16400_BURST_DIAG_STAT,
1132*4882a593Smuzhiyun .gyro_scale_micro = IIO_DEGREE_TO_RAD(40000), /* 0.04 deg/s */
1133*4882a593Smuzhiyun .accel_scale_micro = IIO_G_TO_M_S_2(833), /* 1/1200 g */
1134*4882a593Smuzhiyun .temp_scale_nano = 73860000, /* 0.07386 C */
1135*4882a593Smuzhiyun .temp_offset = 31000000 / 73860, /* 31 C = 0x00 */
1136*4882a593Smuzhiyun .set_freq = adis16334_set_freq,
1137*4882a593Smuzhiyun .get_freq = adis16334_get_freq,
1138*4882a593Smuzhiyun .adis_data = ADIS16400_DATA(&adis16448_timeouts, 24),
1139*4882a593Smuzhiyun }
1140*4882a593Smuzhiyun };
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun static const struct iio_info adis16400_info = {
1143*4882a593Smuzhiyun .read_raw = &adis16400_read_raw,
1144*4882a593Smuzhiyun .write_raw = &adis16400_write_raw,
1145*4882a593Smuzhiyun .update_scan_mode = adis_update_scan_mode,
1146*4882a593Smuzhiyun .debugfs_reg_access = adis_debugfs_reg_access,
1147*4882a593Smuzhiyun };
1148*4882a593Smuzhiyun
adis16400_setup_chan_mask(struct adis16400_state * st)1149*4882a593Smuzhiyun static void adis16400_setup_chan_mask(struct adis16400_state *st)
1150*4882a593Smuzhiyun {
1151*4882a593Smuzhiyun const struct adis16400_chip_info *chip_info = st->variant;
1152*4882a593Smuzhiyun unsigned int i;
1153*4882a593Smuzhiyun
1154*4882a593Smuzhiyun for (i = 0; i < chip_info->num_channels; i++) {
1155*4882a593Smuzhiyun const struct iio_chan_spec *ch = &chip_info->channels[i];
1156*4882a593Smuzhiyun
1157*4882a593Smuzhiyun if (ch->scan_index >= 0 &&
1158*4882a593Smuzhiyun ch->scan_index != ADIS16400_SCAN_TIMESTAMP)
1159*4882a593Smuzhiyun st->avail_scan_mask[0] |= BIT(ch->scan_index);
1160*4882a593Smuzhiyun }
1161*4882a593Smuzhiyun }
1162*4882a593Smuzhiyun
adis16400_stop(void * data)1163*4882a593Smuzhiyun static void adis16400_stop(void *data)
1164*4882a593Smuzhiyun {
1165*4882a593Smuzhiyun adis16400_stop_device(data);
1166*4882a593Smuzhiyun }
1167*4882a593Smuzhiyun
adis16400_probe(struct spi_device * spi)1168*4882a593Smuzhiyun static int adis16400_probe(struct spi_device *spi)
1169*4882a593Smuzhiyun {
1170*4882a593Smuzhiyun struct adis16400_state *st;
1171*4882a593Smuzhiyun struct iio_dev *indio_dev;
1172*4882a593Smuzhiyun int ret;
1173*4882a593Smuzhiyun const struct adis_data *adis16400_data;
1174*4882a593Smuzhiyun
1175*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1176*4882a593Smuzhiyun if (indio_dev == NULL)
1177*4882a593Smuzhiyun return -ENOMEM;
1178*4882a593Smuzhiyun
1179*4882a593Smuzhiyun st = iio_priv(indio_dev);
1180*4882a593Smuzhiyun /* this is only used for removal purposes */
1181*4882a593Smuzhiyun spi_set_drvdata(spi, indio_dev);
1182*4882a593Smuzhiyun
1183*4882a593Smuzhiyun /* setup the industrialio driver allocated elements */
1184*4882a593Smuzhiyun st->variant = &adis16400_chips[spi_get_device_id(spi)->driver_data];
1185*4882a593Smuzhiyun indio_dev->name = spi_get_device_id(spi)->name;
1186*4882a593Smuzhiyun indio_dev->channels = st->variant->channels;
1187*4882a593Smuzhiyun indio_dev->num_channels = st->variant->num_channels;
1188*4882a593Smuzhiyun indio_dev->info = &adis16400_info;
1189*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
1190*4882a593Smuzhiyun
1191*4882a593Smuzhiyun if (!(st->variant->flags & ADIS16400_NO_BURST)) {
1192*4882a593Smuzhiyun adis16400_setup_chan_mask(st);
1193*4882a593Smuzhiyun indio_dev->available_scan_masks = st->avail_scan_mask;
1194*4882a593Smuzhiyun }
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun adis16400_data = &st->variant->adis_data;
1197*4882a593Smuzhiyun
1198*4882a593Smuzhiyun ret = adis_init(&st->adis, indio_dev, spi, adis16400_data);
1199*4882a593Smuzhiyun if (ret)
1200*4882a593Smuzhiyun return ret;
1201*4882a593Smuzhiyun
1202*4882a593Smuzhiyun ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, adis16400_trigger_handler);
1203*4882a593Smuzhiyun if (ret)
1204*4882a593Smuzhiyun return ret;
1205*4882a593Smuzhiyun
1206*4882a593Smuzhiyun /* Get the device into a sane initial state */
1207*4882a593Smuzhiyun ret = adis16400_initial_setup(indio_dev);
1208*4882a593Smuzhiyun if (ret)
1209*4882a593Smuzhiyun return ret;
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun ret = devm_add_action_or_reset(&spi->dev, adis16400_stop, indio_dev);
1212*4882a593Smuzhiyun if (ret)
1213*4882a593Smuzhiyun return ret;
1214*4882a593Smuzhiyun
1215*4882a593Smuzhiyun ret = devm_iio_device_register(&spi->dev, indio_dev);
1216*4882a593Smuzhiyun if (ret)
1217*4882a593Smuzhiyun return ret;
1218*4882a593Smuzhiyun
1219*4882a593Smuzhiyun adis16400_debugfs_init(indio_dev);
1220*4882a593Smuzhiyun return 0;
1221*4882a593Smuzhiyun }
1222*4882a593Smuzhiyun
1223*4882a593Smuzhiyun static const struct spi_device_id adis16400_id[] = {
1224*4882a593Smuzhiyun {"adis16300", ADIS16300},
1225*4882a593Smuzhiyun {"adis16305", ADIS16300},
1226*4882a593Smuzhiyun {"adis16334", ADIS16334},
1227*4882a593Smuzhiyun {"adis16350", ADIS16350},
1228*4882a593Smuzhiyun {"adis16354", ADIS16350},
1229*4882a593Smuzhiyun {"adis16355", ADIS16350},
1230*4882a593Smuzhiyun {"adis16360", ADIS16360},
1231*4882a593Smuzhiyun {"adis16362", ADIS16362},
1232*4882a593Smuzhiyun {"adis16364", ADIS16364},
1233*4882a593Smuzhiyun {"adis16365", ADIS16360},
1234*4882a593Smuzhiyun {"adis16367", ADIS16367},
1235*4882a593Smuzhiyun {"adis16400", ADIS16400},
1236*4882a593Smuzhiyun {"adis16405", ADIS16400},
1237*4882a593Smuzhiyun {"adis16445", ADIS16445},
1238*4882a593Smuzhiyun {"adis16448", ADIS16448},
1239*4882a593Smuzhiyun {}
1240*4882a593Smuzhiyun };
1241*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, adis16400_id);
1242*4882a593Smuzhiyun
1243*4882a593Smuzhiyun static struct spi_driver adis16400_driver = {
1244*4882a593Smuzhiyun .driver = {
1245*4882a593Smuzhiyun .name = "adis16400",
1246*4882a593Smuzhiyun },
1247*4882a593Smuzhiyun .id_table = adis16400_id,
1248*4882a593Smuzhiyun .probe = adis16400_probe,
1249*4882a593Smuzhiyun };
1250*4882a593Smuzhiyun module_spi_driver(adis16400_driver);
1251*4882a593Smuzhiyun
1252*4882a593Smuzhiyun MODULE_AUTHOR("Manuel Stahl <manuel.stahl@iis.fraunhofer.de>");
1253*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices ADIS16400/5 IMU SPI driver");
1254*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1255