xref: /OK3568_Linux_fs/kernel/drivers/iio/health/max30102.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * max30102.c - Support for MAX30102 heart rate and pulse oximeter sensor
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2017 Matt Ranostay <matt.ranostay@konsulko.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Support for MAX30105 optical particle sensor
8*4882a593Smuzhiyun  * Copyright (C) 2017 Peter Meerwald-Stadler <pmeerw@pmeerw.net>
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * 7-bit I2C chip address: 0x57
11*4882a593Smuzhiyun  * TODO: proximity power saving feature
12*4882a593Smuzhiyun  */
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/init.h>
16*4882a593Smuzhiyun #include <linux/interrupt.h>
17*4882a593Smuzhiyun #include <linux/delay.h>
18*4882a593Smuzhiyun #include <linux/err.h>
19*4882a593Smuzhiyun #include <linux/irq.h>
20*4882a593Smuzhiyun #include <linux/i2c.h>
21*4882a593Smuzhiyun #include <linux/mutex.h>
22*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
23*4882a593Smuzhiyun #include <linux/regmap.h>
24*4882a593Smuzhiyun #include <linux/iio/iio.h>
25*4882a593Smuzhiyun #include <linux/iio/buffer.h>
26*4882a593Smuzhiyun #include <linux/iio/kfifo_buf.h>
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define MAX30102_REGMAP_NAME	"max30102_regmap"
29*4882a593Smuzhiyun #define MAX30102_DRV_NAME	"max30102"
30*4882a593Smuzhiyun #define MAX30102_PART_NUMBER	0x15
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun enum max30102_chip_id {
33*4882a593Smuzhiyun 	max30102,
34*4882a593Smuzhiyun 	max30105,
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun enum max3012_led_idx {
38*4882a593Smuzhiyun 	MAX30102_LED_RED,
39*4882a593Smuzhiyun 	MAX30102_LED_IR,
40*4882a593Smuzhiyun 	MAX30105_LED_GREEN,
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define MAX30102_REG_INT_STATUS			0x00
44*4882a593Smuzhiyun #define MAX30102_REG_INT_STATUS_PWR_RDY		BIT(0)
45*4882a593Smuzhiyun #define MAX30102_REG_INT_STATUS_PROX_INT	BIT(4)
46*4882a593Smuzhiyun #define MAX30102_REG_INT_STATUS_ALC_OVF		BIT(5)
47*4882a593Smuzhiyun #define MAX30102_REG_INT_STATUS_PPG_RDY		BIT(6)
48*4882a593Smuzhiyun #define MAX30102_REG_INT_STATUS_FIFO_RDY	BIT(7)
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun #define MAX30102_REG_INT_ENABLE			0x02
51*4882a593Smuzhiyun #define MAX30102_REG_INT_ENABLE_PROX_INT_EN	BIT(4)
52*4882a593Smuzhiyun #define MAX30102_REG_INT_ENABLE_ALC_OVF_EN	BIT(5)
53*4882a593Smuzhiyun #define MAX30102_REG_INT_ENABLE_PPG_EN		BIT(6)
54*4882a593Smuzhiyun #define MAX30102_REG_INT_ENABLE_FIFO_EN		BIT(7)
55*4882a593Smuzhiyun #define MAX30102_REG_INT_ENABLE_MASK		0xf0
56*4882a593Smuzhiyun #define MAX30102_REG_INT_ENABLE_MASK_SHIFT	4
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define MAX30102_REG_FIFO_WR_PTR		0x04
59*4882a593Smuzhiyun #define MAX30102_REG_FIFO_OVR_CTR		0x05
60*4882a593Smuzhiyun #define MAX30102_REG_FIFO_RD_PTR		0x06
61*4882a593Smuzhiyun #define MAX30102_REG_FIFO_DATA			0x07
62*4882a593Smuzhiyun #define MAX30102_REG_FIFO_DATA_BYTES		3
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define MAX30102_REG_FIFO_CONFIG		0x08
65*4882a593Smuzhiyun #define MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES	BIT(1)
66*4882a593Smuzhiyun #define MAX30102_REG_FIFO_CONFIG_AVG_SHIFT	5
67*4882a593Smuzhiyun #define MAX30102_REG_FIFO_CONFIG_AFULL		BIT(0)
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define MAX30102_REG_MODE_CONFIG		0x09
70*4882a593Smuzhiyun #define MAX30102_REG_MODE_CONFIG_MODE_NONE	0x00
71*4882a593Smuzhiyun #define MAX30102_REG_MODE_CONFIG_MODE_HR	0x02 /* red LED */
72*4882a593Smuzhiyun #define MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2	0x03 /* red + IR LED */
73*4882a593Smuzhiyun #define MAX30102_REG_MODE_CONFIG_MODE_MULTI	0x07 /* multi-LED mode */
74*4882a593Smuzhiyun #define MAX30102_REG_MODE_CONFIG_MODE_MASK	GENMASK(2, 0)
75*4882a593Smuzhiyun #define MAX30102_REG_MODE_CONFIG_PWR		BIT(7)
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun #define MAX30102_REG_MODE_CONTROL_SLOT21	0x11 /* multi-LED control */
78*4882a593Smuzhiyun #define MAX30102_REG_MODE_CONTROL_SLOT43	0x12
79*4882a593Smuzhiyun #define MAX30102_REG_MODE_CONTROL_SLOT_MASK	(GENMASK(6, 4) | GENMASK(2, 0))
80*4882a593Smuzhiyun #define MAX30102_REG_MODE_CONTROL_SLOT_SHIFT	4
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun #define MAX30102_REG_SPO2_CONFIG		0x0a
83*4882a593Smuzhiyun #define MAX30102_REG_SPO2_CONFIG_PULSE_411_US	0x03
84*4882a593Smuzhiyun #define MAX30102_REG_SPO2_CONFIG_SR_400HZ	0x03
85*4882a593Smuzhiyun #define MAX30102_REG_SPO2_CONFIG_SR_MASK	0x07
86*4882a593Smuzhiyun #define MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT	2
87*4882a593Smuzhiyun #define MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS	BIT(0)
88*4882a593Smuzhiyun #define MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT	5
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun #define MAX30102_REG_RED_LED_CONFIG		0x0c
91*4882a593Smuzhiyun #define MAX30102_REG_IR_LED_CONFIG		0x0d
92*4882a593Smuzhiyun #define MAX30105_REG_GREEN_LED_CONFIG		0x0e
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun #define MAX30102_REG_TEMP_CONFIG		0x21
95*4882a593Smuzhiyun #define MAX30102_REG_TEMP_CONFIG_TEMP_EN	BIT(0)
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun #define MAX30102_REG_TEMP_INTEGER		0x1f
98*4882a593Smuzhiyun #define MAX30102_REG_TEMP_FRACTION		0x20
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun #define MAX30102_REG_REV_ID			0xfe
101*4882a593Smuzhiyun #define MAX30102_REG_PART_ID			0xff
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun struct max30102_data {
104*4882a593Smuzhiyun 	struct i2c_client *client;
105*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
106*4882a593Smuzhiyun 	struct mutex lock;
107*4882a593Smuzhiyun 	struct regmap *regmap;
108*4882a593Smuzhiyun 	enum max30102_chip_id chip_id;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	u8 buffer[12];
111*4882a593Smuzhiyun 	__be32 processed_buffer[3]; /* 3 x 18-bit (padded to 32-bits) */
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun static const struct regmap_config max30102_regmap_config = {
115*4882a593Smuzhiyun 	.name = MAX30102_REGMAP_NAME,
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	.reg_bits = 8,
118*4882a593Smuzhiyun 	.val_bits = 8,
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun static const unsigned long max30102_scan_masks[] = {
122*4882a593Smuzhiyun 	BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR),
123*4882a593Smuzhiyun 	0
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun static const unsigned long max30105_scan_masks[] = {
127*4882a593Smuzhiyun 	BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR),
128*4882a593Smuzhiyun 	BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) |
129*4882a593Smuzhiyun 		BIT(MAX30105_LED_GREEN),
130*4882a593Smuzhiyun 	0
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun #define MAX30102_INTENSITY_CHANNEL(_si, _mod) { \
134*4882a593Smuzhiyun 		.type = IIO_INTENSITY, \
135*4882a593Smuzhiyun 		.channel2 = _mod, \
136*4882a593Smuzhiyun 		.modified = 1, \
137*4882a593Smuzhiyun 		.scan_index = _si, \
138*4882a593Smuzhiyun 		.scan_type = { \
139*4882a593Smuzhiyun 			.sign = 'u', \
140*4882a593Smuzhiyun 			.shift = 8, \
141*4882a593Smuzhiyun 			.realbits = 18, \
142*4882a593Smuzhiyun 			.storagebits = 32, \
143*4882a593Smuzhiyun 			.endianness = IIO_BE, \
144*4882a593Smuzhiyun 		}, \
145*4882a593Smuzhiyun 	}
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun static const struct iio_chan_spec max30102_channels[] = {
148*4882a593Smuzhiyun 	MAX30102_INTENSITY_CHANNEL(MAX30102_LED_RED, IIO_MOD_LIGHT_RED),
149*4882a593Smuzhiyun 	MAX30102_INTENSITY_CHANNEL(MAX30102_LED_IR, IIO_MOD_LIGHT_IR),
150*4882a593Smuzhiyun 	{
151*4882a593Smuzhiyun 		.type = IIO_TEMP,
152*4882a593Smuzhiyun 		.info_mask_separate =
153*4882a593Smuzhiyun 			BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
154*4882a593Smuzhiyun 		.scan_index = -1,
155*4882a593Smuzhiyun 	},
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun static const struct iio_chan_spec max30105_channels[] = {
159*4882a593Smuzhiyun 	MAX30102_INTENSITY_CHANNEL(MAX30102_LED_RED, IIO_MOD_LIGHT_RED),
160*4882a593Smuzhiyun 	MAX30102_INTENSITY_CHANNEL(MAX30102_LED_IR, IIO_MOD_LIGHT_IR),
161*4882a593Smuzhiyun 	MAX30102_INTENSITY_CHANNEL(MAX30105_LED_GREEN, IIO_MOD_LIGHT_GREEN),
162*4882a593Smuzhiyun 	{
163*4882a593Smuzhiyun 		.type = IIO_TEMP,
164*4882a593Smuzhiyun 		.info_mask_separate =
165*4882a593Smuzhiyun 			BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
166*4882a593Smuzhiyun 		.scan_index = -1,
167*4882a593Smuzhiyun 	},
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun 
max30102_set_power(struct max30102_data * data,bool en)170*4882a593Smuzhiyun static int max30102_set_power(struct max30102_data *data, bool en)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun 	return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
173*4882a593Smuzhiyun 				  MAX30102_REG_MODE_CONFIG_PWR,
174*4882a593Smuzhiyun 				  en ? 0 : MAX30102_REG_MODE_CONFIG_PWR);
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun 
max30102_set_powermode(struct max30102_data * data,u8 mode,bool en)177*4882a593Smuzhiyun static int max30102_set_powermode(struct max30102_data *data, u8 mode, bool en)
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun 	u8 reg = mode;
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	if (!en)
182*4882a593Smuzhiyun 		reg |= MAX30102_REG_MODE_CONFIG_PWR;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	return regmap_update_bits(data->regmap, MAX30102_REG_MODE_CONFIG,
185*4882a593Smuzhiyun 				  MAX30102_REG_MODE_CONFIG_PWR |
186*4882a593Smuzhiyun 				  MAX30102_REG_MODE_CONFIG_MODE_MASK, reg);
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun #define MAX30102_MODE_CONTROL_LED_SLOTS(slot2, slot1) \
190*4882a593Smuzhiyun 	((slot2 << MAX30102_REG_MODE_CONTROL_SLOT_SHIFT) | slot1)
191*4882a593Smuzhiyun 
max30102_buffer_postenable(struct iio_dev * indio_dev)192*4882a593Smuzhiyun static int max30102_buffer_postenable(struct iio_dev *indio_dev)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun 	struct max30102_data *data = iio_priv(indio_dev);
195*4882a593Smuzhiyun 	int ret;
196*4882a593Smuzhiyun 	u8 reg;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	switch (*indio_dev->active_scan_mask) {
199*4882a593Smuzhiyun 	case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR):
200*4882a593Smuzhiyun 		reg = MAX30102_REG_MODE_CONFIG_MODE_HR_SPO2;
201*4882a593Smuzhiyun 		break;
202*4882a593Smuzhiyun 	case BIT(MAX30102_LED_RED) | BIT(MAX30102_LED_IR) |
203*4882a593Smuzhiyun 	     BIT(MAX30105_LED_GREEN):
204*4882a593Smuzhiyun 		ret = regmap_update_bits(data->regmap,
205*4882a593Smuzhiyun 					 MAX30102_REG_MODE_CONTROL_SLOT21,
206*4882a593Smuzhiyun 					 MAX30102_REG_MODE_CONTROL_SLOT_MASK,
207*4882a593Smuzhiyun 					 MAX30102_MODE_CONTROL_LED_SLOTS(2, 1));
208*4882a593Smuzhiyun 		if (ret)
209*4882a593Smuzhiyun 			return ret;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 		ret = regmap_update_bits(data->regmap,
212*4882a593Smuzhiyun 					 MAX30102_REG_MODE_CONTROL_SLOT43,
213*4882a593Smuzhiyun 					 MAX30102_REG_MODE_CONTROL_SLOT_MASK,
214*4882a593Smuzhiyun 					 MAX30102_MODE_CONTROL_LED_SLOTS(0, 3));
215*4882a593Smuzhiyun 		if (ret)
216*4882a593Smuzhiyun 			return ret;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 		reg = MAX30102_REG_MODE_CONFIG_MODE_MULTI;
219*4882a593Smuzhiyun 		break;
220*4882a593Smuzhiyun 	default:
221*4882a593Smuzhiyun 		return -EINVAL;
222*4882a593Smuzhiyun 	}
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	return max30102_set_powermode(data, reg, true);
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun 
max30102_buffer_predisable(struct iio_dev * indio_dev)227*4882a593Smuzhiyun static int max30102_buffer_predisable(struct iio_dev *indio_dev)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun 	struct max30102_data *data = iio_priv(indio_dev);
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	return max30102_set_powermode(data, MAX30102_REG_MODE_CONFIG_MODE_NONE,
232*4882a593Smuzhiyun 				      false);
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun static const struct iio_buffer_setup_ops max30102_buffer_setup_ops = {
236*4882a593Smuzhiyun 	.postenable = max30102_buffer_postenable,
237*4882a593Smuzhiyun 	.predisable = max30102_buffer_predisable,
238*4882a593Smuzhiyun };
239*4882a593Smuzhiyun 
max30102_fifo_count(struct max30102_data * data)240*4882a593Smuzhiyun static inline int max30102_fifo_count(struct max30102_data *data)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun 	unsigned int val;
243*4882a593Smuzhiyun 	int ret;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	ret = regmap_read(data->regmap, MAX30102_REG_INT_STATUS, &val);
246*4882a593Smuzhiyun 	if (ret)
247*4882a593Smuzhiyun 		return ret;
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	/* FIFO has one sample slot left */
250*4882a593Smuzhiyun 	if (val & MAX30102_REG_INT_STATUS_FIFO_RDY)
251*4882a593Smuzhiyun 		return 1;
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	return 0;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun #define MAX30102_COPY_DATA(i) \
257*4882a593Smuzhiyun 	memcpy(&data->processed_buffer[(i)], \
258*4882a593Smuzhiyun 	       &buffer[(i) * MAX30102_REG_FIFO_DATA_BYTES], \
259*4882a593Smuzhiyun 	       MAX30102_REG_FIFO_DATA_BYTES)
260*4882a593Smuzhiyun 
max30102_read_measurement(struct max30102_data * data,unsigned int measurements)261*4882a593Smuzhiyun static int max30102_read_measurement(struct max30102_data *data,
262*4882a593Smuzhiyun 				     unsigned int measurements)
263*4882a593Smuzhiyun {
264*4882a593Smuzhiyun 	int ret;
265*4882a593Smuzhiyun 	u8 *buffer = (u8 *) &data->buffer;
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	ret = i2c_smbus_read_i2c_block_data(data->client,
268*4882a593Smuzhiyun 					    MAX30102_REG_FIFO_DATA,
269*4882a593Smuzhiyun 					    measurements *
270*4882a593Smuzhiyun 					    MAX30102_REG_FIFO_DATA_BYTES,
271*4882a593Smuzhiyun 					    buffer);
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	switch (measurements) {
274*4882a593Smuzhiyun 	case 3:
275*4882a593Smuzhiyun 		MAX30102_COPY_DATA(2);
276*4882a593Smuzhiyun 		fallthrough;
277*4882a593Smuzhiyun 	case 2:
278*4882a593Smuzhiyun 		MAX30102_COPY_DATA(1);
279*4882a593Smuzhiyun 		fallthrough;
280*4882a593Smuzhiyun 	case 1:
281*4882a593Smuzhiyun 		MAX30102_COPY_DATA(0);
282*4882a593Smuzhiyun 		break;
283*4882a593Smuzhiyun 	default:
284*4882a593Smuzhiyun 		return -EINVAL;
285*4882a593Smuzhiyun 	}
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	return (ret == measurements * MAX30102_REG_FIFO_DATA_BYTES) ?
288*4882a593Smuzhiyun 	       0 : -EINVAL;
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun 
max30102_interrupt_handler(int irq,void * private)291*4882a593Smuzhiyun static irqreturn_t max30102_interrupt_handler(int irq, void *private)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun 	struct iio_dev *indio_dev = private;
294*4882a593Smuzhiyun 	struct max30102_data *data = iio_priv(indio_dev);
295*4882a593Smuzhiyun 	unsigned int measurements = bitmap_weight(indio_dev->active_scan_mask,
296*4882a593Smuzhiyun 						  indio_dev->masklength);
297*4882a593Smuzhiyun 	int ret, cnt = 0;
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun 	mutex_lock(&data->lock);
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	while (cnt || (cnt = max30102_fifo_count(data)) > 0) {
302*4882a593Smuzhiyun 		ret = max30102_read_measurement(data, measurements);
303*4882a593Smuzhiyun 		if (ret)
304*4882a593Smuzhiyun 			break;
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 		iio_push_to_buffers(data->indio_dev, data->processed_buffer);
307*4882a593Smuzhiyun 		cnt--;
308*4882a593Smuzhiyun 	}
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	mutex_unlock(&data->lock);
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	return IRQ_HANDLED;
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun 
max30102_get_current_idx(unsigned int val,int * reg)315*4882a593Smuzhiyun static int max30102_get_current_idx(unsigned int val, int *reg)
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun 	/* each step is 0.200 mA */
318*4882a593Smuzhiyun 	*reg = val / 200;
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 	return *reg > 0xff ? -EINVAL : 0;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun 
max30102_led_init(struct max30102_data * data)323*4882a593Smuzhiyun static int max30102_led_init(struct max30102_data *data)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun 	struct device *dev = &data->client->dev;
326*4882a593Smuzhiyun 	unsigned int val;
327*4882a593Smuzhiyun 	int reg, ret;
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	ret = device_property_read_u32(dev, "maxim,red-led-current-microamp", &val);
330*4882a593Smuzhiyun 	if (ret) {
331*4882a593Smuzhiyun 		dev_info(dev, "no red-led-current-microamp set\n");
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 		/* Default to 7 mA RED LED */
334*4882a593Smuzhiyun 		val = 7000;
335*4882a593Smuzhiyun 	}
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	ret = max30102_get_current_idx(val, &reg);
338*4882a593Smuzhiyun 	if (ret) {
339*4882a593Smuzhiyun 		dev_err(dev, "invalid RED LED current setting %d\n", val);
340*4882a593Smuzhiyun 		return ret;
341*4882a593Smuzhiyun 	}
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	ret = regmap_write(data->regmap, MAX30102_REG_RED_LED_CONFIG, reg);
344*4882a593Smuzhiyun 	if (ret)
345*4882a593Smuzhiyun 		return ret;
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	if (data->chip_id == max30105) {
348*4882a593Smuzhiyun 		ret = device_property_read_u32(dev,
349*4882a593Smuzhiyun 			"maxim,green-led-current-microamp", &val);
350*4882a593Smuzhiyun 		if (ret) {
351*4882a593Smuzhiyun 			dev_info(dev, "no green-led-current-microamp set\n");
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 			/* Default to 7 mA green LED */
354*4882a593Smuzhiyun 			val = 7000;
355*4882a593Smuzhiyun 		}
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 		ret = max30102_get_current_idx(val, &reg);
358*4882a593Smuzhiyun 		if (ret) {
359*4882a593Smuzhiyun 			dev_err(dev, "invalid green LED current setting %d\n",
360*4882a593Smuzhiyun 				val);
361*4882a593Smuzhiyun 			return ret;
362*4882a593Smuzhiyun 		}
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 		ret = regmap_write(data->regmap, MAX30105_REG_GREEN_LED_CONFIG,
365*4882a593Smuzhiyun 				   reg);
366*4882a593Smuzhiyun 		if (ret)
367*4882a593Smuzhiyun 			return ret;
368*4882a593Smuzhiyun 	}
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun 	ret = device_property_read_u32(dev, "maxim,ir-led-current-microamp", &val);
371*4882a593Smuzhiyun 	if (ret) {
372*4882a593Smuzhiyun 		dev_info(dev, "no ir-led-current-microamp set\n");
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 		/* Default to 7 mA IR LED */
375*4882a593Smuzhiyun 		val = 7000;
376*4882a593Smuzhiyun 	}
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	ret = max30102_get_current_idx(val, &reg);
379*4882a593Smuzhiyun 	if (ret) {
380*4882a593Smuzhiyun 		dev_err(dev, "invalid IR LED current setting %d\n", val);
381*4882a593Smuzhiyun 		return ret;
382*4882a593Smuzhiyun 	}
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	return regmap_write(data->regmap, MAX30102_REG_IR_LED_CONFIG, reg);
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun 
max30102_chip_init(struct max30102_data * data)387*4882a593Smuzhiyun static int max30102_chip_init(struct max30102_data *data)
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun 	int ret;
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	/* setup LED current settings */
392*4882a593Smuzhiyun 	ret = max30102_led_init(data);
393*4882a593Smuzhiyun 	if (ret)
394*4882a593Smuzhiyun 		return ret;
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	/* configure 18-bit HR + SpO2 readings at 400Hz */
397*4882a593Smuzhiyun 	ret = regmap_write(data->regmap, MAX30102_REG_SPO2_CONFIG,
398*4882a593Smuzhiyun 				(MAX30102_REG_SPO2_CONFIG_ADC_4096_STEPS
399*4882a593Smuzhiyun 				 << MAX30102_REG_SPO2_CONFIG_ADC_MASK_SHIFT) |
400*4882a593Smuzhiyun 				(MAX30102_REG_SPO2_CONFIG_SR_400HZ
401*4882a593Smuzhiyun 				 << MAX30102_REG_SPO2_CONFIG_SR_MASK_SHIFT) |
402*4882a593Smuzhiyun 				 MAX30102_REG_SPO2_CONFIG_PULSE_411_US);
403*4882a593Smuzhiyun 	if (ret)
404*4882a593Smuzhiyun 		return ret;
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	/* average 4 samples + generate FIFO interrupt */
407*4882a593Smuzhiyun 	ret = regmap_write(data->regmap, MAX30102_REG_FIFO_CONFIG,
408*4882a593Smuzhiyun 				(MAX30102_REG_FIFO_CONFIG_AVG_4SAMPLES
409*4882a593Smuzhiyun 				 << MAX30102_REG_FIFO_CONFIG_AVG_SHIFT) |
410*4882a593Smuzhiyun 				 MAX30102_REG_FIFO_CONFIG_AFULL);
411*4882a593Smuzhiyun 	if (ret)
412*4882a593Smuzhiyun 		return ret;
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	/* enable FIFO interrupt */
415*4882a593Smuzhiyun 	return regmap_update_bits(data->regmap, MAX30102_REG_INT_ENABLE,
416*4882a593Smuzhiyun 				 MAX30102_REG_INT_ENABLE_MASK,
417*4882a593Smuzhiyun 				 MAX30102_REG_INT_ENABLE_FIFO_EN);
418*4882a593Smuzhiyun }
419*4882a593Smuzhiyun 
max30102_read_temp(struct max30102_data * data,int * val)420*4882a593Smuzhiyun static int max30102_read_temp(struct max30102_data *data, int *val)
421*4882a593Smuzhiyun {
422*4882a593Smuzhiyun 	int ret;
423*4882a593Smuzhiyun 	unsigned int reg;
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 	ret = regmap_read(data->regmap, MAX30102_REG_TEMP_INTEGER, &reg);
426*4882a593Smuzhiyun 	if (ret < 0)
427*4882a593Smuzhiyun 		return ret;
428*4882a593Smuzhiyun 	*val = reg << 4;
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	ret = regmap_read(data->regmap, MAX30102_REG_TEMP_FRACTION, &reg);
431*4882a593Smuzhiyun 	if (ret < 0)
432*4882a593Smuzhiyun 		return ret;
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	*val |= reg & 0xf;
435*4882a593Smuzhiyun 	*val = sign_extend32(*val, 11);
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	return 0;
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun 
max30102_get_temp(struct max30102_data * data,int * val,bool en)440*4882a593Smuzhiyun static int max30102_get_temp(struct max30102_data *data, int *val, bool en)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun 	int ret;
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun 	if (en) {
445*4882a593Smuzhiyun 		ret = max30102_set_power(data, true);
446*4882a593Smuzhiyun 		if (ret)
447*4882a593Smuzhiyun 			return ret;
448*4882a593Smuzhiyun 	}
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun 	/* start acquisition */
451*4882a593Smuzhiyun 	ret = regmap_update_bits(data->regmap, MAX30102_REG_TEMP_CONFIG,
452*4882a593Smuzhiyun 				 MAX30102_REG_TEMP_CONFIG_TEMP_EN,
453*4882a593Smuzhiyun 				 MAX30102_REG_TEMP_CONFIG_TEMP_EN);
454*4882a593Smuzhiyun 	if (ret)
455*4882a593Smuzhiyun 		goto out;
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	msleep(35);
458*4882a593Smuzhiyun 	ret = max30102_read_temp(data, val);
459*4882a593Smuzhiyun 
460*4882a593Smuzhiyun out:
461*4882a593Smuzhiyun 	if (en)
462*4882a593Smuzhiyun 		max30102_set_power(data, false);
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	return ret;
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun 
max30102_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)467*4882a593Smuzhiyun static int max30102_read_raw(struct iio_dev *indio_dev,
468*4882a593Smuzhiyun 			     struct iio_chan_spec const *chan,
469*4882a593Smuzhiyun 			     int *val, int *val2, long mask)
470*4882a593Smuzhiyun {
471*4882a593Smuzhiyun 	struct max30102_data *data = iio_priv(indio_dev);
472*4882a593Smuzhiyun 	int ret = -EINVAL;
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 	switch (mask) {
475*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
476*4882a593Smuzhiyun 		/*
477*4882a593Smuzhiyun 		 * Temperature reading can only be acquired when not in
478*4882a593Smuzhiyun 		 * shutdown; leave shutdown briefly when buffer not running
479*4882a593Smuzhiyun 		 */
480*4882a593Smuzhiyun 		mutex_lock(&indio_dev->mlock);
481*4882a593Smuzhiyun 		if (!iio_buffer_enabled(indio_dev))
482*4882a593Smuzhiyun 			ret = max30102_get_temp(data, val, true);
483*4882a593Smuzhiyun 		else
484*4882a593Smuzhiyun 			ret = max30102_get_temp(data, val, false);
485*4882a593Smuzhiyun 		mutex_unlock(&indio_dev->mlock);
486*4882a593Smuzhiyun 		if (ret)
487*4882a593Smuzhiyun 			return ret;
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun 		ret = IIO_VAL_INT;
490*4882a593Smuzhiyun 		break;
491*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
492*4882a593Smuzhiyun 		*val = 1000;  /* 62.5 */
493*4882a593Smuzhiyun 		*val2 = 16;
494*4882a593Smuzhiyun 		ret = IIO_VAL_FRACTIONAL;
495*4882a593Smuzhiyun 		break;
496*4882a593Smuzhiyun 	}
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun 	return ret;
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun static const struct iio_info max30102_info = {
502*4882a593Smuzhiyun 	.read_raw = max30102_read_raw,
503*4882a593Smuzhiyun };
504*4882a593Smuzhiyun 
max30102_probe(struct i2c_client * client,const struct i2c_device_id * id)505*4882a593Smuzhiyun static int max30102_probe(struct i2c_client *client,
506*4882a593Smuzhiyun 			  const struct i2c_device_id *id)
507*4882a593Smuzhiyun {
508*4882a593Smuzhiyun 	struct max30102_data *data;
509*4882a593Smuzhiyun 	struct iio_buffer *buffer;
510*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
511*4882a593Smuzhiyun 	int ret;
512*4882a593Smuzhiyun 	unsigned int reg;
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
515*4882a593Smuzhiyun 	if (!indio_dev)
516*4882a593Smuzhiyun 		return -ENOMEM;
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun 	buffer = devm_iio_kfifo_allocate(&client->dev);
519*4882a593Smuzhiyun 	if (!buffer)
520*4882a593Smuzhiyun 		return -ENOMEM;
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	iio_device_attach_buffer(indio_dev, buffer);
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	indio_dev->name = MAX30102_DRV_NAME;
525*4882a593Smuzhiyun 	indio_dev->info = &max30102_info;
526*4882a593Smuzhiyun 	indio_dev->modes = (INDIO_BUFFER_SOFTWARE | INDIO_DIRECT_MODE);
527*4882a593Smuzhiyun 	indio_dev->setup_ops = &max30102_buffer_setup_ops;
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	data = iio_priv(indio_dev);
530*4882a593Smuzhiyun 	data->indio_dev = indio_dev;
531*4882a593Smuzhiyun 	data->client = client;
532*4882a593Smuzhiyun 	data->chip_id = id->driver_data;
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 	mutex_init(&data->lock);
535*4882a593Smuzhiyun 	i2c_set_clientdata(client, indio_dev);
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 	switch (data->chip_id) {
538*4882a593Smuzhiyun 	case max30105:
539*4882a593Smuzhiyun 		indio_dev->channels = max30105_channels;
540*4882a593Smuzhiyun 		indio_dev->num_channels = ARRAY_SIZE(max30105_channels);
541*4882a593Smuzhiyun 		indio_dev->available_scan_masks = max30105_scan_masks;
542*4882a593Smuzhiyun 		break;
543*4882a593Smuzhiyun 	case max30102:
544*4882a593Smuzhiyun 		indio_dev->channels = max30102_channels;
545*4882a593Smuzhiyun 		indio_dev->num_channels = ARRAY_SIZE(max30102_channels);
546*4882a593Smuzhiyun 		indio_dev->available_scan_masks = max30102_scan_masks;
547*4882a593Smuzhiyun 		break;
548*4882a593Smuzhiyun 	default:
549*4882a593Smuzhiyun 		return -ENODEV;
550*4882a593Smuzhiyun 	}
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun 	data->regmap = devm_regmap_init_i2c(client, &max30102_regmap_config);
553*4882a593Smuzhiyun 	if (IS_ERR(data->regmap)) {
554*4882a593Smuzhiyun 		dev_err(&client->dev, "regmap initialization failed\n");
555*4882a593Smuzhiyun 		return PTR_ERR(data->regmap);
556*4882a593Smuzhiyun 	}
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	/* check part ID */
559*4882a593Smuzhiyun 	ret = regmap_read(data->regmap, MAX30102_REG_PART_ID, &reg);
560*4882a593Smuzhiyun 	if (ret)
561*4882a593Smuzhiyun 		return ret;
562*4882a593Smuzhiyun 	if (reg != MAX30102_PART_NUMBER)
563*4882a593Smuzhiyun 		return -ENODEV;
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun 	/* show revision ID */
566*4882a593Smuzhiyun 	ret = regmap_read(data->regmap, MAX30102_REG_REV_ID, &reg);
567*4882a593Smuzhiyun 	if (ret)
568*4882a593Smuzhiyun 		return ret;
569*4882a593Smuzhiyun 	dev_dbg(&client->dev, "max3010x revision %02x\n", reg);
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	/* clear mode setting, chip shutdown */
572*4882a593Smuzhiyun 	ret = max30102_set_powermode(data, MAX30102_REG_MODE_CONFIG_MODE_NONE,
573*4882a593Smuzhiyun 				     false);
574*4882a593Smuzhiyun 	if (ret)
575*4882a593Smuzhiyun 		return ret;
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun 	ret = max30102_chip_init(data);
578*4882a593Smuzhiyun 	if (ret)
579*4882a593Smuzhiyun 		return ret;
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun 	if (client->irq <= 0) {
582*4882a593Smuzhiyun 		dev_err(&client->dev, "no valid irq defined\n");
583*4882a593Smuzhiyun 		return -EINVAL;
584*4882a593Smuzhiyun 	}
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun 	ret = devm_request_threaded_irq(&client->dev, client->irq,
587*4882a593Smuzhiyun 					NULL, max30102_interrupt_handler,
588*4882a593Smuzhiyun 					IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
589*4882a593Smuzhiyun 					"max30102_irq", indio_dev);
590*4882a593Smuzhiyun 	if (ret) {
591*4882a593Smuzhiyun 		dev_err(&client->dev, "request irq (%d) failed\n", client->irq);
592*4882a593Smuzhiyun 		return ret;
593*4882a593Smuzhiyun 	}
594*4882a593Smuzhiyun 
595*4882a593Smuzhiyun 	return iio_device_register(indio_dev);
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun 
max30102_remove(struct i2c_client * client)598*4882a593Smuzhiyun static int max30102_remove(struct i2c_client *client)
599*4882a593Smuzhiyun {
600*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
601*4882a593Smuzhiyun 	struct max30102_data *data = iio_priv(indio_dev);
602*4882a593Smuzhiyun 
603*4882a593Smuzhiyun 	iio_device_unregister(indio_dev);
604*4882a593Smuzhiyun 	max30102_set_power(data, false);
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	return 0;
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun static const struct i2c_device_id max30102_id[] = {
610*4882a593Smuzhiyun 	{ "max30102", max30102 },
611*4882a593Smuzhiyun 	{ "max30105", max30105 },
612*4882a593Smuzhiyun 	{}
613*4882a593Smuzhiyun };
614*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, max30102_id);
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun static const struct of_device_id max30102_dt_ids[] = {
617*4882a593Smuzhiyun 	{ .compatible = "maxim,max30102" },
618*4882a593Smuzhiyun 	{ .compatible = "maxim,max30105" },
619*4882a593Smuzhiyun 	{ }
620*4882a593Smuzhiyun };
621*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, max30102_dt_ids);
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun static struct i2c_driver max30102_driver = {
624*4882a593Smuzhiyun 	.driver = {
625*4882a593Smuzhiyun 		.name	= MAX30102_DRV_NAME,
626*4882a593Smuzhiyun 		.of_match_table	= max30102_dt_ids,
627*4882a593Smuzhiyun 	},
628*4882a593Smuzhiyun 	.probe		= max30102_probe,
629*4882a593Smuzhiyun 	.remove		= max30102_remove,
630*4882a593Smuzhiyun 	.id_table	= max30102_id,
631*4882a593Smuzhiyun };
632*4882a593Smuzhiyun module_i2c_driver(max30102_driver);
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun MODULE_AUTHOR("Matt Ranostay <matt.ranostay@konsulko.com>");
635*4882a593Smuzhiyun MODULE_DESCRIPTION("MAX30102 heart rate/pulse oximeter and MAX30105 particle sensor driver");
636*4882a593Smuzhiyun MODULE_LICENSE("GPL");
637