1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * max30100.c - Support for MAX30100 heart rate and pulse oximeter sensor
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2015, 2018
6*4882a593Smuzhiyun * Author: Matt Ranostay <matt.ranostay@konsulko.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * TODO: enable pulse length controls via device tree properties
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <linux/delay.h>
15*4882a593Smuzhiyun #include <linux/err.h>
16*4882a593Smuzhiyun #include <linux/irq.h>
17*4882a593Smuzhiyun #include <linux/i2c.h>
18*4882a593Smuzhiyun #include <linux/mutex.h>
19*4882a593Smuzhiyun #include <linux/property.h>
20*4882a593Smuzhiyun #include <linux/regmap.h>
21*4882a593Smuzhiyun #include <linux/iio/iio.h>
22*4882a593Smuzhiyun #include <linux/iio/buffer.h>
23*4882a593Smuzhiyun #include <linux/iio/kfifo_buf.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define MAX30100_REGMAP_NAME "max30100_regmap"
26*4882a593Smuzhiyun #define MAX30100_DRV_NAME "max30100"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define MAX30100_REG_INT_STATUS 0x00
29*4882a593Smuzhiyun #define MAX30100_REG_INT_STATUS_PWR_RDY BIT(0)
30*4882a593Smuzhiyun #define MAX30100_REG_INT_STATUS_SPO2_RDY BIT(4)
31*4882a593Smuzhiyun #define MAX30100_REG_INT_STATUS_HR_RDY BIT(5)
32*4882a593Smuzhiyun #define MAX30100_REG_INT_STATUS_FIFO_RDY BIT(7)
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define MAX30100_REG_INT_ENABLE 0x01
35*4882a593Smuzhiyun #define MAX30100_REG_INT_ENABLE_SPO2_EN BIT(0)
36*4882a593Smuzhiyun #define MAX30100_REG_INT_ENABLE_HR_EN BIT(1)
37*4882a593Smuzhiyun #define MAX30100_REG_INT_ENABLE_FIFO_EN BIT(3)
38*4882a593Smuzhiyun #define MAX30100_REG_INT_ENABLE_MASK 0xf0
39*4882a593Smuzhiyun #define MAX30100_REG_INT_ENABLE_MASK_SHIFT 4
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define MAX30100_REG_FIFO_WR_PTR 0x02
42*4882a593Smuzhiyun #define MAX30100_REG_FIFO_OVR_CTR 0x03
43*4882a593Smuzhiyun #define MAX30100_REG_FIFO_RD_PTR 0x04
44*4882a593Smuzhiyun #define MAX30100_REG_FIFO_DATA 0x05
45*4882a593Smuzhiyun #define MAX30100_REG_FIFO_DATA_ENTRY_COUNT 16
46*4882a593Smuzhiyun #define MAX30100_REG_FIFO_DATA_ENTRY_LEN 4
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define MAX30100_REG_MODE_CONFIG 0x06
49*4882a593Smuzhiyun #define MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN BIT(0)
50*4882a593Smuzhiyun #define MAX30100_REG_MODE_CONFIG_MODE_HR_EN BIT(1)
51*4882a593Smuzhiyun #define MAX30100_REG_MODE_CONFIG_MODE_MASK 0x03
52*4882a593Smuzhiyun #define MAX30100_REG_MODE_CONFIG_TEMP_EN BIT(3)
53*4882a593Smuzhiyun #define MAX30100_REG_MODE_CONFIG_PWR BIT(7)
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define MAX30100_REG_SPO2_CONFIG 0x07
56*4882a593Smuzhiyun #define MAX30100_REG_SPO2_CONFIG_100HZ BIT(2)
57*4882a593Smuzhiyun #define MAX30100_REG_SPO2_CONFIG_HI_RES_EN BIT(6)
58*4882a593Smuzhiyun #define MAX30100_REG_SPO2_CONFIG_1600US 0x3
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define MAX30100_REG_LED_CONFIG 0x09
61*4882a593Smuzhiyun #define MAX30100_REG_LED_CONFIG_LED_MASK 0x0f
62*4882a593Smuzhiyun #define MAX30100_REG_LED_CONFIG_RED_LED_SHIFT 4
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define MAX30100_REG_LED_CONFIG_24MA 0x07
65*4882a593Smuzhiyun #define MAX30100_REG_LED_CONFIG_50MA 0x0f
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define MAX30100_REG_TEMP_INTEGER 0x16
68*4882a593Smuzhiyun #define MAX30100_REG_TEMP_FRACTION 0x17
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun struct max30100_data {
71*4882a593Smuzhiyun struct i2c_client *client;
72*4882a593Smuzhiyun struct iio_dev *indio_dev;
73*4882a593Smuzhiyun struct mutex lock;
74*4882a593Smuzhiyun struct regmap *regmap;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun __be16 buffer[2]; /* 2 16-bit channels */
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun
max30100_is_volatile_reg(struct device * dev,unsigned int reg)79*4882a593Smuzhiyun static bool max30100_is_volatile_reg(struct device *dev, unsigned int reg)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun switch (reg) {
82*4882a593Smuzhiyun case MAX30100_REG_INT_STATUS:
83*4882a593Smuzhiyun case MAX30100_REG_MODE_CONFIG:
84*4882a593Smuzhiyun case MAX30100_REG_FIFO_WR_PTR:
85*4882a593Smuzhiyun case MAX30100_REG_FIFO_OVR_CTR:
86*4882a593Smuzhiyun case MAX30100_REG_FIFO_RD_PTR:
87*4882a593Smuzhiyun case MAX30100_REG_FIFO_DATA:
88*4882a593Smuzhiyun case MAX30100_REG_TEMP_INTEGER:
89*4882a593Smuzhiyun case MAX30100_REG_TEMP_FRACTION:
90*4882a593Smuzhiyun return true;
91*4882a593Smuzhiyun default:
92*4882a593Smuzhiyun return false;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun static const struct regmap_config max30100_regmap_config = {
97*4882a593Smuzhiyun .name = MAX30100_REGMAP_NAME,
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun .reg_bits = 8,
100*4882a593Smuzhiyun .val_bits = 8,
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun .max_register = MAX30100_REG_TEMP_FRACTION,
103*4882a593Smuzhiyun .cache_type = REGCACHE_FLAT,
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun .volatile_reg = max30100_is_volatile_reg,
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun static const unsigned int max30100_led_current_mapping[] = {
109*4882a593Smuzhiyun 4400, 7600, 11000, 14200, 17400,
110*4882a593Smuzhiyun 20800, 24000, 27100, 30600, 33800,
111*4882a593Smuzhiyun 37000, 40200, 43600, 46800, 50000
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun static const unsigned long max30100_scan_masks[] = {0x3, 0};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun static const struct iio_chan_spec max30100_channels[] = {
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun .type = IIO_INTENSITY,
119*4882a593Smuzhiyun .channel2 = IIO_MOD_LIGHT_IR,
120*4882a593Smuzhiyun .modified = 1,
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun .scan_index = 0,
123*4882a593Smuzhiyun .scan_type = {
124*4882a593Smuzhiyun .sign = 'u',
125*4882a593Smuzhiyun .realbits = 16,
126*4882a593Smuzhiyun .storagebits = 16,
127*4882a593Smuzhiyun .endianness = IIO_BE,
128*4882a593Smuzhiyun },
129*4882a593Smuzhiyun },
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun .type = IIO_INTENSITY,
132*4882a593Smuzhiyun .channel2 = IIO_MOD_LIGHT_RED,
133*4882a593Smuzhiyun .modified = 1,
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun .scan_index = 1,
136*4882a593Smuzhiyun .scan_type = {
137*4882a593Smuzhiyun .sign = 'u',
138*4882a593Smuzhiyun .realbits = 16,
139*4882a593Smuzhiyun .storagebits = 16,
140*4882a593Smuzhiyun .endianness = IIO_BE,
141*4882a593Smuzhiyun },
142*4882a593Smuzhiyun },
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun .type = IIO_TEMP,
145*4882a593Smuzhiyun .info_mask_separate =
146*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
147*4882a593Smuzhiyun .scan_index = -1,
148*4882a593Smuzhiyun },
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun
max30100_set_powermode(struct max30100_data * data,bool state)151*4882a593Smuzhiyun static int max30100_set_powermode(struct max30100_data *data, bool state)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun return regmap_update_bits(data->regmap, MAX30100_REG_MODE_CONFIG,
154*4882a593Smuzhiyun MAX30100_REG_MODE_CONFIG_PWR,
155*4882a593Smuzhiyun state ? 0 : MAX30100_REG_MODE_CONFIG_PWR);
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun
max30100_clear_fifo(struct max30100_data * data)158*4882a593Smuzhiyun static int max30100_clear_fifo(struct max30100_data *data)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun int ret;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun ret = regmap_write(data->regmap, MAX30100_REG_FIFO_WR_PTR, 0);
163*4882a593Smuzhiyun if (ret)
164*4882a593Smuzhiyun return ret;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun ret = regmap_write(data->regmap, MAX30100_REG_FIFO_OVR_CTR, 0);
167*4882a593Smuzhiyun if (ret)
168*4882a593Smuzhiyun return ret;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun return regmap_write(data->regmap, MAX30100_REG_FIFO_RD_PTR, 0);
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun
max30100_buffer_postenable(struct iio_dev * indio_dev)173*4882a593Smuzhiyun static int max30100_buffer_postenable(struct iio_dev *indio_dev)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun struct max30100_data *data = iio_priv(indio_dev);
176*4882a593Smuzhiyun int ret;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun ret = max30100_set_powermode(data, true);
179*4882a593Smuzhiyun if (ret)
180*4882a593Smuzhiyun return ret;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun return max30100_clear_fifo(data);
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
max30100_buffer_predisable(struct iio_dev * indio_dev)185*4882a593Smuzhiyun static int max30100_buffer_predisable(struct iio_dev *indio_dev)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun struct max30100_data *data = iio_priv(indio_dev);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun return max30100_set_powermode(data, false);
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun static const struct iio_buffer_setup_ops max30100_buffer_setup_ops = {
193*4882a593Smuzhiyun .postenable = max30100_buffer_postenable,
194*4882a593Smuzhiyun .predisable = max30100_buffer_predisable,
195*4882a593Smuzhiyun };
196*4882a593Smuzhiyun
max30100_fifo_count(struct max30100_data * data)197*4882a593Smuzhiyun static inline int max30100_fifo_count(struct max30100_data *data)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun unsigned int val;
200*4882a593Smuzhiyun int ret;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun ret = regmap_read(data->regmap, MAX30100_REG_INT_STATUS, &val);
203*4882a593Smuzhiyun if (ret)
204*4882a593Smuzhiyun return ret;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun /* FIFO is almost full */
207*4882a593Smuzhiyun if (val & MAX30100_REG_INT_STATUS_FIFO_RDY)
208*4882a593Smuzhiyun return MAX30100_REG_FIFO_DATA_ENTRY_COUNT - 1;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun return 0;
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
max30100_read_measurement(struct max30100_data * data)213*4882a593Smuzhiyun static int max30100_read_measurement(struct max30100_data *data)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun int ret;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun ret = i2c_smbus_read_i2c_block_data(data->client,
218*4882a593Smuzhiyun MAX30100_REG_FIFO_DATA,
219*4882a593Smuzhiyun MAX30100_REG_FIFO_DATA_ENTRY_LEN,
220*4882a593Smuzhiyun (u8 *) &data->buffer);
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun return (ret == MAX30100_REG_FIFO_DATA_ENTRY_LEN) ? 0 : ret;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
max30100_interrupt_handler(int irq,void * private)225*4882a593Smuzhiyun static irqreturn_t max30100_interrupt_handler(int irq, void *private)
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun struct iio_dev *indio_dev = private;
228*4882a593Smuzhiyun struct max30100_data *data = iio_priv(indio_dev);
229*4882a593Smuzhiyun int ret, cnt = 0;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun mutex_lock(&data->lock);
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun while (cnt || (cnt = max30100_fifo_count(data)) > 0) {
234*4882a593Smuzhiyun ret = max30100_read_measurement(data);
235*4882a593Smuzhiyun if (ret)
236*4882a593Smuzhiyun break;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun iio_push_to_buffers(data->indio_dev, data->buffer);
239*4882a593Smuzhiyun cnt--;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun mutex_unlock(&data->lock);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun return IRQ_HANDLED;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
max30100_get_current_idx(unsigned int val,int * reg)247*4882a593Smuzhiyun static int max30100_get_current_idx(unsigned int val, int *reg)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun int idx;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun /* LED turned off */
252*4882a593Smuzhiyun if (val == 0) {
253*4882a593Smuzhiyun *reg = 0;
254*4882a593Smuzhiyun return 0;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun for (idx = 0; idx < ARRAY_SIZE(max30100_led_current_mapping); idx++) {
258*4882a593Smuzhiyun if (max30100_led_current_mapping[idx] == val) {
259*4882a593Smuzhiyun *reg = idx + 1;
260*4882a593Smuzhiyun return 0;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun return -EINVAL;
265*4882a593Smuzhiyun }
266*4882a593Smuzhiyun
max30100_led_init(struct max30100_data * data)267*4882a593Smuzhiyun static int max30100_led_init(struct max30100_data *data)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun struct device *dev = &data->client->dev;
270*4882a593Smuzhiyun unsigned int val[2];
271*4882a593Smuzhiyun int reg, ret;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun ret = device_property_read_u32_array(dev, "maxim,led-current-microamp",
274*4882a593Smuzhiyun (unsigned int *) &val, 2);
275*4882a593Smuzhiyun if (ret) {
276*4882a593Smuzhiyun /* Default to 24 mA RED LED, 50 mA IR LED */
277*4882a593Smuzhiyun reg = (MAX30100_REG_LED_CONFIG_24MA <<
278*4882a593Smuzhiyun MAX30100_REG_LED_CONFIG_RED_LED_SHIFT) |
279*4882a593Smuzhiyun MAX30100_REG_LED_CONFIG_50MA;
280*4882a593Smuzhiyun dev_warn(dev, "no led-current-microamp set");
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun return regmap_write(data->regmap, MAX30100_REG_LED_CONFIG, reg);
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun /* RED LED current */
286*4882a593Smuzhiyun ret = max30100_get_current_idx(val[0], ®);
287*4882a593Smuzhiyun if (ret) {
288*4882a593Smuzhiyun dev_err(dev, "invalid RED current setting %d", val[0]);
289*4882a593Smuzhiyun return ret;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun ret = regmap_update_bits(data->regmap, MAX30100_REG_LED_CONFIG,
293*4882a593Smuzhiyun MAX30100_REG_LED_CONFIG_LED_MASK <<
294*4882a593Smuzhiyun MAX30100_REG_LED_CONFIG_RED_LED_SHIFT,
295*4882a593Smuzhiyun reg << MAX30100_REG_LED_CONFIG_RED_LED_SHIFT);
296*4882a593Smuzhiyun if (ret)
297*4882a593Smuzhiyun return ret;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun /* IR LED current */
300*4882a593Smuzhiyun ret = max30100_get_current_idx(val[1], ®);
301*4882a593Smuzhiyun if (ret) {
302*4882a593Smuzhiyun dev_err(dev, "invalid IR current setting %d", val[1]);
303*4882a593Smuzhiyun return ret;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun return regmap_update_bits(data->regmap, MAX30100_REG_LED_CONFIG,
307*4882a593Smuzhiyun MAX30100_REG_LED_CONFIG_LED_MASK, reg);
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
max30100_chip_init(struct max30100_data * data)310*4882a593Smuzhiyun static int max30100_chip_init(struct max30100_data *data)
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun int ret;
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun /* setup LED current settings */
315*4882a593Smuzhiyun ret = max30100_led_init(data);
316*4882a593Smuzhiyun if (ret)
317*4882a593Smuzhiyun return ret;
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun /* enable hi-res SPO2 readings at 100Hz */
320*4882a593Smuzhiyun ret = regmap_write(data->regmap, MAX30100_REG_SPO2_CONFIG,
321*4882a593Smuzhiyun MAX30100_REG_SPO2_CONFIG_HI_RES_EN |
322*4882a593Smuzhiyun MAX30100_REG_SPO2_CONFIG_100HZ);
323*4882a593Smuzhiyun if (ret)
324*4882a593Smuzhiyun return ret;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun /* enable SPO2 mode */
327*4882a593Smuzhiyun ret = regmap_update_bits(data->regmap, MAX30100_REG_MODE_CONFIG,
328*4882a593Smuzhiyun MAX30100_REG_MODE_CONFIG_MODE_MASK,
329*4882a593Smuzhiyun MAX30100_REG_MODE_CONFIG_MODE_HR_EN |
330*4882a593Smuzhiyun MAX30100_REG_MODE_CONFIG_MODE_SPO2_EN);
331*4882a593Smuzhiyun if (ret)
332*4882a593Smuzhiyun return ret;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun /* enable FIFO interrupt */
335*4882a593Smuzhiyun return regmap_update_bits(data->regmap, MAX30100_REG_INT_ENABLE,
336*4882a593Smuzhiyun MAX30100_REG_INT_ENABLE_MASK,
337*4882a593Smuzhiyun MAX30100_REG_INT_ENABLE_FIFO_EN
338*4882a593Smuzhiyun << MAX30100_REG_INT_ENABLE_MASK_SHIFT);
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
max30100_read_temp(struct max30100_data * data,int * val)341*4882a593Smuzhiyun static int max30100_read_temp(struct max30100_data *data, int *val)
342*4882a593Smuzhiyun {
343*4882a593Smuzhiyun int ret;
344*4882a593Smuzhiyun unsigned int reg;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun ret = regmap_read(data->regmap, MAX30100_REG_TEMP_INTEGER, ®);
347*4882a593Smuzhiyun if (ret < 0)
348*4882a593Smuzhiyun return ret;
349*4882a593Smuzhiyun *val = reg << 4;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun ret = regmap_read(data->regmap, MAX30100_REG_TEMP_FRACTION, ®);
352*4882a593Smuzhiyun if (ret < 0)
353*4882a593Smuzhiyun return ret;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun *val |= reg & 0xf;
356*4882a593Smuzhiyun *val = sign_extend32(*val, 11);
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun return 0;
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun
max30100_get_temp(struct max30100_data * data,int * val)361*4882a593Smuzhiyun static int max30100_get_temp(struct max30100_data *data, int *val)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun int ret;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun /* start acquisition */
366*4882a593Smuzhiyun ret = regmap_update_bits(data->regmap, MAX30100_REG_MODE_CONFIG,
367*4882a593Smuzhiyun MAX30100_REG_MODE_CONFIG_TEMP_EN,
368*4882a593Smuzhiyun MAX30100_REG_MODE_CONFIG_TEMP_EN);
369*4882a593Smuzhiyun if (ret)
370*4882a593Smuzhiyun return ret;
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun msleep(35);
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun return max30100_read_temp(data, val);
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun
max30100_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)377*4882a593Smuzhiyun static int max30100_read_raw(struct iio_dev *indio_dev,
378*4882a593Smuzhiyun struct iio_chan_spec const *chan,
379*4882a593Smuzhiyun int *val, int *val2, long mask)
380*4882a593Smuzhiyun {
381*4882a593Smuzhiyun struct max30100_data *data = iio_priv(indio_dev);
382*4882a593Smuzhiyun int ret = -EINVAL;
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun switch (mask) {
385*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
386*4882a593Smuzhiyun /*
387*4882a593Smuzhiyun * Temperature reading can only be acquired while engine
388*4882a593Smuzhiyun * is running
389*4882a593Smuzhiyun */
390*4882a593Smuzhiyun mutex_lock(&indio_dev->mlock);
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun if (!iio_buffer_enabled(indio_dev))
393*4882a593Smuzhiyun ret = -EAGAIN;
394*4882a593Smuzhiyun else {
395*4882a593Smuzhiyun ret = max30100_get_temp(data, val);
396*4882a593Smuzhiyun if (!ret)
397*4882a593Smuzhiyun ret = IIO_VAL_INT;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun mutex_unlock(&indio_dev->mlock);
402*4882a593Smuzhiyun break;
403*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
404*4882a593Smuzhiyun *val = 1; /* 0.0625 */
405*4882a593Smuzhiyun *val2 = 16;
406*4882a593Smuzhiyun ret = IIO_VAL_FRACTIONAL;
407*4882a593Smuzhiyun break;
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun return ret;
411*4882a593Smuzhiyun }
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun static const struct iio_info max30100_info = {
414*4882a593Smuzhiyun .read_raw = max30100_read_raw,
415*4882a593Smuzhiyun };
416*4882a593Smuzhiyun
max30100_probe(struct i2c_client * client,const struct i2c_device_id * id)417*4882a593Smuzhiyun static int max30100_probe(struct i2c_client *client,
418*4882a593Smuzhiyun const struct i2c_device_id *id)
419*4882a593Smuzhiyun {
420*4882a593Smuzhiyun struct max30100_data *data;
421*4882a593Smuzhiyun struct iio_buffer *buffer;
422*4882a593Smuzhiyun struct iio_dev *indio_dev;
423*4882a593Smuzhiyun int ret;
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
426*4882a593Smuzhiyun if (!indio_dev)
427*4882a593Smuzhiyun return -ENOMEM;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun buffer = devm_iio_kfifo_allocate(&client->dev);
430*4882a593Smuzhiyun if (!buffer)
431*4882a593Smuzhiyun return -ENOMEM;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun iio_device_attach_buffer(indio_dev, buffer);
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun indio_dev->name = MAX30100_DRV_NAME;
436*4882a593Smuzhiyun indio_dev->channels = max30100_channels;
437*4882a593Smuzhiyun indio_dev->info = &max30100_info;
438*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(max30100_channels);
439*4882a593Smuzhiyun indio_dev->available_scan_masks = max30100_scan_masks;
440*4882a593Smuzhiyun indio_dev->modes = (INDIO_BUFFER_SOFTWARE | INDIO_DIRECT_MODE);
441*4882a593Smuzhiyun indio_dev->setup_ops = &max30100_buffer_setup_ops;
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun data = iio_priv(indio_dev);
444*4882a593Smuzhiyun data->indio_dev = indio_dev;
445*4882a593Smuzhiyun data->client = client;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun mutex_init(&data->lock);
448*4882a593Smuzhiyun i2c_set_clientdata(client, indio_dev);
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun data->regmap = devm_regmap_init_i2c(client, &max30100_regmap_config);
451*4882a593Smuzhiyun if (IS_ERR(data->regmap)) {
452*4882a593Smuzhiyun dev_err(&client->dev, "regmap initialization failed.\n");
453*4882a593Smuzhiyun return PTR_ERR(data->regmap);
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun max30100_set_powermode(data, false);
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun ret = max30100_chip_init(data);
458*4882a593Smuzhiyun if (ret)
459*4882a593Smuzhiyun return ret;
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun if (client->irq <= 0) {
462*4882a593Smuzhiyun dev_err(&client->dev, "no valid irq defined\n");
463*4882a593Smuzhiyun return -EINVAL;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun ret = devm_request_threaded_irq(&client->dev, client->irq,
466*4882a593Smuzhiyun NULL, max30100_interrupt_handler,
467*4882a593Smuzhiyun IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
468*4882a593Smuzhiyun "max30100_irq", indio_dev);
469*4882a593Smuzhiyun if (ret) {
470*4882a593Smuzhiyun dev_err(&client->dev, "request irq (%d) failed\n", client->irq);
471*4882a593Smuzhiyun return ret;
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun return iio_device_register(indio_dev);
475*4882a593Smuzhiyun }
476*4882a593Smuzhiyun
max30100_remove(struct i2c_client * client)477*4882a593Smuzhiyun static int max30100_remove(struct i2c_client *client)
478*4882a593Smuzhiyun {
479*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(client);
480*4882a593Smuzhiyun struct max30100_data *data = iio_priv(indio_dev);
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun iio_device_unregister(indio_dev);
483*4882a593Smuzhiyun max30100_set_powermode(data, false);
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun return 0;
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun static const struct i2c_device_id max30100_id[] = {
489*4882a593Smuzhiyun { "max30100", 0 },
490*4882a593Smuzhiyun {}
491*4882a593Smuzhiyun };
492*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, max30100_id);
493*4882a593Smuzhiyun
494*4882a593Smuzhiyun static const struct of_device_id max30100_dt_ids[] = {
495*4882a593Smuzhiyun { .compatible = "maxim,max30100" },
496*4882a593Smuzhiyun { }
497*4882a593Smuzhiyun };
498*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, max30100_dt_ids);
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun static struct i2c_driver max30100_driver = {
501*4882a593Smuzhiyun .driver = {
502*4882a593Smuzhiyun .name = MAX30100_DRV_NAME,
503*4882a593Smuzhiyun .of_match_table = max30100_dt_ids,
504*4882a593Smuzhiyun },
505*4882a593Smuzhiyun .probe = max30100_probe,
506*4882a593Smuzhiyun .remove = max30100_remove,
507*4882a593Smuzhiyun .id_table = max30100_id,
508*4882a593Smuzhiyun };
509*4882a593Smuzhiyun module_i2c_driver(max30100_driver);
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun MODULE_AUTHOR("Matt Ranostay <matt.ranostay@konsulko.com>");
512*4882a593Smuzhiyun MODULE_DESCRIPTION("MAX30100 heart rate and pulse oximeter sensor");
513*4882a593Smuzhiyun MODULE_LICENSE("GPL");
514