xref: /OK3568_Linux_fs/kernel/drivers/iio/health/afe4404.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * AFE4404 Heart Rate Monitors and Low-Cost Pulse Oximeters
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
6*4882a593Smuzhiyun  *	Andrew F. Davis <afd@ti.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/err.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/i2c.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/regmap.h>
16*4882a593Smuzhiyun #include <linux/sysfs.h>
17*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <linux/iio/iio.h>
20*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
21*4882a593Smuzhiyun #include <linux/iio/buffer.h>
22*4882a593Smuzhiyun #include <linux/iio/trigger.h>
23*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
24*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #include "afe440x.h"
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define AFE4404_DRIVER_NAME		"afe4404"
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun /* AFE4404 registers */
31*4882a593Smuzhiyun #define AFE4404_TIA_GAIN_SEP		0x20
32*4882a593Smuzhiyun #define AFE4404_TIA_GAIN		0x21
33*4882a593Smuzhiyun #define AFE4404_PROG_TG_STC		0x34
34*4882a593Smuzhiyun #define AFE4404_PROG_TG_ENDC		0x35
35*4882a593Smuzhiyun #define AFE4404_LED3LEDSTC		0x36
36*4882a593Smuzhiyun #define AFE4404_LED3LEDENDC		0x37
37*4882a593Smuzhiyun #define AFE4404_CLKDIV_PRF		0x39
38*4882a593Smuzhiyun #define AFE4404_OFFDAC			0x3a
39*4882a593Smuzhiyun #define AFE4404_DEC			0x3d
40*4882a593Smuzhiyun #define AFE4404_AVG_LED2_ALED2VAL	0x3f
41*4882a593Smuzhiyun #define AFE4404_AVG_LED1_ALED1VAL	0x40
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun /* AFE4404 CONTROL2 register fields */
44*4882a593Smuzhiyun #define AFE440X_CONTROL2_OSC_ENABLE	BIT(9)
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun enum afe4404_fields {
47*4882a593Smuzhiyun 	/* Gains */
48*4882a593Smuzhiyun 	F_TIA_GAIN_SEP, F_TIA_CF_SEP,
49*4882a593Smuzhiyun 	F_TIA_GAIN, TIA_CF,
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	/* LED Current */
52*4882a593Smuzhiyun 	F_ILED1, F_ILED2, F_ILED3,
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	/* Offset DAC */
55*4882a593Smuzhiyun 	F_OFFDAC_AMB2, F_OFFDAC_LED1, F_OFFDAC_AMB1, F_OFFDAC_LED2,
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	/* sentinel */
58*4882a593Smuzhiyun 	F_MAX_FIELDS
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun static const struct reg_field afe4404_reg_fields[] = {
62*4882a593Smuzhiyun 	/* Gains */
63*4882a593Smuzhiyun 	[F_TIA_GAIN_SEP]	= REG_FIELD(AFE4404_TIA_GAIN_SEP, 0, 2),
64*4882a593Smuzhiyun 	[F_TIA_CF_SEP]		= REG_FIELD(AFE4404_TIA_GAIN_SEP, 3, 5),
65*4882a593Smuzhiyun 	[F_TIA_GAIN]		= REG_FIELD(AFE4404_TIA_GAIN, 0, 2),
66*4882a593Smuzhiyun 	[TIA_CF]		= REG_FIELD(AFE4404_TIA_GAIN, 3, 5),
67*4882a593Smuzhiyun 	/* LED Current */
68*4882a593Smuzhiyun 	[F_ILED1]		= REG_FIELD(AFE440X_LEDCNTRL, 0, 5),
69*4882a593Smuzhiyun 	[F_ILED2]		= REG_FIELD(AFE440X_LEDCNTRL, 6, 11),
70*4882a593Smuzhiyun 	[F_ILED3]		= REG_FIELD(AFE440X_LEDCNTRL, 12, 17),
71*4882a593Smuzhiyun 	/* Offset DAC */
72*4882a593Smuzhiyun 	[F_OFFDAC_AMB2]		= REG_FIELD(AFE4404_OFFDAC, 0, 4),
73*4882a593Smuzhiyun 	[F_OFFDAC_LED1]		= REG_FIELD(AFE4404_OFFDAC, 5, 9),
74*4882a593Smuzhiyun 	[F_OFFDAC_AMB1]		= REG_FIELD(AFE4404_OFFDAC, 10, 14),
75*4882a593Smuzhiyun 	[F_OFFDAC_LED2]		= REG_FIELD(AFE4404_OFFDAC, 15, 19),
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun /**
79*4882a593Smuzhiyun  * struct afe4404_data - AFE4404 device instance data
80*4882a593Smuzhiyun  * @dev: Device structure
81*4882a593Smuzhiyun  * @regmap: Register map of the device
82*4882a593Smuzhiyun  * @fields: Register fields of the device
83*4882a593Smuzhiyun  * @regulator: Pointer to the regulator for the IC
84*4882a593Smuzhiyun  * @trig: IIO trigger for this device
85*4882a593Smuzhiyun  * @irq: ADC_RDY line interrupt number
86*4882a593Smuzhiyun  * @buffer: Used to construct a scan to push to the iio buffer.
87*4882a593Smuzhiyun  */
88*4882a593Smuzhiyun struct afe4404_data {
89*4882a593Smuzhiyun 	struct device *dev;
90*4882a593Smuzhiyun 	struct regmap *regmap;
91*4882a593Smuzhiyun 	struct regmap_field *fields[F_MAX_FIELDS];
92*4882a593Smuzhiyun 	struct regulator *regulator;
93*4882a593Smuzhiyun 	struct iio_trigger *trig;
94*4882a593Smuzhiyun 	int irq;
95*4882a593Smuzhiyun 	s32 buffer[10] __aligned(8);
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun enum afe4404_chan_id {
99*4882a593Smuzhiyun 	LED2 = 1,
100*4882a593Smuzhiyun 	ALED2,
101*4882a593Smuzhiyun 	LED1,
102*4882a593Smuzhiyun 	ALED1,
103*4882a593Smuzhiyun 	LED2_ALED2,
104*4882a593Smuzhiyun 	LED1_ALED1,
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun static const unsigned int afe4404_channel_values[] = {
108*4882a593Smuzhiyun 	[LED2] = AFE440X_LED2VAL,
109*4882a593Smuzhiyun 	[ALED2] = AFE440X_ALED2VAL,
110*4882a593Smuzhiyun 	[LED1] = AFE440X_LED1VAL,
111*4882a593Smuzhiyun 	[ALED1] = AFE440X_ALED1VAL,
112*4882a593Smuzhiyun 	[LED2_ALED2] = AFE440X_LED2_ALED2VAL,
113*4882a593Smuzhiyun 	[LED1_ALED1] = AFE440X_LED1_ALED1VAL,
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun static const unsigned int afe4404_channel_leds[] = {
117*4882a593Smuzhiyun 	[LED2] = F_ILED2,
118*4882a593Smuzhiyun 	[ALED2] = F_ILED3,
119*4882a593Smuzhiyun 	[LED1] = F_ILED1,
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun static const unsigned int afe4404_channel_offdacs[] = {
123*4882a593Smuzhiyun 	[LED2] = F_OFFDAC_LED2,
124*4882a593Smuzhiyun 	[ALED2] = F_OFFDAC_AMB2,
125*4882a593Smuzhiyun 	[LED1] = F_OFFDAC_LED1,
126*4882a593Smuzhiyun 	[ALED1] = F_OFFDAC_AMB1,
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun static const struct iio_chan_spec afe4404_channels[] = {
130*4882a593Smuzhiyun 	/* ADC values */
131*4882a593Smuzhiyun 	AFE440X_INTENSITY_CHAN(LED2, BIT(IIO_CHAN_INFO_OFFSET)),
132*4882a593Smuzhiyun 	AFE440X_INTENSITY_CHAN(ALED2, BIT(IIO_CHAN_INFO_OFFSET)),
133*4882a593Smuzhiyun 	AFE440X_INTENSITY_CHAN(LED1, BIT(IIO_CHAN_INFO_OFFSET)),
134*4882a593Smuzhiyun 	AFE440X_INTENSITY_CHAN(ALED1, BIT(IIO_CHAN_INFO_OFFSET)),
135*4882a593Smuzhiyun 	AFE440X_INTENSITY_CHAN(LED2_ALED2, 0),
136*4882a593Smuzhiyun 	AFE440X_INTENSITY_CHAN(LED1_ALED1, 0),
137*4882a593Smuzhiyun 	/* LED current */
138*4882a593Smuzhiyun 	AFE440X_CURRENT_CHAN(LED2),
139*4882a593Smuzhiyun 	AFE440X_CURRENT_CHAN(ALED2),
140*4882a593Smuzhiyun 	AFE440X_CURRENT_CHAN(LED1),
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun static const struct afe440x_val_table afe4404_res_table[] = {
144*4882a593Smuzhiyun 	{ .integer = 500000, .fract = 0 },
145*4882a593Smuzhiyun 	{ .integer = 250000, .fract = 0 },
146*4882a593Smuzhiyun 	{ .integer = 100000, .fract = 0 },
147*4882a593Smuzhiyun 	{ .integer = 50000, .fract = 0 },
148*4882a593Smuzhiyun 	{ .integer = 25000, .fract = 0 },
149*4882a593Smuzhiyun 	{ .integer = 10000, .fract = 0 },
150*4882a593Smuzhiyun 	{ .integer = 1000000, .fract = 0 },
151*4882a593Smuzhiyun 	{ .integer = 2000000, .fract = 0 },
152*4882a593Smuzhiyun };
153*4882a593Smuzhiyun AFE440X_TABLE_ATTR(in_intensity_resistance_available, afe4404_res_table);
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun static const struct afe440x_val_table afe4404_cap_table[] = {
156*4882a593Smuzhiyun 	{ .integer = 0, .fract = 5000 },
157*4882a593Smuzhiyun 	{ .integer = 0, .fract = 2500 },
158*4882a593Smuzhiyun 	{ .integer = 0, .fract = 10000 },
159*4882a593Smuzhiyun 	{ .integer = 0, .fract = 7500 },
160*4882a593Smuzhiyun 	{ .integer = 0, .fract = 20000 },
161*4882a593Smuzhiyun 	{ .integer = 0, .fract = 17500 },
162*4882a593Smuzhiyun 	{ .integer = 0, .fract = 25000 },
163*4882a593Smuzhiyun 	{ .integer = 0, .fract = 22500 },
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun AFE440X_TABLE_ATTR(in_intensity_capacitance_available, afe4404_cap_table);
166*4882a593Smuzhiyun 
afe440x_show_register(struct device * dev,struct device_attribute * attr,char * buf)167*4882a593Smuzhiyun static ssize_t afe440x_show_register(struct device *dev,
168*4882a593Smuzhiyun 				     struct device_attribute *attr,
169*4882a593Smuzhiyun 				     char *buf)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
172*4882a593Smuzhiyun 	struct afe4404_data *afe = iio_priv(indio_dev);
173*4882a593Smuzhiyun 	struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
174*4882a593Smuzhiyun 	unsigned int reg_val;
175*4882a593Smuzhiyun 	int vals[2];
176*4882a593Smuzhiyun 	int ret;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	ret = regmap_field_read(afe->fields[afe440x_attr->field], &reg_val);
179*4882a593Smuzhiyun 	if (ret)
180*4882a593Smuzhiyun 		return ret;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	if (reg_val >= afe440x_attr->table_size)
183*4882a593Smuzhiyun 		return -EINVAL;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	vals[0] = afe440x_attr->val_table[reg_val].integer;
186*4882a593Smuzhiyun 	vals[1] = afe440x_attr->val_table[reg_val].fract;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals);
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun 
afe440x_store_register(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)191*4882a593Smuzhiyun static ssize_t afe440x_store_register(struct device *dev,
192*4882a593Smuzhiyun 				      struct device_attribute *attr,
193*4882a593Smuzhiyun 				      const char *buf, size_t count)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
196*4882a593Smuzhiyun 	struct afe4404_data *afe = iio_priv(indio_dev);
197*4882a593Smuzhiyun 	struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
198*4882a593Smuzhiyun 	int val, integer, fract, ret;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	ret = iio_str_to_fixpoint(buf, 100000, &integer, &fract);
201*4882a593Smuzhiyun 	if (ret)
202*4882a593Smuzhiyun 		return ret;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	for (val = 0; val < afe440x_attr->table_size; val++)
205*4882a593Smuzhiyun 		if (afe440x_attr->val_table[val].integer == integer &&
206*4882a593Smuzhiyun 		    afe440x_attr->val_table[val].fract == fract)
207*4882a593Smuzhiyun 			break;
208*4882a593Smuzhiyun 	if (val == afe440x_attr->table_size)
209*4882a593Smuzhiyun 		return -EINVAL;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	ret = regmap_field_write(afe->fields[afe440x_attr->field], val);
212*4882a593Smuzhiyun 	if (ret)
213*4882a593Smuzhiyun 		return ret;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	return count;
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun static AFE440X_ATTR(in_intensity1_resistance, F_TIA_GAIN_SEP, afe4404_res_table);
219*4882a593Smuzhiyun static AFE440X_ATTR(in_intensity1_capacitance, F_TIA_CF_SEP, afe4404_cap_table);
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun static AFE440X_ATTR(in_intensity2_resistance, F_TIA_GAIN_SEP, afe4404_res_table);
222*4882a593Smuzhiyun static AFE440X_ATTR(in_intensity2_capacitance, F_TIA_CF_SEP, afe4404_cap_table);
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun static AFE440X_ATTR(in_intensity3_resistance, F_TIA_GAIN, afe4404_res_table);
225*4882a593Smuzhiyun static AFE440X_ATTR(in_intensity3_capacitance, TIA_CF, afe4404_cap_table);
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun static AFE440X_ATTR(in_intensity4_resistance, F_TIA_GAIN, afe4404_res_table);
228*4882a593Smuzhiyun static AFE440X_ATTR(in_intensity4_capacitance, TIA_CF, afe4404_cap_table);
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun static struct attribute *afe440x_attributes[] = {
231*4882a593Smuzhiyun 	&dev_attr_in_intensity_resistance_available.attr,
232*4882a593Smuzhiyun 	&dev_attr_in_intensity_capacitance_available.attr,
233*4882a593Smuzhiyun 	&afe440x_attr_in_intensity1_resistance.dev_attr.attr,
234*4882a593Smuzhiyun 	&afe440x_attr_in_intensity1_capacitance.dev_attr.attr,
235*4882a593Smuzhiyun 	&afe440x_attr_in_intensity2_resistance.dev_attr.attr,
236*4882a593Smuzhiyun 	&afe440x_attr_in_intensity2_capacitance.dev_attr.attr,
237*4882a593Smuzhiyun 	&afe440x_attr_in_intensity3_resistance.dev_attr.attr,
238*4882a593Smuzhiyun 	&afe440x_attr_in_intensity3_capacitance.dev_attr.attr,
239*4882a593Smuzhiyun 	&afe440x_attr_in_intensity4_resistance.dev_attr.attr,
240*4882a593Smuzhiyun 	&afe440x_attr_in_intensity4_capacitance.dev_attr.attr,
241*4882a593Smuzhiyun 	NULL
242*4882a593Smuzhiyun };
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun static const struct attribute_group afe440x_attribute_group = {
245*4882a593Smuzhiyun 	.attrs = afe440x_attributes
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun 
afe4404_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)248*4882a593Smuzhiyun static int afe4404_read_raw(struct iio_dev *indio_dev,
249*4882a593Smuzhiyun 			    struct iio_chan_spec const *chan,
250*4882a593Smuzhiyun 			    int *val, int *val2, long mask)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun 	struct afe4404_data *afe = iio_priv(indio_dev);
253*4882a593Smuzhiyun 	unsigned int value_reg, led_field, offdac_field;
254*4882a593Smuzhiyun 	int ret;
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	switch (chan->type) {
257*4882a593Smuzhiyun 	case IIO_INTENSITY:
258*4882a593Smuzhiyun 		switch (mask) {
259*4882a593Smuzhiyun 		case IIO_CHAN_INFO_RAW:
260*4882a593Smuzhiyun 			value_reg = afe4404_channel_values[chan->address];
261*4882a593Smuzhiyun 			ret = regmap_read(afe->regmap, value_reg, val);
262*4882a593Smuzhiyun 			if (ret)
263*4882a593Smuzhiyun 				return ret;
264*4882a593Smuzhiyun 			return IIO_VAL_INT;
265*4882a593Smuzhiyun 		case IIO_CHAN_INFO_OFFSET:
266*4882a593Smuzhiyun 			offdac_field = afe4404_channel_offdacs[chan->address];
267*4882a593Smuzhiyun 			ret = regmap_field_read(afe->fields[offdac_field], val);
268*4882a593Smuzhiyun 			if (ret)
269*4882a593Smuzhiyun 				return ret;
270*4882a593Smuzhiyun 			return IIO_VAL_INT;
271*4882a593Smuzhiyun 		}
272*4882a593Smuzhiyun 		break;
273*4882a593Smuzhiyun 	case IIO_CURRENT:
274*4882a593Smuzhiyun 		switch (mask) {
275*4882a593Smuzhiyun 		case IIO_CHAN_INFO_RAW:
276*4882a593Smuzhiyun 			led_field = afe4404_channel_leds[chan->address];
277*4882a593Smuzhiyun 			ret = regmap_field_read(afe->fields[led_field], val);
278*4882a593Smuzhiyun 			if (ret)
279*4882a593Smuzhiyun 				return ret;
280*4882a593Smuzhiyun 			return IIO_VAL_INT;
281*4882a593Smuzhiyun 		case IIO_CHAN_INFO_SCALE:
282*4882a593Smuzhiyun 			*val = 0;
283*4882a593Smuzhiyun 			*val2 = 800000;
284*4882a593Smuzhiyun 			return IIO_VAL_INT_PLUS_MICRO;
285*4882a593Smuzhiyun 		}
286*4882a593Smuzhiyun 		break;
287*4882a593Smuzhiyun 	default:
288*4882a593Smuzhiyun 		break;
289*4882a593Smuzhiyun 	}
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	return -EINVAL;
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun 
afe4404_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)294*4882a593Smuzhiyun static int afe4404_write_raw(struct iio_dev *indio_dev,
295*4882a593Smuzhiyun 			     struct iio_chan_spec const *chan,
296*4882a593Smuzhiyun 			     int val, int val2, long mask)
297*4882a593Smuzhiyun {
298*4882a593Smuzhiyun 	struct afe4404_data *afe = iio_priv(indio_dev);
299*4882a593Smuzhiyun 	unsigned int led_field, offdac_field;
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	switch (chan->type) {
302*4882a593Smuzhiyun 	case IIO_INTENSITY:
303*4882a593Smuzhiyun 		switch (mask) {
304*4882a593Smuzhiyun 		case IIO_CHAN_INFO_OFFSET:
305*4882a593Smuzhiyun 			offdac_field = afe4404_channel_offdacs[chan->address];
306*4882a593Smuzhiyun 			return regmap_field_write(afe->fields[offdac_field], val);
307*4882a593Smuzhiyun 		}
308*4882a593Smuzhiyun 		break;
309*4882a593Smuzhiyun 	case IIO_CURRENT:
310*4882a593Smuzhiyun 		switch (mask) {
311*4882a593Smuzhiyun 		case IIO_CHAN_INFO_RAW:
312*4882a593Smuzhiyun 			led_field = afe4404_channel_leds[chan->address];
313*4882a593Smuzhiyun 			return regmap_field_write(afe->fields[led_field], val);
314*4882a593Smuzhiyun 		}
315*4882a593Smuzhiyun 		break;
316*4882a593Smuzhiyun 	default:
317*4882a593Smuzhiyun 		break;
318*4882a593Smuzhiyun 	}
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 	return -EINVAL;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun static const struct iio_info afe4404_iio_info = {
324*4882a593Smuzhiyun 	.attrs = &afe440x_attribute_group,
325*4882a593Smuzhiyun 	.read_raw = afe4404_read_raw,
326*4882a593Smuzhiyun 	.write_raw = afe4404_write_raw,
327*4882a593Smuzhiyun };
328*4882a593Smuzhiyun 
afe4404_trigger_handler(int irq,void * private)329*4882a593Smuzhiyun static irqreturn_t afe4404_trigger_handler(int irq, void *private)
330*4882a593Smuzhiyun {
331*4882a593Smuzhiyun 	struct iio_poll_func *pf = private;
332*4882a593Smuzhiyun 	struct iio_dev *indio_dev = pf->indio_dev;
333*4882a593Smuzhiyun 	struct afe4404_data *afe = iio_priv(indio_dev);
334*4882a593Smuzhiyun 	int ret, bit, i = 0;
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	for_each_set_bit(bit, indio_dev->active_scan_mask,
337*4882a593Smuzhiyun 			 indio_dev->masklength) {
338*4882a593Smuzhiyun 		ret = regmap_read(afe->regmap, afe4404_channel_values[bit],
339*4882a593Smuzhiyun 				  &afe->buffer[i++]);
340*4882a593Smuzhiyun 		if (ret)
341*4882a593Smuzhiyun 			goto err;
342*4882a593Smuzhiyun 	}
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	iio_push_to_buffers_with_timestamp(indio_dev, afe->buffer,
345*4882a593Smuzhiyun 					   pf->timestamp);
346*4882a593Smuzhiyun err:
347*4882a593Smuzhiyun 	iio_trigger_notify_done(indio_dev->trig);
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	return IRQ_HANDLED;
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun static const struct iio_trigger_ops afe4404_trigger_ops = {
353*4882a593Smuzhiyun };
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun /* Default timings from data-sheet */
356*4882a593Smuzhiyun #define AFE4404_TIMING_PAIRS			\
357*4882a593Smuzhiyun 	{ AFE440X_PRPCOUNT,	39999	},	\
358*4882a593Smuzhiyun 	{ AFE440X_LED2LEDSTC,	0	},	\
359*4882a593Smuzhiyun 	{ AFE440X_LED2LEDENDC,	398	},	\
360*4882a593Smuzhiyun 	{ AFE440X_LED2STC,	80	},	\
361*4882a593Smuzhiyun 	{ AFE440X_LED2ENDC,	398	},	\
362*4882a593Smuzhiyun 	{ AFE440X_ADCRSTSTCT0,	5600	},	\
363*4882a593Smuzhiyun 	{ AFE440X_ADCRSTENDCT0,	5606	},	\
364*4882a593Smuzhiyun 	{ AFE440X_LED2CONVST,	5607	},	\
365*4882a593Smuzhiyun 	{ AFE440X_LED2CONVEND,	6066	},	\
366*4882a593Smuzhiyun 	{ AFE4404_LED3LEDSTC,	400	},	\
367*4882a593Smuzhiyun 	{ AFE4404_LED3LEDENDC,	798	},	\
368*4882a593Smuzhiyun 	{ AFE440X_ALED2STC,	480	},	\
369*4882a593Smuzhiyun 	{ AFE440X_ALED2ENDC,	798	},	\
370*4882a593Smuzhiyun 	{ AFE440X_ADCRSTSTCT1,	6068	},	\
371*4882a593Smuzhiyun 	{ AFE440X_ADCRSTENDCT1,	6074	},	\
372*4882a593Smuzhiyun 	{ AFE440X_ALED2CONVST,	6075	},	\
373*4882a593Smuzhiyun 	{ AFE440X_ALED2CONVEND,	6534	},	\
374*4882a593Smuzhiyun 	{ AFE440X_LED1LEDSTC,	800	},	\
375*4882a593Smuzhiyun 	{ AFE440X_LED1LEDENDC,	1198	},	\
376*4882a593Smuzhiyun 	{ AFE440X_LED1STC,	880	},	\
377*4882a593Smuzhiyun 	{ AFE440X_LED1ENDC,	1198	},	\
378*4882a593Smuzhiyun 	{ AFE440X_ADCRSTSTCT2,	6536	},	\
379*4882a593Smuzhiyun 	{ AFE440X_ADCRSTENDCT2,	6542	},	\
380*4882a593Smuzhiyun 	{ AFE440X_LED1CONVST,	6543	},	\
381*4882a593Smuzhiyun 	{ AFE440X_LED1CONVEND,	7003	},	\
382*4882a593Smuzhiyun 	{ AFE440X_ALED1STC,	1280	},	\
383*4882a593Smuzhiyun 	{ AFE440X_ALED1ENDC,	1598	},	\
384*4882a593Smuzhiyun 	{ AFE440X_ADCRSTSTCT3,	7005	},	\
385*4882a593Smuzhiyun 	{ AFE440X_ADCRSTENDCT3,	7011	},	\
386*4882a593Smuzhiyun 	{ AFE440X_ALED1CONVST,	7012	},	\
387*4882a593Smuzhiyun 	{ AFE440X_ALED1CONVEND,	7471	},	\
388*4882a593Smuzhiyun 	{ AFE440X_PDNCYCLESTC,	7671	},	\
389*4882a593Smuzhiyun 	{ AFE440X_PDNCYCLEENDC,	39199	}
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun static const struct reg_sequence afe4404_reg_sequences[] = {
392*4882a593Smuzhiyun 	AFE4404_TIMING_PAIRS,
393*4882a593Smuzhiyun 	{ AFE440X_CONTROL1, AFE440X_CONTROL1_TIMEREN },
394*4882a593Smuzhiyun 	{ AFE4404_TIA_GAIN_SEP, AFE440X_TIAGAIN_ENSEPGAIN },
395*4882a593Smuzhiyun 	{ AFE440X_CONTROL2, AFE440X_CONTROL2_OSC_ENABLE	},
396*4882a593Smuzhiyun };
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun static const struct regmap_range afe4404_yes_ranges[] = {
399*4882a593Smuzhiyun 	regmap_reg_range(AFE440X_LED2VAL, AFE440X_LED1_ALED1VAL),
400*4882a593Smuzhiyun 	regmap_reg_range(AFE4404_AVG_LED2_ALED2VAL, AFE4404_AVG_LED1_ALED1VAL),
401*4882a593Smuzhiyun };
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun static const struct regmap_access_table afe4404_volatile_table = {
404*4882a593Smuzhiyun 	.yes_ranges = afe4404_yes_ranges,
405*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(afe4404_yes_ranges),
406*4882a593Smuzhiyun };
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun static const struct regmap_config afe4404_regmap_config = {
409*4882a593Smuzhiyun 	.reg_bits = 8,
410*4882a593Smuzhiyun 	.val_bits = 24,
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	.max_register = AFE4404_AVG_LED1_ALED1VAL,
413*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
414*4882a593Smuzhiyun 	.volatile_table = &afe4404_volatile_table,
415*4882a593Smuzhiyun };
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun static const struct of_device_id afe4404_of_match[] = {
418*4882a593Smuzhiyun 	{ .compatible = "ti,afe4404", },
419*4882a593Smuzhiyun 	{ /* sentinel */ }
420*4882a593Smuzhiyun };
421*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, afe4404_of_match);
422*4882a593Smuzhiyun 
afe4404_suspend(struct device * dev)423*4882a593Smuzhiyun static int __maybe_unused afe4404_suspend(struct device *dev)
424*4882a593Smuzhiyun {
425*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
426*4882a593Smuzhiyun 	struct afe4404_data *afe = iio_priv(indio_dev);
427*4882a593Smuzhiyun 	int ret;
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun 	ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
430*4882a593Smuzhiyun 				 AFE440X_CONTROL2_PDN_AFE,
431*4882a593Smuzhiyun 				 AFE440X_CONTROL2_PDN_AFE);
432*4882a593Smuzhiyun 	if (ret)
433*4882a593Smuzhiyun 		return ret;
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	ret = regulator_disable(afe->regulator);
436*4882a593Smuzhiyun 	if (ret) {
437*4882a593Smuzhiyun 		dev_err(dev, "Unable to disable regulator\n");
438*4882a593Smuzhiyun 		return ret;
439*4882a593Smuzhiyun 	}
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun 	return 0;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun 
afe4404_resume(struct device * dev)444*4882a593Smuzhiyun static int __maybe_unused afe4404_resume(struct device *dev)
445*4882a593Smuzhiyun {
446*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
447*4882a593Smuzhiyun 	struct afe4404_data *afe = iio_priv(indio_dev);
448*4882a593Smuzhiyun 	int ret;
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun 	ret = regulator_enable(afe->regulator);
451*4882a593Smuzhiyun 	if (ret) {
452*4882a593Smuzhiyun 		dev_err(dev, "Unable to enable regulator\n");
453*4882a593Smuzhiyun 		return ret;
454*4882a593Smuzhiyun 	}
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
457*4882a593Smuzhiyun 				 AFE440X_CONTROL2_PDN_AFE, 0);
458*4882a593Smuzhiyun 	if (ret)
459*4882a593Smuzhiyun 		return ret;
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun 	return 0;
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(afe4404_pm_ops, afe4404_suspend, afe4404_resume);
465*4882a593Smuzhiyun 
afe4404_probe(struct i2c_client * client,const struct i2c_device_id * id)466*4882a593Smuzhiyun static int afe4404_probe(struct i2c_client *client,
467*4882a593Smuzhiyun 			 const struct i2c_device_id *id)
468*4882a593Smuzhiyun {
469*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
470*4882a593Smuzhiyun 	struct afe4404_data *afe;
471*4882a593Smuzhiyun 	int i, ret;
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*afe));
474*4882a593Smuzhiyun 	if (!indio_dev)
475*4882a593Smuzhiyun 		return -ENOMEM;
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun 	afe = iio_priv(indio_dev);
478*4882a593Smuzhiyun 	i2c_set_clientdata(client, indio_dev);
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	afe->dev = &client->dev;
481*4882a593Smuzhiyun 	afe->irq = client->irq;
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 	afe->regmap = devm_regmap_init_i2c(client, &afe4404_regmap_config);
484*4882a593Smuzhiyun 	if (IS_ERR(afe->regmap)) {
485*4882a593Smuzhiyun 		dev_err(afe->dev, "Unable to allocate register map\n");
486*4882a593Smuzhiyun 		return PTR_ERR(afe->regmap);
487*4882a593Smuzhiyun 	}
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun 	for (i = 0; i < F_MAX_FIELDS; i++) {
490*4882a593Smuzhiyun 		afe->fields[i] = devm_regmap_field_alloc(afe->dev, afe->regmap,
491*4882a593Smuzhiyun 							 afe4404_reg_fields[i]);
492*4882a593Smuzhiyun 		if (IS_ERR(afe->fields[i])) {
493*4882a593Smuzhiyun 			dev_err(afe->dev, "Unable to allocate regmap fields\n");
494*4882a593Smuzhiyun 			return PTR_ERR(afe->fields[i]);
495*4882a593Smuzhiyun 		}
496*4882a593Smuzhiyun 	}
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun 	afe->regulator = devm_regulator_get(afe->dev, "tx_sup");
499*4882a593Smuzhiyun 	if (IS_ERR(afe->regulator)) {
500*4882a593Smuzhiyun 		dev_err(afe->dev, "Unable to get regulator\n");
501*4882a593Smuzhiyun 		return PTR_ERR(afe->regulator);
502*4882a593Smuzhiyun 	}
503*4882a593Smuzhiyun 	ret = regulator_enable(afe->regulator);
504*4882a593Smuzhiyun 	if (ret) {
505*4882a593Smuzhiyun 		dev_err(afe->dev, "Unable to enable regulator\n");
506*4882a593Smuzhiyun 		return ret;
507*4882a593Smuzhiyun 	}
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	ret = regmap_write(afe->regmap, AFE440X_CONTROL0,
510*4882a593Smuzhiyun 			   AFE440X_CONTROL0_SW_RESET);
511*4882a593Smuzhiyun 	if (ret) {
512*4882a593Smuzhiyun 		dev_err(afe->dev, "Unable to reset device\n");
513*4882a593Smuzhiyun 		goto disable_reg;
514*4882a593Smuzhiyun 	}
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	ret = regmap_multi_reg_write(afe->regmap, afe4404_reg_sequences,
517*4882a593Smuzhiyun 				     ARRAY_SIZE(afe4404_reg_sequences));
518*4882a593Smuzhiyun 	if (ret) {
519*4882a593Smuzhiyun 		dev_err(afe->dev, "Unable to set register defaults\n");
520*4882a593Smuzhiyun 		goto disable_reg;
521*4882a593Smuzhiyun 	}
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
524*4882a593Smuzhiyun 	indio_dev->channels = afe4404_channels;
525*4882a593Smuzhiyun 	indio_dev->num_channels = ARRAY_SIZE(afe4404_channels);
526*4882a593Smuzhiyun 	indio_dev->name = AFE4404_DRIVER_NAME;
527*4882a593Smuzhiyun 	indio_dev->info = &afe4404_iio_info;
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	if (afe->irq > 0) {
530*4882a593Smuzhiyun 		afe->trig = devm_iio_trigger_alloc(afe->dev,
531*4882a593Smuzhiyun 						   "%s-dev%d",
532*4882a593Smuzhiyun 						   indio_dev->name,
533*4882a593Smuzhiyun 						   indio_dev->id);
534*4882a593Smuzhiyun 		if (!afe->trig) {
535*4882a593Smuzhiyun 			dev_err(afe->dev, "Unable to allocate IIO trigger\n");
536*4882a593Smuzhiyun 			ret = -ENOMEM;
537*4882a593Smuzhiyun 			goto disable_reg;
538*4882a593Smuzhiyun 		}
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 		iio_trigger_set_drvdata(afe->trig, indio_dev);
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 		afe->trig->ops = &afe4404_trigger_ops;
543*4882a593Smuzhiyun 		afe->trig->dev.parent = afe->dev;
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun 		ret = iio_trigger_register(afe->trig);
546*4882a593Smuzhiyun 		if (ret) {
547*4882a593Smuzhiyun 			dev_err(afe->dev, "Unable to register IIO trigger\n");
548*4882a593Smuzhiyun 			goto disable_reg;
549*4882a593Smuzhiyun 		}
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 		ret = devm_request_threaded_irq(afe->dev, afe->irq,
552*4882a593Smuzhiyun 						iio_trigger_generic_data_rdy_poll,
553*4882a593Smuzhiyun 						NULL, IRQF_ONESHOT,
554*4882a593Smuzhiyun 						AFE4404_DRIVER_NAME,
555*4882a593Smuzhiyun 						afe->trig);
556*4882a593Smuzhiyun 		if (ret) {
557*4882a593Smuzhiyun 			dev_err(afe->dev, "Unable to request IRQ\n");
558*4882a593Smuzhiyun 			goto disable_reg;
559*4882a593Smuzhiyun 		}
560*4882a593Smuzhiyun 	}
561*4882a593Smuzhiyun 
562*4882a593Smuzhiyun 	ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
563*4882a593Smuzhiyun 					 afe4404_trigger_handler, NULL);
564*4882a593Smuzhiyun 	if (ret) {
565*4882a593Smuzhiyun 		dev_err(afe->dev, "Unable to setup buffer\n");
566*4882a593Smuzhiyun 		goto unregister_trigger;
567*4882a593Smuzhiyun 	}
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun 	ret = iio_device_register(indio_dev);
570*4882a593Smuzhiyun 	if (ret) {
571*4882a593Smuzhiyun 		dev_err(afe->dev, "Unable to register IIO device\n");
572*4882a593Smuzhiyun 		goto unregister_triggered_buffer;
573*4882a593Smuzhiyun 	}
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	return 0;
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun unregister_triggered_buffer:
578*4882a593Smuzhiyun 	iio_triggered_buffer_cleanup(indio_dev);
579*4882a593Smuzhiyun unregister_trigger:
580*4882a593Smuzhiyun 	if (afe->irq > 0)
581*4882a593Smuzhiyun 		iio_trigger_unregister(afe->trig);
582*4882a593Smuzhiyun disable_reg:
583*4882a593Smuzhiyun 	regulator_disable(afe->regulator);
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	return ret;
586*4882a593Smuzhiyun }
587*4882a593Smuzhiyun 
afe4404_remove(struct i2c_client * client)588*4882a593Smuzhiyun static int afe4404_remove(struct i2c_client *client)
589*4882a593Smuzhiyun {
590*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
591*4882a593Smuzhiyun 	struct afe4404_data *afe = iio_priv(indio_dev);
592*4882a593Smuzhiyun 	int ret;
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	iio_device_unregister(indio_dev);
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun 	iio_triggered_buffer_cleanup(indio_dev);
597*4882a593Smuzhiyun 
598*4882a593Smuzhiyun 	if (afe->irq > 0)
599*4882a593Smuzhiyun 		iio_trigger_unregister(afe->trig);
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun 	ret = regulator_disable(afe->regulator);
602*4882a593Smuzhiyun 	if (ret) {
603*4882a593Smuzhiyun 		dev_err(afe->dev, "Unable to disable regulator\n");
604*4882a593Smuzhiyun 		return ret;
605*4882a593Smuzhiyun 	}
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 	return 0;
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun static const struct i2c_device_id afe4404_ids[] = {
611*4882a593Smuzhiyun 	{ "afe4404", 0 },
612*4882a593Smuzhiyun 	{ /* sentinel */ }
613*4882a593Smuzhiyun };
614*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, afe4404_ids);
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun static struct i2c_driver afe4404_i2c_driver = {
617*4882a593Smuzhiyun 	.driver = {
618*4882a593Smuzhiyun 		.name = AFE4404_DRIVER_NAME,
619*4882a593Smuzhiyun 		.of_match_table = afe4404_of_match,
620*4882a593Smuzhiyun 		.pm = &afe4404_pm_ops,
621*4882a593Smuzhiyun 	},
622*4882a593Smuzhiyun 	.probe = afe4404_probe,
623*4882a593Smuzhiyun 	.remove = afe4404_remove,
624*4882a593Smuzhiyun 	.id_table = afe4404_ids,
625*4882a593Smuzhiyun };
626*4882a593Smuzhiyun module_i2c_driver(afe4404_i2c_driver);
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
629*4882a593Smuzhiyun MODULE_DESCRIPTION("TI AFE4404 Heart Rate Monitor and Pulse Oximeter AFE");
630*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
631