xref: /OK3568_Linux_fs/kernel/drivers/iio/health/afe4403.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * AFE4403 Heart Rate Monitors and Low-Cost Pulse Oximeters
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
6*4882a593Smuzhiyun  *	Andrew F. Davis <afd@ti.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/err.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/regmap.h>
15*4882a593Smuzhiyun #include <linux/spi/spi.h>
16*4882a593Smuzhiyun #include <linux/sysfs.h>
17*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <linux/iio/iio.h>
20*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
21*4882a593Smuzhiyun #include <linux/iio/buffer.h>
22*4882a593Smuzhiyun #include <linux/iio/trigger.h>
23*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
24*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #include <asm/unaligned.h>
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #include "afe440x.h"
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define AFE4403_DRIVER_NAME		"afe4403"
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /* AFE4403 Registers */
33*4882a593Smuzhiyun #define AFE4403_TIAGAIN			0x20
34*4882a593Smuzhiyun #define AFE4403_TIA_AMB_GAIN		0x21
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun enum afe4403_fields {
37*4882a593Smuzhiyun 	/* Gains */
38*4882a593Smuzhiyun 	F_RF_LED1, F_CF_LED1,
39*4882a593Smuzhiyun 	F_RF_LED, F_CF_LED,
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun 	/* LED Current */
42*4882a593Smuzhiyun 	F_ILED1, F_ILED2,
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	/* sentinel */
45*4882a593Smuzhiyun 	F_MAX_FIELDS
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun static const struct reg_field afe4403_reg_fields[] = {
49*4882a593Smuzhiyun 	/* Gains */
50*4882a593Smuzhiyun 	[F_RF_LED1]	= REG_FIELD(AFE4403_TIAGAIN, 0, 2),
51*4882a593Smuzhiyun 	[F_CF_LED1]	= REG_FIELD(AFE4403_TIAGAIN, 3, 7),
52*4882a593Smuzhiyun 	[F_RF_LED]	= REG_FIELD(AFE4403_TIA_AMB_GAIN, 0, 2),
53*4882a593Smuzhiyun 	[F_CF_LED]	= REG_FIELD(AFE4403_TIA_AMB_GAIN, 3, 7),
54*4882a593Smuzhiyun 	/* LED Current */
55*4882a593Smuzhiyun 	[F_ILED1]	= REG_FIELD(AFE440X_LEDCNTRL, 0, 7),
56*4882a593Smuzhiyun 	[F_ILED2]	= REG_FIELD(AFE440X_LEDCNTRL, 8, 15),
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun /**
60*4882a593Smuzhiyun  * struct afe4403_data - AFE4403 device instance data
61*4882a593Smuzhiyun  * @dev: Device structure
62*4882a593Smuzhiyun  * @spi: SPI device handle
63*4882a593Smuzhiyun  * @regmap: Register map of the device
64*4882a593Smuzhiyun  * @fields: Register fields of the device
65*4882a593Smuzhiyun  * @regulator: Pointer to the regulator for the IC
66*4882a593Smuzhiyun  * @trig: IIO trigger for this device
67*4882a593Smuzhiyun  * @irq: ADC_RDY line interrupt number
68*4882a593Smuzhiyun  * @buffer: Used to construct data layout to push into IIO buffer.
69*4882a593Smuzhiyun  */
70*4882a593Smuzhiyun struct afe4403_data {
71*4882a593Smuzhiyun 	struct device *dev;
72*4882a593Smuzhiyun 	struct spi_device *spi;
73*4882a593Smuzhiyun 	struct regmap *regmap;
74*4882a593Smuzhiyun 	struct regmap_field *fields[F_MAX_FIELDS];
75*4882a593Smuzhiyun 	struct regulator *regulator;
76*4882a593Smuzhiyun 	struct iio_trigger *trig;
77*4882a593Smuzhiyun 	int irq;
78*4882a593Smuzhiyun 	/* Ensure suitable alignment for timestamp */
79*4882a593Smuzhiyun 	s32 buffer[8] __aligned(8);
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun enum afe4403_chan_id {
83*4882a593Smuzhiyun 	LED2 = 1,
84*4882a593Smuzhiyun 	ALED2,
85*4882a593Smuzhiyun 	LED1,
86*4882a593Smuzhiyun 	ALED1,
87*4882a593Smuzhiyun 	LED2_ALED2,
88*4882a593Smuzhiyun 	LED1_ALED1,
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun static const unsigned int afe4403_channel_values[] = {
92*4882a593Smuzhiyun 	[LED2] = AFE440X_LED2VAL,
93*4882a593Smuzhiyun 	[ALED2] = AFE440X_ALED2VAL,
94*4882a593Smuzhiyun 	[LED1] = AFE440X_LED1VAL,
95*4882a593Smuzhiyun 	[ALED1] = AFE440X_ALED1VAL,
96*4882a593Smuzhiyun 	[LED2_ALED2] = AFE440X_LED2_ALED2VAL,
97*4882a593Smuzhiyun 	[LED1_ALED1] = AFE440X_LED1_ALED1VAL,
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun static const unsigned int afe4403_channel_leds[] = {
101*4882a593Smuzhiyun 	[LED2] = F_ILED2,
102*4882a593Smuzhiyun 	[LED1] = F_ILED1,
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun static const struct iio_chan_spec afe4403_channels[] = {
106*4882a593Smuzhiyun 	/* ADC values */
107*4882a593Smuzhiyun 	AFE440X_INTENSITY_CHAN(LED2, 0),
108*4882a593Smuzhiyun 	AFE440X_INTENSITY_CHAN(ALED2, 0),
109*4882a593Smuzhiyun 	AFE440X_INTENSITY_CHAN(LED1, 0),
110*4882a593Smuzhiyun 	AFE440X_INTENSITY_CHAN(ALED1, 0),
111*4882a593Smuzhiyun 	AFE440X_INTENSITY_CHAN(LED2_ALED2, 0),
112*4882a593Smuzhiyun 	AFE440X_INTENSITY_CHAN(LED1_ALED1, 0),
113*4882a593Smuzhiyun 	/* LED current */
114*4882a593Smuzhiyun 	AFE440X_CURRENT_CHAN(LED2),
115*4882a593Smuzhiyun 	AFE440X_CURRENT_CHAN(LED1),
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun static const struct afe440x_val_table afe4403_res_table[] = {
119*4882a593Smuzhiyun 	{ 500000 }, { 250000 }, { 100000 }, { 50000 },
120*4882a593Smuzhiyun 	{ 25000 }, { 10000 }, { 1000000 }, { 0 },
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun AFE440X_TABLE_ATTR(in_intensity_resistance_available, afe4403_res_table);
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun static const struct afe440x_val_table afe4403_cap_table[] = {
125*4882a593Smuzhiyun 	{ 0, 5000 }, { 0, 10000 }, { 0, 20000 }, { 0, 25000 },
126*4882a593Smuzhiyun 	{ 0, 30000 }, { 0, 35000 }, { 0, 45000 }, { 0, 50000 },
127*4882a593Smuzhiyun 	{ 0, 55000 }, { 0, 60000 }, { 0, 70000 }, { 0, 75000 },
128*4882a593Smuzhiyun 	{ 0, 80000 }, { 0, 85000 }, { 0, 95000 }, { 0, 100000 },
129*4882a593Smuzhiyun 	{ 0, 155000 }, { 0, 160000 }, { 0, 170000 }, { 0, 175000 },
130*4882a593Smuzhiyun 	{ 0, 180000 }, { 0, 185000 }, { 0, 195000 }, { 0, 200000 },
131*4882a593Smuzhiyun 	{ 0, 205000 }, { 0, 210000 }, { 0, 220000 }, { 0, 225000 },
132*4882a593Smuzhiyun 	{ 0, 230000 }, { 0, 235000 }, { 0, 245000 }, { 0, 250000 },
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun AFE440X_TABLE_ATTR(in_intensity_capacitance_available, afe4403_cap_table);
135*4882a593Smuzhiyun 
afe440x_show_register(struct device * dev,struct device_attribute * attr,char * buf)136*4882a593Smuzhiyun static ssize_t afe440x_show_register(struct device *dev,
137*4882a593Smuzhiyun 				     struct device_attribute *attr,
138*4882a593Smuzhiyun 				     char *buf)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
141*4882a593Smuzhiyun 	struct afe4403_data *afe = iio_priv(indio_dev);
142*4882a593Smuzhiyun 	struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
143*4882a593Smuzhiyun 	unsigned int reg_val;
144*4882a593Smuzhiyun 	int vals[2];
145*4882a593Smuzhiyun 	int ret;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	ret = regmap_field_read(afe->fields[afe440x_attr->field], &reg_val);
148*4882a593Smuzhiyun 	if (ret)
149*4882a593Smuzhiyun 		return ret;
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	if (reg_val >= afe440x_attr->table_size)
152*4882a593Smuzhiyun 		return -EINVAL;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	vals[0] = afe440x_attr->val_table[reg_val].integer;
155*4882a593Smuzhiyun 	vals[1] = afe440x_attr->val_table[reg_val].fract;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals);
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun 
afe440x_store_register(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)160*4882a593Smuzhiyun static ssize_t afe440x_store_register(struct device *dev,
161*4882a593Smuzhiyun 				      struct device_attribute *attr,
162*4882a593Smuzhiyun 				      const char *buf, size_t count)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
165*4882a593Smuzhiyun 	struct afe4403_data *afe = iio_priv(indio_dev);
166*4882a593Smuzhiyun 	struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
167*4882a593Smuzhiyun 	int val, integer, fract, ret;
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	ret = iio_str_to_fixpoint(buf, 100000, &integer, &fract);
170*4882a593Smuzhiyun 	if (ret)
171*4882a593Smuzhiyun 		return ret;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	for (val = 0; val < afe440x_attr->table_size; val++)
174*4882a593Smuzhiyun 		if (afe440x_attr->val_table[val].integer == integer &&
175*4882a593Smuzhiyun 		    afe440x_attr->val_table[val].fract == fract)
176*4882a593Smuzhiyun 			break;
177*4882a593Smuzhiyun 	if (val == afe440x_attr->table_size)
178*4882a593Smuzhiyun 		return -EINVAL;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	ret = regmap_field_write(afe->fields[afe440x_attr->field], val);
181*4882a593Smuzhiyun 	if (ret)
182*4882a593Smuzhiyun 		return ret;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	return count;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun static AFE440X_ATTR(in_intensity1_resistance, F_RF_LED, afe4403_res_table);
188*4882a593Smuzhiyun static AFE440X_ATTR(in_intensity1_capacitance, F_CF_LED, afe4403_cap_table);
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun static AFE440X_ATTR(in_intensity2_resistance, F_RF_LED, afe4403_res_table);
191*4882a593Smuzhiyun static AFE440X_ATTR(in_intensity2_capacitance, F_CF_LED, afe4403_cap_table);
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun static AFE440X_ATTR(in_intensity3_resistance, F_RF_LED1, afe4403_res_table);
194*4882a593Smuzhiyun static AFE440X_ATTR(in_intensity3_capacitance, F_CF_LED1, afe4403_cap_table);
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun static AFE440X_ATTR(in_intensity4_resistance, F_RF_LED1, afe4403_res_table);
197*4882a593Smuzhiyun static AFE440X_ATTR(in_intensity4_capacitance, F_CF_LED1, afe4403_cap_table);
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun static struct attribute *afe440x_attributes[] = {
200*4882a593Smuzhiyun 	&dev_attr_in_intensity_resistance_available.attr,
201*4882a593Smuzhiyun 	&dev_attr_in_intensity_capacitance_available.attr,
202*4882a593Smuzhiyun 	&afe440x_attr_in_intensity1_resistance.dev_attr.attr,
203*4882a593Smuzhiyun 	&afe440x_attr_in_intensity1_capacitance.dev_attr.attr,
204*4882a593Smuzhiyun 	&afe440x_attr_in_intensity2_resistance.dev_attr.attr,
205*4882a593Smuzhiyun 	&afe440x_attr_in_intensity2_capacitance.dev_attr.attr,
206*4882a593Smuzhiyun 	&afe440x_attr_in_intensity3_resistance.dev_attr.attr,
207*4882a593Smuzhiyun 	&afe440x_attr_in_intensity3_capacitance.dev_attr.attr,
208*4882a593Smuzhiyun 	&afe440x_attr_in_intensity4_resistance.dev_attr.attr,
209*4882a593Smuzhiyun 	&afe440x_attr_in_intensity4_capacitance.dev_attr.attr,
210*4882a593Smuzhiyun 	NULL
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun static const struct attribute_group afe440x_attribute_group = {
214*4882a593Smuzhiyun 	.attrs = afe440x_attributes
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun 
afe4403_read(struct afe4403_data * afe,unsigned int reg,u32 * val)217*4882a593Smuzhiyun static int afe4403_read(struct afe4403_data *afe, unsigned int reg, u32 *val)
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun 	u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ};
220*4882a593Smuzhiyun 	u8 rx[3];
221*4882a593Smuzhiyun 	int ret;
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	/* Enable reading from the device */
224*4882a593Smuzhiyun 	ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
225*4882a593Smuzhiyun 	if (ret)
226*4882a593Smuzhiyun 		return ret;
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	ret = spi_write_then_read(afe->spi, &reg, 1, rx, sizeof(rx));
229*4882a593Smuzhiyun 	if (ret)
230*4882a593Smuzhiyun 		return ret;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	*val = get_unaligned_be24(&rx[0]);
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	/* Disable reading from the device */
235*4882a593Smuzhiyun 	tx[3] = AFE440X_CONTROL0_WRITE;
236*4882a593Smuzhiyun 	ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
237*4882a593Smuzhiyun 	if (ret)
238*4882a593Smuzhiyun 		return ret;
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	return 0;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun 
afe4403_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)243*4882a593Smuzhiyun static int afe4403_read_raw(struct iio_dev *indio_dev,
244*4882a593Smuzhiyun 			    struct iio_chan_spec const *chan,
245*4882a593Smuzhiyun 			    int *val, int *val2, long mask)
246*4882a593Smuzhiyun {
247*4882a593Smuzhiyun 	struct afe4403_data *afe = iio_priv(indio_dev);
248*4882a593Smuzhiyun 	unsigned int reg, field;
249*4882a593Smuzhiyun 	int ret;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	switch (chan->type) {
252*4882a593Smuzhiyun 	case IIO_INTENSITY:
253*4882a593Smuzhiyun 		switch (mask) {
254*4882a593Smuzhiyun 		case IIO_CHAN_INFO_RAW:
255*4882a593Smuzhiyun 			reg = afe4403_channel_values[chan->address];
256*4882a593Smuzhiyun 			ret = afe4403_read(afe, reg, val);
257*4882a593Smuzhiyun 			if (ret)
258*4882a593Smuzhiyun 				return ret;
259*4882a593Smuzhiyun 			return IIO_VAL_INT;
260*4882a593Smuzhiyun 		}
261*4882a593Smuzhiyun 		break;
262*4882a593Smuzhiyun 	case IIO_CURRENT:
263*4882a593Smuzhiyun 		switch (mask) {
264*4882a593Smuzhiyun 		case IIO_CHAN_INFO_RAW:
265*4882a593Smuzhiyun 			field = afe4403_channel_leds[chan->address];
266*4882a593Smuzhiyun 			ret = regmap_field_read(afe->fields[field], val);
267*4882a593Smuzhiyun 			if (ret)
268*4882a593Smuzhiyun 				return ret;
269*4882a593Smuzhiyun 			return IIO_VAL_INT;
270*4882a593Smuzhiyun 		case IIO_CHAN_INFO_SCALE:
271*4882a593Smuzhiyun 			*val = 0;
272*4882a593Smuzhiyun 			*val2 = 800000;
273*4882a593Smuzhiyun 			return IIO_VAL_INT_PLUS_MICRO;
274*4882a593Smuzhiyun 		}
275*4882a593Smuzhiyun 		break;
276*4882a593Smuzhiyun 	default:
277*4882a593Smuzhiyun 		break;
278*4882a593Smuzhiyun 	}
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	return -EINVAL;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun 
afe4403_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)283*4882a593Smuzhiyun static int afe4403_write_raw(struct iio_dev *indio_dev,
284*4882a593Smuzhiyun 			     struct iio_chan_spec const *chan,
285*4882a593Smuzhiyun 			     int val, int val2, long mask)
286*4882a593Smuzhiyun {
287*4882a593Smuzhiyun 	struct afe4403_data *afe = iio_priv(indio_dev);
288*4882a593Smuzhiyun 	unsigned int field = afe4403_channel_leds[chan->address];
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 	switch (chan->type) {
291*4882a593Smuzhiyun 	case IIO_CURRENT:
292*4882a593Smuzhiyun 		switch (mask) {
293*4882a593Smuzhiyun 		case IIO_CHAN_INFO_RAW:
294*4882a593Smuzhiyun 			return regmap_field_write(afe->fields[field], val);
295*4882a593Smuzhiyun 		}
296*4882a593Smuzhiyun 		break;
297*4882a593Smuzhiyun 	default:
298*4882a593Smuzhiyun 		break;
299*4882a593Smuzhiyun 	}
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	return -EINVAL;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun static const struct iio_info afe4403_iio_info = {
305*4882a593Smuzhiyun 	.attrs = &afe440x_attribute_group,
306*4882a593Smuzhiyun 	.read_raw = afe4403_read_raw,
307*4882a593Smuzhiyun 	.write_raw = afe4403_write_raw,
308*4882a593Smuzhiyun };
309*4882a593Smuzhiyun 
afe4403_trigger_handler(int irq,void * private)310*4882a593Smuzhiyun static irqreturn_t afe4403_trigger_handler(int irq, void *private)
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun 	struct iio_poll_func *pf = private;
313*4882a593Smuzhiyun 	struct iio_dev *indio_dev = pf->indio_dev;
314*4882a593Smuzhiyun 	struct afe4403_data *afe = iio_priv(indio_dev);
315*4882a593Smuzhiyun 	int ret, bit, i = 0;
316*4882a593Smuzhiyun 	u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ};
317*4882a593Smuzhiyun 	u8 rx[3];
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun 	/* Enable reading from the device */
320*4882a593Smuzhiyun 	ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
321*4882a593Smuzhiyun 	if (ret)
322*4882a593Smuzhiyun 		goto err;
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	for_each_set_bit(bit, indio_dev->active_scan_mask,
325*4882a593Smuzhiyun 			 indio_dev->masklength) {
326*4882a593Smuzhiyun 		ret = spi_write_then_read(afe->spi,
327*4882a593Smuzhiyun 					  &afe4403_channel_values[bit], 1,
328*4882a593Smuzhiyun 					  rx, sizeof(rx));
329*4882a593Smuzhiyun 		if (ret)
330*4882a593Smuzhiyun 			goto err;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 		afe->buffer[i++] = get_unaligned_be24(&rx[0]);
333*4882a593Smuzhiyun 	}
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 	/* Disable reading from the device */
336*4882a593Smuzhiyun 	tx[3] = AFE440X_CONTROL0_WRITE;
337*4882a593Smuzhiyun 	ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
338*4882a593Smuzhiyun 	if (ret)
339*4882a593Smuzhiyun 		goto err;
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun 	iio_push_to_buffers_with_timestamp(indio_dev, afe->buffer,
342*4882a593Smuzhiyun 					   pf->timestamp);
343*4882a593Smuzhiyun err:
344*4882a593Smuzhiyun 	iio_trigger_notify_done(indio_dev->trig);
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	return IRQ_HANDLED;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun static const struct iio_trigger_ops afe4403_trigger_ops = {
350*4882a593Smuzhiyun };
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun #define AFE4403_TIMING_PAIRS			\
353*4882a593Smuzhiyun 	{ AFE440X_LED2STC,	0x000050 },	\
354*4882a593Smuzhiyun 	{ AFE440X_LED2ENDC,	0x0003e7 },	\
355*4882a593Smuzhiyun 	{ AFE440X_LED1LEDSTC,	0x0007d0 },	\
356*4882a593Smuzhiyun 	{ AFE440X_LED1LEDENDC,	0x000bb7 },	\
357*4882a593Smuzhiyun 	{ AFE440X_ALED2STC,	0x000438 },	\
358*4882a593Smuzhiyun 	{ AFE440X_ALED2ENDC,	0x0007cf },	\
359*4882a593Smuzhiyun 	{ AFE440X_LED1STC,	0x000820 },	\
360*4882a593Smuzhiyun 	{ AFE440X_LED1ENDC,	0x000bb7 },	\
361*4882a593Smuzhiyun 	{ AFE440X_LED2LEDSTC,	0x000000 },	\
362*4882a593Smuzhiyun 	{ AFE440X_LED2LEDENDC,	0x0003e7 },	\
363*4882a593Smuzhiyun 	{ AFE440X_ALED1STC,	0x000c08 },	\
364*4882a593Smuzhiyun 	{ AFE440X_ALED1ENDC,	0x000f9f },	\
365*4882a593Smuzhiyun 	{ AFE440X_LED2CONVST,	0x0003ef },	\
366*4882a593Smuzhiyun 	{ AFE440X_LED2CONVEND,	0x0007cf },	\
367*4882a593Smuzhiyun 	{ AFE440X_ALED2CONVST,	0x0007d7 },	\
368*4882a593Smuzhiyun 	{ AFE440X_ALED2CONVEND,	0x000bb7 },	\
369*4882a593Smuzhiyun 	{ AFE440X_LED1CONVST,	0x000bbf },	\
370*4882a593Smuzhiyun 	{ AFE440X_LED1CONVEND,	0x009c3f },	\
371*4882a593Smuzhiyun 	{ AFE440X_ALED1CONVST,	0x000fa7 },	\
372*4882a593Smuzhiyun 	{ AFE440X_ALED1CONVEND,	0x001387 },	\
373*4882a593Smuzhiyun 	{ AFE440X_ADCRSTSTCT0,	0x0003e8 },	\
374*4882a593Smuzhiyun 	{ AFE440X_ADCRSTENDCT0,	0x0003eb },	\
375*4882a593Smuzhiyun 	{ AFE440X_ADCRSTSTCT1,	0x0007d0 },	\
376*4882a593Smuzhiyun 	{ AFE440X_ADCRSTENDCT1,	0x0007d3 },	\
377*4882a593Smuzhiyun 	{ AFE440X_ADCRSTSTCT2,	0x000bb8 },	\
378*4882a593Smuzhiyun 	{ AFE440X_ADCRSTENDCT2,	0x000bbb },	\
379*4882a593Smuzhiyun 	{ AFE440X_ADCRSTSTCT3,	0x000fa0 },	\
380*4882a593Smuzhiyun 	{ AFE440X_ADCRSTENDCT3,	0x000fa3 },	\
381*4882a593Smuzhiyun 	{ AFE440X_PRPCOUNT,	0x009c3f },	\
382*4882a593Smuzhiyun 	{ AFE440X_PDNCYCLESTC,	0x001518 },	\
383*4882a593Smuzhiyun 	{ AFE440X_PDNCYCLEENDC,	0x00991f }
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun static const struct reg_sequence afe4403_reg_sequences[] = {
386*4882a593Smuzhiyun 	AFE4403_TIMING_PAIRS,
387*4882a593Smuzhiyun 	{ AFE440X_CONTROL1, AFE440X_CONTROL1_TIMEREN },
388*4882a593Smuzhiyun 	{ AFE4403_TIAGAIN, AFE440X_TIAGAIN_ENSEPGAIN },
389*4882a593Smuzhiyun };
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun static const struct regmap_range afe4403_yes_ranges[] = {
392*4882a593Smuzhiyun 	regmap_reg_range(AFE440X_LED2VAL, AFE440X_LED1_ALED1VAL),
393*4882a593Smuzhiyun };
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun static const struct regmap_access_table afe4403_volatile_table = {
396*4882a593Smuzhiyun 	.yes_ranges = afe4403_yes_ranges,
397*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(afe4403_yes_ranges),
398*4882a593Smuzhiyun };
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun static const struct regmap_config afe4403_regmap_config = {
401*4882a593Smuzhiyun 	.reg_bits = 8,
402*4882a593Smuzhiyun 	.val_bits = 24,
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	.max_register = AFE440X_PDNCYCLEENDC,
405*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
406*4882a593Smuzhiyun 	.volatile_table = &afe4403_volatile_table,
407*4882a593Smuzhiyun };
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun static const struct of_device_id afe4403_of_match[] = {
410*4882a593Smuzhiyun 	{ .compatible = "ti,afe4403", },
411*4882a593Smuzhiyun 	{ /* sentinel */ }
412*4882a593Smuzhiyun };
413*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, afe4403_of_match);
414*4882a593Smuzhiyun 
afe4403_suspend(struct device * dev)415*4882a593Smuzhiyun static int __maybe_unused afe4403_suspend(struct device *dev)
416*4882a593Smuzhiyun {
417*4882a593Smuzhiyun 	struct iio_dev *indio_dev = spi_get_drvdata(to_spi_device(dev));
418*4882a593Smuzhiyun 	struct afe4403_data *afe = iio_priv(indio_dev);
419*4882a593Smuzhiyun 	int ret;
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 	ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
422*4882a593Smuzhiyun 				 AFE440X_CONTROL2_PDN_AFE,
423*4882a593Smuzhiyun 				 AFE440X_CONTROL2_PDN_AFE);
424*4882a593Smuzhiyun 	if (ret)
425*4882a593Smuzhiyun 		return ret;
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 	ret = regulator_disable(afe->regulator);
428*4882a593Smuzhiyun 	if (ret) {
429*4882a593Smuzhiyun 		dev_err(dev, "Unable to disable regulator\n");
430*4882a593Smuzhiyun 		return ret;
431*4882a593Smuzhiyun 	}
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	return 0;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun 
afe4403_resume(struct device * dev)436*4882a593Smuzhiyun static int __maybe_unused afe4403_resume(struct device *dev)
437*4882a593Smuzhiyun {
438*4882a593Smuzhiyun 	struct iio_dev *indio_dev = spi_get_drvdata(to_spi_device(dev));
439*4882a593Smuzhiyun 	struct afe4403_data *afe = iio_priv(indio_dev);
440*4882a593Smuzhiyun 	int ret;
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun 	ret = regulator_enable(afe->regulator);
443*4882a593Smuzhiyun 	if (ret) {
444*4882a593Smuzhiyun 		dev_err(dev, "Unable to enable regulator\n");
445*4882a593Smuzhiyun 		return ret;
446*4882a593Smuzhiyun 	}
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun 	ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
449*4882a593Smuzhiyun 				 AFE440X_CONTROL2_PDN_AFE, 0);
450*4882a593Smuzhiyun 	if (ret)
451*4882a593Smuzhiyun 		return ret;
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun 	return 0;
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(afe4403_pm_ops, afe4403_suspend, afe4403_resume);
457*4882a593Smuzhiyun 
afe4403_probe(struct spi_device * spi)458*4882a593Smuzhiyun static int afe4403_probe(struct spi_device *spi)
459*4882a593Smuzhiyun {
460*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
461*4882a593Smuzhiyun 	struct afe4403_data *afe;
462*4882a593Smuzhiyun 	int i, ret;
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*afe));
465*4882a593Smuzhiyun 	if (!indio_dev)
466*4882a593Smuzhiyun 		return -ENOMEM;
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 	afe = iio_priv(indio_dev);
469*4882a593Smuzhiyun 	spi_set_drvdata(spi, indio_dev);
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	afe->dev = &spi->dev;
472*4882a593Smuzhiyun 	afe->spi = spi;
473*4882a593Smuzhiyun 	afe->irq = spi->irq;
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun 	afe->regmap = devm_regmap_init_spi(spi, &afe4403_regmap_config);
476*4882a593Smuzhiyun 	if (IS_ERR(afe->regmap)) {
477*4882a593Smuzhiyun 		dev_err(afe->dev, "Unable to allocate register map\n");
478*4882a593Smuzhiyun 		return PTR_ERR(afe->regmap);
479*4882a593Smuzhiyun 	}
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	for (i = 0; i < F_MAX_FIELDS; i++) {
482*4882a593Smuzhiyun 		afe->fields[i] = devm_regmap_field_alloc(afe->dev, afe->regmap,
483*4882a593Smuzhiyun 							 afe4403_reg_fields[i]);
484*4882a593Smuzhiyun 		if (IS_ERR(afe->fields[i])) {
485*4882a593Smuzhiyun 			dev_err(afe->dev, "Unable to allocate regmap fields\n");
486*4882a593Smuzhiyun 			return PTR_ERR(afe->fields[i]);
487*4882a593Smuzhiyun 		}
488*4882a593Smuzhiyun 	}
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	afe->regulator = devm_regulator_get(afe->dev, "tx_sup");
491*4882a593Smuzhiyun 	if (IS_ERR(afe->regulator)) {
492*4882a593Smuzhiyun 		dev_err(afe->dev, "Unable to get regulator\n");
493*4882a593Smuzhiyun 		return PTR_ERR(afe->regulator);
494*4882a593Smuzhiyun 	}
495*4882a593Smuzhiyun 	ret = regulator_enable(afe->regulator);
496*4882a593Smuzhiyun 	if (ret) {
497*4882a593Smuzhiyun 		dev_err(afe->dev, "Unable to enable regulator\n");
498*4882a593Smuzhiyun 		return ret;
499*4882a593Smuzhiyun 	}
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun 	ret = regmap_write(afe->regmap, AFE440X_CONTROL0,
502*4882a593Smuzhiyun 			   AFE440X_CONTROL0_SW_RESET);
503*4882a593Smuzhiyun 	if (ret) {
504*4882a593Smuzhiyun 		dev_err(afe->dev, "Unable to reset device\n");
505*4882a593Smuzhiyun 		goto err_disable_reg;
506*4882a593Smuzhiyun 	}
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	ret = regmap_multi_reg_write(afe->regmap, afe4403_reg_sequences,
509*4882a593Smuzhiyun 				     ARRAY_SIZE(afe4403_reg_sequences));
510*4882a593Smuzhiyun 	if (ret) {
511*4882a593Smuzhiyun 		dev_err(afe->dev, "Unable to set register defaults\n");
512*4882a593Smuzhiyun 		goto err_disable_reg;
513*4882a593Smuzhiyun 	}
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
516*4882a593Smuzhiyun 	indio_dev->channels = afe4403_channels;
517*4882a593Smuzhiyun 	indio_dev->num_channels = ARRAY_SIZE(afe4403_channels);
518*4882a593Smuzhiyun 	indio_dev->name = AFE4403_DRIVER_NAME;
519*4882a593Smuzhiyun 	indio_dev->info = &afe4403_iio_info;
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun 	if (afe->irq > 0) {
522*4882a593Smuzhiyun 		afe->trig = devm_iio_trigger_alloc(afe->dev,
523*4882a593Smuzhiyun 						   "%s-dev%d",
524*4882a593Smuzhiyun 						   indio_dev->name,
525*4882a593Smuzhiyun 						   indio_dev->id);
526*4882a593Smuzhiyun 		if (!afe->trig) {
527*4882a593Smuzhiyun 			dev_err(afe->dev, "Unable to allocate IIO trigger\n");
528*4882a593Smuzhiyun 			ret = -ENOMEM;
529*4882a593Smuzhiyun 			goto err_disable_reg;
530*4882a593Smuzhiyun 		}
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 		iio_trigger_set_drvdata(afe->trig, indio_dev);
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 		afe->trig->ops = &afe4403_trigger_ops;
535*4882a593Smuzhiyun 		afe->trig->dev.parent = afe->dev;
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 		ret = iio_trigger_register(afe->trig);
538*4882a593Smuzhiyun 		if (ret) {
539*4882a593Smuzhiyun 			dev_err(afe->dev, "Unable to register IIO trigger\n");
540*4882a593Smuzhiyun 			goto err_disable_reg;
541*4882a593Smuzhiyun 		}
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun 		ret = devm_request_threaded_irq(afe->dev, afe->irq,
544*4882a593Smuzhiyun 						iio_trigger_generic_data_rdy_poll,
545*4882a593Smuzhiyun 						NULL, IRQF_ONESHOT,
546*4882a593Smuzhiyun 						AFE4403_DRIVER_NAME,
547*4882a593Smuzhiyun 						afe->trig);
548*4882a593Smuzhiyun 		if (ret) {
549*4882a593Smuzhiyun 			dev_err(afe->dev, "Unable to request IRQ\n");
550*4882a593Smuzhiyun 			goto err_trig;
551*4882a593Smuzhiyun 		}
552*4882a593Smuzhiyun 	}
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun 	ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
555*4882a593Smuzhiyun 					 afe4403_trigger_handler, NULL);
556*4882a593Smuzhiyun 	if (ret) {
557*4882a593Smuzhiyun 		dev_err(afe->dev, "Unable to setup buffer\n");
558*4882a593Smuzhiyun 		goto err_trig;
559*4882a593Smuzhiyun 	}
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun 	ret = iio_device_register(indio_dev);
562*4882a593Smuzhiyun 	if (ret) {
563*4882a593Smuzhiyun 		dev_err(afe->dev, "Unable to register IIO device\n");
564*4882a593Smuzhiyun 		goto err_buff;
565*4882a593Smuzhiyun 	}
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 	return 0;
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun err_buff:
570*4882a593Smuzhiyun 	iio_triggered_buffer_cleanup(indio_dev);
571*4882a593Smuzhiyun err_trig:
572*4882a593Smuzhiyun 	if (afe->irq > 0)
573*4882a593Smuzhiyun 		iio_trigger_unregister(afe->trig);
574*4882a593Smuzhiyun err_disable_reg:
575*4882a593Smuzhiyun 	regulator_disable(afe->regulator);
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun 	return ret;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun 
afe4403_remove(struct spi_device * spi)580*4882a593Smuzhiyun static int afe4403_remove(struct spi_device *spi)
581*4882a593Smuzhiyun {
582*4882a593Smuzhiyun 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
583*4882a593Smuzhiyun 	struct afe4403_data *afe = iio_priv(indio_dev);
584*4882a593Smuzhiyun 	int ret;
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun 	iio_device_unregister(indio_dev);
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun 	iio_triggered_buffer_cleanup(indio_dev);
589*4882a593Smuzhiyun 
590*4882a593Smuzhiyun 	if (afe->irq > 0)
591*4882a593Smuzhiyun 		iio_trigger_unregister(afe->trig);
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun 	ret = regulator_disable(afe->regulator);
594*4882a593Smuzhiyun 	if (ret) {
595*4882a593Smuzhiyun 		dev_err(afe->dev, "Unable to disable regulator\n");
596*4882a593Smuzhiyun 		return ret;
597*4882a593Smuzhiyun 	}
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun 	return 0;
600*4882a593Smuzhiyun }
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun static const struct spi_device_id afe4403_ids[] = {
603*4882a593Smuzhiyun 	{ "afe4403", 0 },
604*4882a593Smuzhiyun 	{ /* sentinel */ }
605*4882a593Smuzhiyun };
606*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, afe4403_ids);
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun static struct spi_driver afe4403_spi_driver = {
609*4882a593Smuzhiyun 	.driver = {
610*4882a593Smuzhiyun 		.name = AFE4403_DRIVER_NAME,
611*4882a593Smuzhiyun 		.of_match_table = afe4403_of_match,
612*4882a593Smuzhiyun 		.pm = &afe4403_pm_ops,
613*4882a593Smuzhiyun 	},
614*4882a593Smuzhiyun 	.probe = afe4403_probe,
615*4882a593Smuzhiyun 	.remove = afe4403_remove,
616*4882a593Smuzhiyun 	.id_table = afe4403_ids,
617*4882a593Smuzhiyun };
618*4882a593Smuzhiyun module_spi_driver(afe4403_spi_driver);
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
621*4882a593Smuzhiyun MODULE_DESCRIPTION("TI AFE4403 Heart Rate Monitor and Pulse Oximeter AFE");
622*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
623