1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Driver for NXP FXAS21002C Gyroscope - Header 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2019 Linaro Ltd. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef FXAS21002C_H_ 9*4882a593Smuzhiyun #define FXAS21002C_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/regmap.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define FXAS21002C_REG_STATUS 0x00 14*4882a593Smuzhiyun #define FXAS21002C_REG_OUT_X_MSB 0x01 15*4882a593Smuzhiyun #define FXAS21002C_REG_OUT_X_LSB 0x02 16*4882a593Smuzhiyun #define FXAS21002C_REG_OUT_Y_MSB 0x03 17*4882a593Smuzhiyun #define FXAS21002C_REG_OUT_Y_LSB 0x04 18*4882a593Smuzhiyun #define FXAS21002C_REG_OUT_Z_MSB 0x05 19*4882a593Smuzhiyun #define FXAS21002C_REG_OUT_Z_LSB 0x06 20*4882a593Smuzhiyun #define FXAS21002C_REG_DR_STATUS 0x07 21*4882a593Smuzhiyun #define FXAS21002C_REG_F_STATUS 0x08 22*4882a593Smuzhiyun #define FXAS21002C_REG_F_SETUP 0x09 23*4882a593Smuzhiyun #define FXAS21002C_REG_F_EVENT 0x0A 24*4882a593Smuzhiyun #define FXAS21002C_REG_INT_SRC_FLAG 0x0B 25*4882a593Smuzhiyun #define FXAS21002C_REG_WHO_AM_I 0x0C 26*4882a593Smuzhiyun #define FXAS21002C_REG_CTRL0 0x0D 27*4882a593Smuzhiyun #define FXAS21002C_REG_RT_CFG 0x0E 28*4882a593Smuzhiyun #define FXAS21002C_REG_RT_SRC 0x0F 29*4882a593Smuzhiyun #define FXAS21002C_REG_RT_THS 0x10 30*4882a593Smuzhiyun #define FXAS21002C_REG_RT_COUNT 0x11 31*4882a593Smuzhiyun #define FXAS21002C_REG_TEMP 0x12 32*4882a593Smuzhiyun #define FXAS21002C_REG_CTRL1 0x13 33*4882a593Smuzhiyun #define FXAS21002C_REG_CTRL2 0x14 34*4882a593Smuzhiyun #define FXAS21002C_REG_CTRL3 0x15 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun enum fxas21002c_fields { 37*4882a593Smuzhiyun F_DR_STATUS, 38*4882a593Smuzhiyun F_OUT_X_MSB, 39*4882a593Smuzhiyun F_OUT_X_LSB, 40*4882a593Smuzhiyun F_OUT_Y_MSB, 41*4882a593Smuzhiyun F_OUT_Y_LSB, 42*4882a593Smuzhiyun F_OUT_Z_MSB, 43*4882a593Smuzhiyun F_OUT_Z_LSB, 44*4882a593Smuzhiyun /* DR_STATUS */ 45*4882a593Smuzhiyun F_ZYX_OW, F_Z_OW, F_Y_OW, F_X_OW, F_ZYX_DR, F_Z_DR, F_Y_DR, F_X_DR, 46*4882a593Smuzhiyun /* F_STATUS */ 47*4882a593Smuzhiyun F_OVF, F_WMKF, F_CNT, 48*4882a593Smuzhiyun /* F_SETUP */ 49*4882a593Smuzhiyun F_MODE, F_WMRK, 50*4882a593Smuzhiyun /* F_EVENT */ 51*4882a593Smuzhiyun F_EVENT, FE_TIME, 52*4882a593Smuzhiyun /* INT_SOURCE_FLAG */ 53*4882a593Smuzhiyun F_BOOTEND, F_SRC_FIFO, F_SRC_RT, F_SRC_DRDY, 54*4882a593Smuzhiyun /* WHO_AM_I */ 55*4882a593Smuzhiyun F_WHO_AM_I, 56*4882a593Smuzhiyun /* CTRL_REG0 */ 57*4882a593Smuzhiyun F_BW, F_SPIW, F_SEL, F_HPF_EN, F_FS, 58*4882a593Smuzhiyun /* RT_CFG */ 59*4882a593Smuzhiyun F_ELE, F_ZTEFE, F_YTEFE, F_XTEFE, 60*4882a593Smuzhiyun /* RT_SRC */ 61*4882a593Smuzhiyun F_EA, F_ZRT, F_ZRT_POL, F_YRT, F_YRT_POL, F_XRT, F_XRT_POL, 62*4882a593Smuzhiyun /* RT_THS */ 63*4882a593Smuzhiyun F_DBCNTM, F_THS, 64*4882a593Smuzhiyun /* RT_COUNT */ 65*4882a593Smuzhiyun F_RT_COUNT, 66*4882a593Smuzhiyun /* TEMP */ 67*4882a593Smuzhiyun F_TEMP, 68*4882a593Smuzhiyun /* CTRL_REG1 */ 69*4882a593Smuzhiyun F_RST, F_ST, F_DR, F_ACTIVE, F_READY, 70*4882a593Smuzhiyun /* CTRL_REG2 */ 71*4882a593Smuzhiyun F_INT_CFG_FIFO, F_INT_EN_FIFO, F_INT_CFG_RT, F_INT_EN_RT, 72*4882a593Smuzhiyun F_INT_CFG_DRDY, F_INT_EN_DRDY, F_IPOL, F_PP_OD, 73*4882a593Smuzhiyun /* CTRL_REG3 */ 74*4882a593Smuzhiyun F_WRAPTOONE, F_EXTCTRLEN, F_FS_DOUBLE, 75*4882a593Smuzhiyun /* MAX FIELDS */ 76*4882a593Smuzhiyun F_MAX_FIELDS, 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun extern const struct dev_pm_ops fxas21002c_pm_ops; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun int fxas21002c_core_probe(struct device *dev, struct regmap *regmap, int irq, 82*4882a593Smuzhiyun const char *name); 83*4882a593Smuzhiyun void fxas21002c_core_remove(struct device *dev); 84*4882a593Smuzhiyun #endif 85