1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * mcp4922.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Driver for Microchip Digital to Analog Converters.
6*4882a593Smuzhiyun * Supports MCP4902, MCP4912, and MCP4922.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Copyright (c) 2014 EMAC Inc.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/spi/spi.h>
14*4882a593Smuzhiyun #include <linux/iio/iio.h>
15*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
16*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
17*4882a593Smuzhiyun #include <linux/bitops.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define MCP4922_NUM_CHANNELS 2
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun enum mcp4922_supported_device_ids {
22*4882a593Smuzhiyun ID_MCP4902,
23*4882a593Smuzhiyun ID_MCP4912,
24*4882a593Smuzhiyun ID_MCP4922,
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct mcp4922_state {
28*4882a593Smuzhiyun struct spi_device *spi;
29*4882a593Smuzhiyun unsigned int value[MCP4922_NUM_CHANNELS];
30*4882a593Smuzhiyun unsigned int vref_mv;
31*4882a593Smuzhiyun struct regulator *vref_reg;
32*4882a593Smuzhiyun u8 mosi[2] ____cacheline_aligned;
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define MCP4922_CHAN(chan, bits) { \
36*4882a593Smuzhiyun .type = IIO_VOLTAGE, \
37*4882a593Smuzhiyun .output = 1, \
38*4882a593Smuzhiyun .indexed = 1, \
39*4882a593Smuzhiyun .channel = chan, \
40*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
41*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
42*4882a593Smuzhiyun .scan_type = { \
43*4882a593Smuzhiyun .sign = 'u', \
44*4882a593Smuzhiyun .realbits = (bits), \
45*4882a593Smuzhiyun .storagebits = 16, \
46*4882a593Smuzhiyun .shift = 12 - (bits), \
47*4882a593Smuzhiyun }, \
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
mcp4922_spi_write(struct mcp4922_state * state,u8 addr,u32 val)50*4882a593Smuzhiyun static int mcp4922_spi_write(struct mcp4922_state *state, u8 addr, u32 val)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun state->mosi[1] = val & 0xff;
53*4882a593Smuzhiyun state->mosi[0] = (addr == 0) ? 0x00 : 0x80;
54*4882a593Smuzhiyun state->mosi[0] |= 0x30 | ((val >> 8) & 0x0f);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return spi_write(state->spi, state->mosi, 2);
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
mcp4922_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)59*4882a593Smuzhiyun static int mcp4922_read_raw(struct iio_dev *indio_dev,
60*4882a593Smuzhiyun struct iio_chan_spec const *chan,
61*4882a593Smuzhiyun int *val,
62*4882a593Smuzhiyun int *val2,
63*4882a593Smuzhiyun long mask)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun struct mcp4922_state *state = iio_priv(indio_dev);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun switch (mask) {
68*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
69*4882a593Smuzhiyun *val = state->value[chan->channel];
70*4882a593Smuzhiyun return IIO_VAL_INT;
71*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
72*4882a593Smuzhiyun *val = state->vref_mv;
73*4882a593Smuzhiyun *val2 = chan->scan_type.realbits;
74*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL_LOG2;
75*4882a593Smuzhiyun default:
76*4882a593Smuzhiyun return -EINVAL;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
mcp4922_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)80*4882a593Smuzhiyun static int mcp4922_write_raw(struct iio_dev *indio_dev,
81*4882a593Smuzhiyun struct iio_chan_spec const *chan,
82*4882a593Smuzhiyun int val,
83*4882a593Smuzhiyun int val2,
84*4882a593Smuzhiyun long mask)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun struct mcp4922_state *state = iio_priv(indio_dev);
87*4882a593Smuzhiyun int ret;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun if (val2 != 0)
90*4882a593Smuzhiyun return -EINVAL;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun switch (mask) {
93*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
94*4882a593Smuzhiyun if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0))
95*4882a593Smuzhiyun return -EINVAL;
96*4882a593Smuzhiyun val <<= chan->scan_type.shift;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun ret = mcp4922_spi_write(state, chan->channel, val);
99*4882a593Smuzhiyun if (!ret)
100*4882a593Smuzhiyun state->value[chan->channel] = val;
101*4882a593Smuzhiyun return ret;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun default:
104*4882a593Smuzhiyun return -EINVAL;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun static const struct iio_chan_spec mcp4922_channels[3][MCP4922_NUM_CHANNELS] = {
109*4882a593Smuzhiyun [ID_MCP4902] = { MCP4922_CHAN(0, 8), MCP4922_CHAN(1, 8) },
110*4882a593Smuzhiyun [ID_MCP4912] = { MCP4922_CHAN(0, 10), MCP4922_CHAN(1, 10) },
111*4882a593Smuzhiyun [ID_MCP4922] = { MCP4922_CHAN(0, 12), MCP4922_CHAN(1, 12) },
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun static const struct iio_info mcp4922_info = {
115*4882a593Smuzhiyun .read_raw = &mcp4922_read_raw,
116*4882a593Smuzhiyun .write_raw = &mcp4922_write_raw,
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun
mcp4922_probe(struct spi_device * spi)119*4882a593Smuzhiyun static int mcp4922_probe(struct spi_device *spi)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun struct iio_dev *indio_dev;
122*4882a593Smuzhiyun struct mcp4922_state *state;
123*4882a593Smuzhiyun const struct spi_device_id *id;
124*4882a593Smuzhiyun int ret;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*state));
127*4882a593Smuzhiyun if (indio_dev == NULL)
128*4882a593Smuzhiyun return -ENOMEM;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun state = iio_priv(indio_dev);
131*4882a593Smuzhiyun state->spi = spi;
132*4882a593Smuzhiyun state->vref_reg = devm_regulator_get(&spi->dev, "vref");
133*4882a593Smuzhiyun if (IS_ERR(state->vref_reg)) {
134*4882a593Smuzhiyun dev_err(&spi->dev, "Vref regulator not specified\n");
135*4882a593Smuzhiyun return PTR_ERR(state->vref_reg);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun ret = regulator_enable(state->vref_reg);
139*4882a593Smuzhiyun if (ret) {
140*4882a593Smuzhiyun dev_err(&spi->dev, "Failed to enable vref regulator: %d\n",
141*4882a593Smuzhiyun ret);
142*4882a593Smuzhiyun return ret;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun ret = regulator_get_voltage(state->vref_reg);
146*4882a593Smuzhiyun if (ret < 0) {
147*4882a593Smuzhiyun dev_err(&spi->dev, "Failed to read vref regulator: %d\n",
148*4882a593Smuzhiyun ret);
149*4882a593Smuzhiyun goto error_disable_reg;
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun state->vref_mv = ret / 1000;
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun spi_set_drvdata(spi, indio_dev);
154*4882a593Smuzhiyun id = spi_get_device_id(spi);
155*4882a593Smuzhiyun indio_dev->info = &mcp4922_info;
156*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
157*4882a593Smuzhiyun indio_dev->channels = mcp4922_channels[id->driver_data];
158*4882a593Smuzhiyun indio_dev->num_channels = MCP4922_NUM_CHANNELS;
159*4882a593Smuzhiyun indio_dev->name = id->name;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
162*4882a593Smuzhiyun if (ret) {
163*4882a593Smuzhiyun dev_err(&spi->dev, "Failed to register iio device: %d\n",
164*4882a593Smuzhiyun ret);
165*4882a593Smuzhiyun goto error_disable_reg;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun return 0;
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun error_disable_reg:
171*4882a593Smuzhiyun regulator_disable(state->vref_reg);
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun return ret;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
mcp4922_remove(struct spi_device * spi)176*4882a593Smuzhiyun static int mcp4922_remove(struct spi_device *spi)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun struct iio_dev *indio_dev = spi_get_drvdata(spi);
179*4882a593Smuzhiyun struct mcp4922_state *state;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun iio_device_unregister(indio_dev);
182*4882a593Smuzhiyun state = iio_priv(indio_dev);
183*4882a593Smuzhiyun regulator_disable(state->vref_reg);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun return 0;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun static const struct spi_device_id mcp4922_id[] = {
189*4882a593Smuzhiyun {"mcp4902", ID_MCP4902},
190*4882a593Smuzhiyun {"mcp4912", ID_MCP4912},
191*4882a593Smuzhiyun {"mcp4922", ID_MCP4922},
192*4882a593Smuzhiyun {}
193*4882a593Smuzhiyun };
194*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, mcp4922_id);
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun static struct spi_driver mcp4922_driver = {
197*4882a593Smuzhiyun .driver = {
198*4882a593Smuzhiyun .name = "mcp4922",
199*4882a593Smuzhiyun },
200*4882a593Smuzhiyun .probe = mcp4922_probe,
201*4882a593Smuzhiyun .remove = mcp4922_remove,
202*4882a593Smuzhiyun .id_table = mcp4922_id,
203*4882a593Smuzhiyun };
204*4882a593Smuzhiyun module_spi_driver(mcp4922_driver);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun MODULE_AUTHOR("Michael Welling <mwelling@ieee.org>");
207*4882a593Smuzhiyun MODULE_DESCRIPTION("Microchip MCP4902, MCP4912, MCP4922 DAC");
208*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
209