xref: /OK3568_Linux_fs/kernel/drivers/iio/dac/ltc2632.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * LTC2632 Digital to analog convertors spi driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2017 Maxime Roussin-Bélanger
6*4882a593Smuzhiyun  * expanded by Silvan Murer <silvan.murer@gmail.com>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/spi/spi.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/iio/iio.h>
13*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <asm/unaligned.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define LTC2632_CMD_WRITE_INPUT_N               0x0
18*4882a593Smuzhiyun #define LTC2632_CMD_UPDATE_DAC_N                0x1
19*4882a593Smuzhiyun #define LTC2632_CMD_WRITE_INPUT_N_UPDATE_ALL    0x2
20*4882a593Smuzhiyun #define LTC2632_CMD_WRITE_INPUT_N_UPDATE_N      0x3
21*4882a593Smuzhiyun #define LTC2632_CMD_POWERDOWN_DAC_N             0x4
22*4882a593Smuzhiyun #define LTC2632_CMD_POWERDOWN_CHIP              0x5
23*4882a593Smuzhiyun #define LTC2632_CMD_INTERNAL_REFER              0x6
24*4882a593Smuzhiyun #define LTC2632_CMD_EXTERNAL_REFER              0x7
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun /**
27*4882a593Smuzhiyun  * struct ltc2632_chip_info - chip specific information
28*4882a593Smuzhiyun  * @channels:		channel spec for the DAC
29*4882a593Smuzhiyun  * @num_channels:	DAC channel count of the chip
30*4882a593Smuzhiyun  * @vref_mv:		internal reference voltage
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun struct ltc2632_chip_info {
33*4882a593Smuzhiyun 	const struct iio_chan_spec *channels;
34*4882a593Smuzhiyun 	const size_t num_channels;
35*4882a593Smuzhiyun 	const int vref_mv;
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /**
39*4882a593Smuzhiyun  * struct ltc2632_state - driver instance specific data
40*4882a593Smuzhiyun  * @spi_dev:			pointer to the spi_device struct
41*4882a593Smuzhiyun  * @powerdown_cache_mask:	used to show current channel powerdown state
42*4882a593Smuzhiyun  * @vref_mv:			used reference voltage (internal or external)
43*4882a593Smuzhiyun  * @vref_reg:		regulator for the reference voltage
44*4882a593Smuzhiyun  */
45*4882a593Smuzhiyun struct ltc2632_state {
46*4882a593Smuzhiyun 	struct spi_device *spi_dev;
47*4882a593Smuzhiyun 	unsigned int powerdown_cache_mask;
48*4882a593Smuzhiyun 	int vref_mv;
49*4882a593Smuzhiyun 	struct regulator *vref_reg;
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun enum ltc2632_supported_device_ids {
53*4882a593Smuzhiyun 	ID_LTC2632L12,
54*4882a593Smuzhiyun 	ID_LTC2632L10,
55*4882a593Smuzhiyun 	ID_LTC2632L8,
56*4882a593Smuzhiyun 	ID_LTC2632H12,
57*4882a593Smuzhiyun 	ID_LTC2632H10,
58*4882a593Smuzhiyun 	ID_LTC2632H8,
59*4882a593Smuzhiyun 	ID_LTC2634L12,
60*4882a593Smuzhiyun 	ID_LTC2634L10,
61*4882a593Smuzhiyun 	ID_LTC2634L8,
62*4882a593Smuzhiyun 	ID_LTC2634H12,
63*4882a593Smuzhiyun 	ID_LTC2634H10,
64*4882a593Smuzhiyun 	ID_LTC2634H8,
65*4882a593Smuzhiyun 	ID_LTC2636L12,
66*4882a593Smuzhiyun 	ID_LTC2636L10,
67*4882a593Smuzhiyun 	ID_LTC2636L8,
68*4882a593Smuzhiyun 	ID_LTC2636H12,
69*4882a593Smuzhiyun 	ID_LTC2636H10,
70*4882a593Smuzhiyun 	ID_LTC2636H8,
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun 
ltc2632_spi_write(struct spi_device * spi,u8 cmd,u8 addr,u16 val,u8 shift)73*4882a593Smuzhiyun static int ltc2632_spi_write(struct spi_device *spi,
74*4882a593Smuzhiyun 			     u8 cmd, u8 addr, u16 val, u8 shift)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	u32 data;
77*4882a593Smuzhiyun 	u8 msg[3];
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	/*
80*4882a593Smuzhiyun 	 * The input shift register is 24 bits wide.
81*4882a593Smuzhiyun 	 * The next four are the command bits, C3 to C0,
82*4882a593Smuzhiyun 	 * followed by the 4-bit DAC address, A3 to A0, and then the
83*4882a593Smuzhiyun 	 * 12-, 10-, 8-bit data-word. The data-word comprises the 12-,
84*4882a593Smuzhiyun 	 * 10-, 8-bit input code followed by 4, 6, or 8 don't care bits.
85*4882a593Smuzhiyun 	 */
86*4882a593Smuzhiyun 	data = (cmd << 20) | (addr << 16) | (val << shift);
87*4882a593Smuzhiyun 	put_unaligned_be24(data, &msg[0]);
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	return spi_write(spi, msg, sizeof(msg));
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun 
ltc2632_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)92*4882a593Smuzhiyun static int ltc2632_read_raw(struct iio_dev *indio_dev,
93*4882a593Smuzhiyun 			    struct iio_chan_spec const *chan,
94*4882a593Smuzhiyun 			    int *val,
95*4882a593Smuzhiyun 			    int *val2,
96*4882a593Smuzhiyun 			    long m)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun 	const struct ltc2632_state *st = iio_priv(indio_dev);
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	switch (m) {
101*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
102*4882a593Smuzhiyun 		*val = st->vref_mv;
103*4882a593Smuzhiyun 		*val2 = chan->scan_type.realbits;
104*4882a593Smuzhiyun 		return IIO_VAL_FRACTIONAL_LOG2;
105*4882a593Smuzhiyun 	}
106*4882a593Smuzhiyun 	return -EINVAL;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun 
ltc2632_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)109*4882a593Smuzhiyun static int ltc2632_write_raw(struct iio_dev *indio_dev,
110*4882a593Smuzhiyun 			     struct iio_chan_spec const *chan,
111*4882a593Smuzhiyun 			     int val,
112*4882a593Smuzhiyun 			     int val2,
113*4882a593Smuzhiyun 			     long mask)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun 	struct ltc2632_state *st = iio_priv(indio_dev);
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	switch (mask) {
118*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
119*4882a593Smuzhiyun 		if (val >= (1 << chan->scan_type.realbits) || val < 0)
120*4882a593Smuzhiyun 			return -EINVAL;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 		return ltc2632_spi_write(st->spi_dev,
123*4882a593Smuzhiyun 					 LTC2632_CMD_WRITE_INPUT_N_UPDATE_N,
124*4882a593Smuzhiyun 					 chan->address, val,
125*4882a593Smuzhiyun 					 chan->scan_type.shift);
126*4882a593Smuzhiyun 	default:
127*4882a593Smuzhiyun 		return -EINVAL;
128*4882a593Smuzhiyun 	}
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun 
ltc2632_read_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)131*4882a593Smuzhiyun static ssize_t ltc2632_read_dac_powerdown(struct iio_dev *indio_dev,
132*4882a593Smuzhiyun 					  uintptr_t private,
133*4882a593Smuzhiyun 					  const struct iio_chan_spec *chan,
134*4882a593Smuzhiyun 					  char *buf)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun 	struct ltc2632_state *st = iio_priv(indio_dev);
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	return sprintf(buf, "%d\n",
139*4882a593Smuzhiyun 		       !!(st->powerdown_cache_mask & (1 << chan->channel)));
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
ltc2632_write_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)142*4882a593Smuzhiyun static ssize_t ltc2632_write_dac_powerdown(struct iio_dev *indio_dev,
143*4882a593Smuzhiyun 					   uintptr_t private,
144*4882a593Smuzhiyun 					   const struct iio_chan_spec *chan,
145*4882a593Smuzhiyun 					   const char *buf,
146*4882a593Smuzhiyun 					   size_t len)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun 	bool pwr_down;
149*4882a593Smuzhiyun 	int ret;
150*4882a593Smuzhiyun 	struct ltc2632_state *st = iio_priv(indio_dev);
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	ret = strtobool(buf, &pwr_down);
153*4882a593Smuzhiyun 	if (ret)
154*4882a593Smuzhiyun 		return ret;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	if (pwr_down)
157*4882a593Smuzhiyun 		st->powerdown_cache_mask |= (1 << chan->channel);
158*4882a593Smuzhiyun 	else
159*4882a593Smuzhiyun 		st->powerdown_cache_mask &= ~(1 << chan->channel);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	ret = ltc2632_spi_write(st->spi_dev,
162*4882a593Smuzhiyun 				LTC2632_CMD_POWERDOWN_DAC_N,
163*4882a593Smuzhiyun 				chan->channel, 0, 0);
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	return ret ? ret : len;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun static const struct iio_info ltc2632_info = {
169*4882a593Smuzhiyun 	.write_raw	= ltc2632_write_raw,
170*4882a593Smuzhiyun 	.read_raw	= ltc2632_read_raw,
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun static const struct iio_chan_spec_ext_info ltc2632_ext_info[] = {
174*4882a593Smuzhiyun 	{
175*4882a593Smuzhiyun 		.name = "powerdown",
176*4882a593Smuzhiyun 		.read = ltc2632_read_dac_powerdown,
177*4882a593Smuzhiyun 		.write = ltc2632_write_dac_powerdown,
178*4882a593Smuzhiyun 		.shared = IIO_SEPARATE,
179*4882a593Smuzhiyun 	},
180*4882a593Smuzhiyun 	{ },
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun #define LTC2632_CHANNEL(_chan, _bits) { \
184*4882a593Smuzhiyun 		.type = IIO_VOLTAGE, \
185*4882a593Smuzhiyun 		.indexed = 1, \
186*4882a593Smuzhiyun 		.output = 1, \
187*4882a593Smuzhiyun 		.channel = (_chan), \
188*4882a593Smuzhiyun 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
189*4882a593Smuzhiyun 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
190*4882a593Smuzhiyun 		.address = (_chan), \
191*4882a593Smuzhiyun 		.scan_type = { \
192*4882a593Smuzhiyun 			.realbits	= (_bits), \
193*4882a593Smuzhiyun 			.shift		= 16 - (_bits), \
194*4882a593Smuzhiyun 		}, \
195*4882a593Smuzhiyun 		.ext_info = ltc2632_ext_info, \
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun #define DECLARE_LTC2632_CHANNELS(_name, _bits) \
199*4882a593Smuzhiyun 	const struct iio_chan_spec _name ## _channels[] = { \
200*4882a593Smuzhiyun 		LTC2632_CHANNEL(0, _bits), \
201*4882a593Smuzhiyun 		LTC2632_CHANNEL(1, _bits), \
202*4882a593Smuzhiyun 		LTC2632_CHANNEL(2, _bits), \
203*4882a593Smuzhiyun 		LTC2632_CHANNEL(3, _bits), \
204*4882a593Smuzhiyun 		LTC2632_CHANNEL(4, _bits), \
205*4882a593Smuzhiyun 		LTC2632_CHANNEL(5, _bits), \
206*4882a593Smuzhiyun 		LTC2632_CHANNEL(6, _bits), \
207*4882a593Smuzhiyun 		LTC2632_CHANNEL(7, _bits), \
208*4882a593Smuzhiyun 	}
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun static DECLARE_LTC2632_CHANNELS(ltc2632x12, 12);
211*4882a593Smuzhiyun static DECLARE_LTC2632_CHANNELS(ltc2632x10, 10);
212*4882a593Smuzhiyun static DECLARE_LTC2632_CHANNELS(ltc2632x8, 8);
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun static const struct ltc2632_chip_info ltc2632_chip_info_tbl[] = {
215*4882a593Smuzhiyun 	[ID_LTC2632L12] = {
216*4882a593Smuzhiyun 		.channels	= ltc2632x12_channels,
217*4882a593Smuzhiyun 		.num_channels	= 2,
218*4882a593Smuzhiyun 		.vref_mv	= 2500,
219*4882a593Smuzhiyun 	},
220*4882a593Smuzhiyun 	[ID_LTC2632L10] = {
221*4882a593Smuzhiyun 		.channels	= ltc2632x10_channels,
222*4882a593Smuzhiyun 		.num_channels	= 2,
223*4882a593Smuzhiyun 		.vref_mv	= 2500,
224*4882a593Smuzhiyun 	},
225*4882a593Smuzhiyun 	[ID_LTC2632L8] =  {
226*4882a593Smuzhiyun 		.channels	= ltc2632x8_channels,
227*4882a593Smuzhiyun 		.num_channels	= 2,
228*4882a593Smuzhiyun 		.vref_mv	= 2500,
229*4882a593Smuzhiyun 	},
230*4882a593Smuzhiyun 	[ID_LTC2632H12] = {
231*4882a593Smuzhiyun 		.channels	= ltc2632x12_channels,
232*4882a593Smuzhiyun 		.num_channels	= 2,
233*4882a593Smuzhiyun 		.vref_mv	= 4096,
234*4882a593Smuzhiyun 	},
235*4882a593Smuzhiyun 	[ID_LTC2632H10] = {
236*4882a593Smuzhiyun 		.channels	= ltc2632x10_channels,
237*4882a593Smuzhiyun 		.num_channels	= 2,
238*4882a593Smuzhiyun 		.vref_mv	= 4096,
239*4882a593Smuzhiyun 	},
240*4882a593Smuzhiyun 	[ID_LTC2632H8] =  {
241*4882a593Smuzhiyun 		.channels	= ltc2632x8_channels,
242*4882a593Smuzhiyun 		.num_channels	= 2,
243*4882a593Smuzhiyun 		.vref_mv	= 4096,
244*4882a593Smuzhiyun 	},
245*4882a593Smuzhiyun 	[ID_LTC2634L12] = {
246*4882a593Smuzhiyun 		.channels	= ltc2632x12_channels,
247*4882a593Smuzhiyun 		.num_channels	= 4,
248*4882a593Smuzhiyun 		.vref_mv	= 2500,
249*4882a593Smuzhiyun 	},
250*4882a593Smuzhiyun 	[ID_LTC2634L10] = {
251*4882a593Smuzhiyun 		.channels	= ltc2632x10_channels,
252*4882a593Smuzhiyun 		.num_channels	= 4,
253*4882a593Smuzhiyun 		.vref_mv	= 2500,
254*4882a593Smuzhiyun 	},
255*4882a593Smuzhiyun 	[ID_LTC2634L8] =  {
256*4882a593Smuzhiyun 		.channels	= ltc2632x8_channels,
257*4882a593Smuzhiyun 		.num_channels	= 4,
258*4882a593Smuzhiyun 		.vref_mv	= 2500,
259*4882a593Smuzhiyun 	},
260*4882a593Smuzhiyun 	[ID_LTC2634H12] = {
261*4882a593Smuzhiyun 		.channels	= ltc2632x12_channels,
262*4882a593Smuzhiyun 		.num_channels	= 4,
263*4882a593Smuzhiyun 		.vref_mv	= 4096,
264*4882a593Smuzhiyun 	},
265*4882a593Smuzhiyun 	[ID_LTC2634H10] = {
266*4882a593Smuzhiyun 		.channels	= ltc2632x10_channels,
267*4882a593Smuzhiyun 		.num_channels	= 4,
268*4882a593Smuzhiyun 		.vref_mv	= 4096,
269*4882a593Smuzhiyun 	},
270*4882a593Smuzhiyun 	[ID_LTC2634H8] =  {
271*4882a593Smuzhiyun 		.channels	= ltc2632x8_channels,
272*4882a593Smuzhiyun 		.num_channels	= 4,
273*4882a593Smuzhiyun 		.vref_mv	= 4096,
274*4882a593Smuzhiyun 	},
275*4882a593Smuzhiyun 	[ID_LTC2636L12] = {
276*4882a593Smuzhiyun 		.channels	= ltc2632x12_channels,
277*4882a593Smuzhiyun 		.num_channels	= 8,
278*4882a593Smuzhiyun 		.vref_mv	= 2500,
279*4882a593Smuzhiyun 	},
280*4882a593Smuzhiyun 	[ID_LTC2636L10] = {
281*4882a593Smuzhiyun 		.channels	= ltc2632x10_channels,
282*4882a593Smuzhiyun 		.num_channels	= 8,
283*4882a593Smuzhiyun 		.vref_mv	= 2500,
284*4882a593Smuzhiyun 	},
285*4882a593Smuzhiyun 	[ID_LTC2636L8] =  {
286*4882a593Smuzhiyun 		.channels	= ltc2632x8_channels,
287*4882a593Smuzhiyun 		.num_channels	= 8,
288*4882a593Smuzhiyun 		.vref_mv	= 2500,
289*4882a593Smuzhiyun 	},
290*4882a593Smuzhiyun 	[ID_LTC2636H12] = {
291*4882a593Smuzhiyun 		.channels	= ltc2632x12_channels,
292*4882a593Smuzhiyun 		.num_channels	= 8,
293*4882a593Smuzhiyun 		.vref_mv	= 4096,
294*4882a593Smuzhiyun 	},
295*4882a593Smuzhiyun 	[ID_LTC2636H10] = {
296*4882a593Smuzhiyun 		.channels	= ltc2632x10_channels,
297*4882a593Smuzhiyun 		.num_channels	= 8,
298*4882a593Smuzhiyun 		.vref_mv	= 4096,
299*4882a593Smuzhiyun 	},
300*4882a593Smuzhiyun 	[ID_LTC2636H8] =  {
301*4882a593Smuzhiyun 		.channels	= ltc2632x8_channels,
302*4882a593Smuzhiyun 		.num_channels	= 8,
303*4882a593Smuzhiyun 		.vref_mv	= 4096,
304*4882a593Smuzhiyun 	},
305*4882a593Smuzhiyun };
306*4882a593Smuzhiyun 
ltc2632_probe(struct spi_device * spi)307*4882a593Smuzhiyun static int ltc2632_probe(struct spi_device *spi)
308*4882a593Smuzhiyun {
309*4882a593Smuzhiyun 	struct ltc2632_state *st;
310*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
311*4882a593Smuzhiyun 	struct ltc2632_chip_info *chip_info;
312*4882a593Smuzhiyun 	int ret;
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
315*4882a593Smuzhiyun 	if (!indio_dev)
316*4882a593Smuzhiyun 		return -ENOMEM;
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	st = iio_priv(indio_dev);
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 	spi_set_drvdata(spi, indio_dev);
321*4882a593Smuzhiyun 	st->spi_dev = spi;
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 	chip_info = (struct ltc2632_chip_info *)
324*4882a593Smuzhiyun 			spi_get_device_id(spi)->driver_data;
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun 	st->vref_reg = devm_regulator_get_optional(&spi->dev, "vref");
327*4882a593Smuzhiyun 	if (PTR_ERR(st->vref_reg) == -ENODEV) {
328*4882a593Smuzhiyun 		/* use internal reference voltage */
329*4882a593Smuzhiyun 		st->vref_reg = NULL;
330*4882a593Smuzhiyun 		st->vref_mv = chip_info->vref_mv;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 		ret = ltc2632_spi_write(spi, LTC2632_CMD_INTERNAL_REFER,
333*4882a593Smuzhiyun 				0, 0, 0);
334*4882a593Smuzhiyun 		if (ret) {
335*4882a593Smuzhiyun 			dev_err(&spi->dev,
336*4882a593Smuzhiyun 				"Set internal reference command failed, %d\n",
337*4882a593Smuzhiyun 				ret);
338*4882a593Smuzhiyun 			return ret;
339*4882a593Smuzhiyun 		}
340*4882a593Smuzhiyun 	} else if (IS_ERR(st->vref_reg)) {
341*4882a593Smuzhiyun 		dev_err(&spi->dev,
342*4882a593Smuzhiyun 				"Error getting voltage reference regulator\n");
343*4882a593Smuzhiyun 		return PTR_ERR(st->vref_reg);
344*4882a593Smuzhiyun 	} else {
345*4882a593Smuzhiyun 		/* use external reference voltage */
346*4882a593Smuzhiyun 		ret = regulator_enable(st->vref_reg);
347*4882a593Smuzhiyun 		if (ret) {
348*4882a593Smuzhiyun 			dev_err(&spi->dev,
349*4882a593Smuzhiyun 				"enable reference regulator failed, %d\n",
350*4882a593Smuzhiyun 				ret);
351*4882a593Smuzhiyun 			return ret;
352*4882a593Smuzhiyun 		}
353*4882a593Smuzhiyun 		st->vref_mv = regulator_get_voltage(st->vref_reg) / 1000;
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 		ret = ltc2632_spi_write(spi, LTC2632_CMD_EXTERNAL_REFER,
356*4882a593Smuzhiyun 				0, 0, 0);
357*4882a593Smuzhiyun 		if (ret) {
358*4882a593Smuzhiyun 			dev_err(&spi->dev,
359*4882a593Smuzhiyun 				"Set external reference command failed, %d\n",
360*4882a593Smuzhiyun 				ret);
361*4882a593Smuzhiyun 			return ret;
362*4882a593Smuzhiyun 		}
363*4882a593Smuzhiyun 	}
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	indio_dev->name = dev_of_node(&spi->dev) ? dev_of_node(&spi->dev)->name
366*4882a593Smuzhiyun 						 : spi_get_device_id(spi)->name;
367*4882a593Smuzhiyun 	indio_dev->info = &ltc2632_info;
368*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
369*4882a593Smuzhiyun 	indio_dev->channels = chip_info->channels;
370*4882a593Smuzhiyun 	indio_dev->num_channels = chip_info->num_channels;
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	return iio_device_register(indio_dev);
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun 
ltc2632_remove(struct spi_device * spi)375*4882a593Smuzhiyun static int ltc2632_remove(struct spi_device *spi)
376*4882a593Smuzhiyun {
377*4882a593Smuzhiyun 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
378*4882a593Smuzhiyun 	struct ltc2632_state *st = iio_priv(indio_dev);
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 	iio_device_unregister(indio_dev);
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	if (st->vref_reg)
383*4882a593Smuzhiyun 		regulator_disable(st->vref_reg);
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	return 0;
386*4882a593Smuzhiyun }
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun static const struct spi_device_id ltc2632_id[] = {
389*4882a593Smuzhiyun 	{ "ltc2632-l12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632L12] },
390*4882a593Smuzhiyun 	{ "ltc2632-l10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632L10] },
391*4882a593Smuzhiyun 	{ "ltc2632-l8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632L8] },
392*4882a593Smuzhiyun 	{ "ltc2632-h12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632H12] },
393*4882a593Smuzhiyun 	{ "ltc2632-h10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632H10] },
394*4882a593Smuzhiyun 	{ "ltc2632-h8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2632H8] },
395*4882a593Smuzhiyun 	{ "ltc2634-l12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634L12] },
396*4882a593Smuzhiyun 	{ "ltc2634-l10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634L10] },
397*4882a593Smuzhiyun 	{ "ltc2634-l8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634L8] },
398*4882a593Smuzhiyun 	{ "ltc2634-h12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634H12] },
399*4882a593Smuzhiyun 	{ "ltc2634-h10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634H10] },
400*4882a593Smuzhiyun 	{ "ltc2634-h8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2634H8] },
401*4882a593Smuzhiyun 	{ "ltc2636-l12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636L12] },
402*4882a593Smuzhiyun 	{ "ltc2636-l10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636L10] },
403*4882a593Smuzhiyun 	{ "ltc2636-l8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636L8] },
404*4882a593Smuzhiyun 	{ "ltc2636-h12", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636H12] },
405*4882a593Smuzhiyun 	{ "ltc2636-h10", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636H10] },
406*4882a593Smuzhiyun 	{ "ltc2636-h8", (kernel_ulong_t)&ltc2632_chip_info_tbl[ID_LTC2636H8] },
407*4882a593Smuzhiyun 	{}
408*4882a593Smuzhiyun };
409*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ltc2632_id);
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun static const struct of_device_id ltc2632_of_match[] = {
412*4882a593Smuzhiyun 	{
413*4882a593Smuzhiyun 		.compatible = "lltc,ltc2632-l12",
414*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2632L12]
415*4882a593Smuzhiyun 	}, {
416*4882a593Smuzhiyun 		.compatible = "lltc,ltc2632-l10",
417*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2632L10]
418*4882a593Smuzhiyun 	}, {
419*4882a593Smuzhiyun 		.compatible = "lltc,ltc2632-l8",
420*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2632L8]
421*4882a593Smuzhiyun 	}, {
422*4882a593Smuzhiyun 		.compatible = "lltc,ltc2632-h12",
423*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2632H12]
424*4882a593Smuzhiyun 	}, {
425*4882a593Smuzhiyun 		.compatible = "lltc,ltc2632-h10",
426*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2632H10]
427*4882a593Smuzhiyun 	}, {
428*4882a593Smuzhiyun 		.compatible = "lltc,ltc2632-h8",
429*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2632H8]
430*4882a593Smuzhiyun 	}, {
431*4882a593Smuzhiyun 		.compatible = "lltc,ltc2634-l12",
432*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2634L12]
433*4882a593Smuzhiyun 	}, {
434*4882a593Smuzhiyun 		.compatible = "lltc,ltc2634-l10",
435*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2634L10]
436*4882a593Smuzhiyun 	}, {
437*4882a593Smuzhiyun 		.compatible = "lltc,ltc2634-l8",
438*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2634L8]
439*4882a593Smuzhiyun 	}, {
440*4882a593Smuzhiyun 		.compatible = "lltc,ltc2634-h12",
441*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2634H12]
442*4882a593Smuzhiyun 	}, {
443*4882a593Smuzhiyun 		.compatible = "lltc,ltc2634-h10",
444*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2634H10]
445*4882a593Smuzhiyun 	}, {
446*4882a593Smuzhiyun 		.compatible = "lltc,ltc2634-h8",
447*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2634H8]
448*4882a593Smuzhiyun 	}, {
449*4882a593Smuzhiyun 		.compatible = "lltc,ltc2636-l12",
450*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2636L12]
451*4882a593Smuzhiyun 	}, {
452*4882a593Smuzhiyun 		.compatible = "lltc,ltc2636-l10",
453*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2636L10]
454*4882a593Smuzhiyun 	}, {
455*4882a593Smuzhiyun 		.compatible = "lltc,ltc2636-l8",
456*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2636L8]
457*4882a593Smuzhiyun 	}, {
458*4882a593Smuzhiyun 		.compatible = "lltc,ltc2636-h12",
459*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2636H12]
460*4882a593Smuzhiyun 	}, {
461*4882a593Smuzhiyun 		.compatible = "lltc,ltc2636-h10",
462*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2636H10]
463*4882a593Smuzhiyun 	}, {
464*4882a593Smuzhiyun 		.compatible = "lltc,ltc2636-h8",
465*4882a593Smuzhiyun 		.data = &ltc2632_chip_info_tbl[ID_LTC2636H8]
466*4882a593Smuzhiyun 	},
467*4882a593Smuzhiyun 	{}
468*4882a593Smuzhiyun };
469*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ltc2632_of_match);
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun static struct spi_driver ltc2632_driver = {
472*4882a593Smuzhiyun 	.driver		= {
473*4882a593Smuzhiyun 		.name	= "ltc2632",
474*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(ltc2632_of_match),
475*4882a593Smuzhiyun 	},
476*4882a593Smuzhiyun 	.probe		= ltc2632_probe,
477*4882a593Smuzhiyun 	.remove		= ltc2632_remove,
478*4882a593Smuzhiyun 	.id_table	= ltc2632_id,
479*4882a593Smuzhiyun };
480*4882a593Smuzhiyun module_spi_driver(ltc2632_driver);
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun MODULE_AUTHOR("Maxime Roussin-Belanger <maxime.roussinbelanger@gmail.com>");
483*4882a593Smuzhiyun MODULE_DESCRIPTION("LTC2632 DAC SPI driver");
484*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
485