xref: /OK3568_Linux_fs/kernel/drivers/iio/dac/ad5764.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Analog devices AD5764, AD5764R, AD5744, AD5744R quad-channel
4*4882a593Smuzhiyun  * Digital to Analog Converters driver
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright 2011 Analog Devices Inc.
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/err.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/spi/spi.h>
14*4882a593Smuzhiyun #include <linux/slab.h>
15*4882a593Smuzhiyun #include <linux/sysfs.h>
16*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <linux/iio/iio.h>
19*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define AD5764_REG_SF_NOP			0x0
22*4882a593Smuzhiyun #define AD5764_REG_SF_CONFIG			0x1
23*4882a593Smuzhiyun #define AD5764_REG_SF_CLEAR			0x4
24*4882a593Smuzhiyun #define AD5764_REG_SF_LOAD			0x5
25*4882a593Smuzhiyun #define AD5764_REG_DATA(x)			((2 << 3) | (x))
26*4882a593Smuzhiyun #define AD5764_REG_COARSE_GAIN(x)		((3 << 3) | (x))
27*4882a593Smuzhiyun #define AD5764_REG_FINE_GAIN(x)			((4 << 3) | (x))
28*4882a593Smuzhiyun #define AD5764_REG_OFFSET(x)			((5 << 3) | (x))
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define AD5764_NUM_CHANNELS 4
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /**
33*4882a593Smuzhiyun  * struct ad5764_chip_info - chip specific information
34*4882a593Smuzhiyun  * @int_vref:	Value of the internal reference voltage in uV - 0 if external
35*4882a593Smuzhiyun  *		reference voltage is used
36*4882a593Smuzhiyun  * @channels:	channel specification
37*4882a593Smuzhiyun */
38*4882a593Smuzhiyun struct ad5764_chip_info {
39*4882a593Smuzhiyun 	unsigned long int_vref;
40*4882a593Smuzhiyun 	const struct iio_chan_spec *channels;
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun /**
44*4882a593Smuzhiyun  * struct ad5764_state - driver instance specific data
45*4882a593Smuzhiyun  * @spi:		spi_device
46*4882a593Smuzhiyun  * @chip_info:		chip info
47*4882a593Smuzhiyun  * @vref_reg:		vref supply regulators
48*4882a593Smuzhiyun  * @lock:		lock to protect the data buffer during SPI ops
49*4882a593Smuzhiyun  * @data:		spi transfer buffers
50*4882a593Smuzhiyun  */
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun struct ad5764_state {
53*4882a593Smuzhiyun 	struct spi_device		*spi;
54*4882a593Smuzhiyun 	const struct ad5764_chip_info	*chip_info;
55*4882a593Smuzhiyun 	struct regulator_bulk_data	vref_reg[2];
56*4882a593Smuzhiyun 	struct mutex			lock;
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	/*
59*4882a593Smuzhiyun 	 * DMA (thus cache coherency maintenance) requires the
60*4882a593Smuzhiyun 	 * transfer buffers to live in their own cache lines.
61*4882a593Smuzhiyun 	 */
62*4882a593Smuzhiyun 	union {
63*4882a593Smuzhiyun 		__be32 d32;
64*4882a593Smuzhiyun 		u8 d8[4];
65*4882a593Smuzhiyun 	} data[2] ____cacheline_aligned;
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun enum ad5764_type {
69*4882a593Smuzhiyun 	ID_AD5744,
70*4882a593Smuzhiyun 	ID_AD5744R,
71*4882a593Smuzhiyun 	ID_AD5764,
72*4882a593Smuzhiyun 	ID_AD5764R,
73*4882a593Smuzhiyun };
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun #define AD5764_CHANNEL(_chan, _bits) {				\
76*4882a593Smuzhiyun 	.type = IIO_VOLTAGE,					\
77*4882a593Smuzhiyun 	.indexed = 1,						\
78*4882a593Smuzhiyun 	.output = 1,						\
79*4882a593Smuzhiyun 	.channel = (_chan),					\
80*4882a593Smuzhiyun 	.address = (_chan),					\
81*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
82*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_SCALE) |			\
83*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_CALIBSCALE) |			\
84*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_CALIBBIAS),			\
85*4882a593Smuzhiyun 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET),	\
86*4882a593Smuzhiyun 	.scan_type = {						\
87*4882a593Smuzhiyun 		.sign = 'u',					\
88*4882a593Smuzhiyun 		.realbits = (_bits),				\
89*4882a593Smuzhiyun 		.storagebits = 16,				\
90*4882a593Smuzhiyun 		.shift = 16 - (_bits),				\
91*4882a593Smuzhiyun 	},							\
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun #define DECLARE_AD5764_CHANNELS(_name, _bits) \
95*4882a593Smuzhiyun const struct iio_chan_spec _name##_channels[] = { \
96*4882a593Smuzhiyun 	AD5764_CHANNEL(0, (_bits)), \
97*4882a593Smuzhiyun 	AD5764_CHANNEL(1, (_bits)), \
98*4882a593Smuzhiyun 	AD5764_CHANNEL(2, (_bits)), \
99*4882a593Smuzhiyun 	AD5764_CHANNEL(3, (_bits)), \
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun static DECLARE_AD5764_CHANNELS(ad5764, 16);
103*4882a593Smuzhiyun static DECLARE_AD5764_CHANNELS(ad5744, 14);
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun static const struct ad5764_chip_info ad5764_chip_infos[] = {
106*4882a593Smuzhiyun 	[ID_AD5744] = {
107*4882a593Smuzhiyun 		.int_vref = 0,
108*4882a593Smuzhiyun 		.channels = ad5744_channels,
109*4882a593Smuzhiyun 	},
110*4882a593Smuzhiyun 	[ID_AD5744R] = {
111*4882a593Smuzhiyun 		.int_vref = 5000000,
112*4882a593Smuzhiyun 		.channels = ad5744_channels,
113*4882a593Smuzhiyun 	},
114*4882a593Smuzhiyun 	[ID_AD5764] = {
115*4882a593Smuzhiyun 		.int_vref = 0,
116*4882a593Smuzhiyun 		.channels = ad5764_channels,
117*4882a593Smuzhiyun 	},
118*4882a593Smuzhiyun 	[ID_AD5764R] = {
119*4882a593Smuzhiyun 		.int_vref = 5000000,
120*4882a593Smuzhiyun 		.channels = ad5764_channels,
121*4882a593Smuzhiyun 	},
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun 
ad5764_write(struct iio_dev * indio_dev,unsigned int reg,unsigned int val)124*4882a593Smuzhiyun static int ad5764_write(struct iio_dev *indio_dev, unsigned int reg,
125*4882a593Smuzhiyun 	unsigned int val)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun 	struct ad5764_state *st = iio_priv(indio_dev);
128*4882a593Smuzhiyun 	int ret;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	mutex_lock(&st->lock);
131*4882a593Smuzhiyun 	st->data[0].d32 = cpu_to_be32((reg << 16) | val);
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	ret = spi_write(st->spi, &st->data[0].d8[1], 3);
134*4882a593Smuzhiyun 	mutex_unlock(&st->lock);
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	return ret;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun 
ad5764_read(struct iio_dev * indio_dev,unsigned int reg,unsigned int * val)139*4882a593Smuzhiyun static int ad5764_read(struct iio_dev *indio_dev, unsigned int reg,
140*4882a593Smuzhiyun 	unsigned int *val)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	struct ad5764_state *st = iio_priv(indio_dev);
143*4882a593Smuzhiyun 	int ret;
144*4882a593Smuzhiyun 	struct spi_transfer t[] = {
145*4882a593Smuzhiyun 		{
146*4882a593Smuzhiyun 			.tx_buf = &st->data[0].d8[1],
147*4882a593Smuzhiyun 			.len = 3,
148*4882a593Smuzhiyun 			.cs_change = 1,
149*4882a593Smuzhiyun 		}, {
150*4882a593Smuzhiyun 			.rx_buf = &st->data[1].d8[1],
151*4882a593Smuzhiyun 			.len = 3,
152*4882a593Smuzhiyun 		},
153*4882a593Smuzhiyun 	};
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	mutex_lock(&st->lock);
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	st->data[0].d32 = cpu_to_be32((1 << 23) | (reg << 16));
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
160*4882a593Smuzhiyun 	if (ret >= 0)
161*4882a593Smuzhiyun 		*val = be32_to_cpu(st->data[1].d32) & 0xffff;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	mutex_unlock(&st->lock);
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	return ret;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun 
ad5764_chan_info_to_reg(struct iio_chan_spec const * chan,long info)168*4882a593Smuzhiyun static int ad5764_chan_info_to_reg(struct iio_chan_spec const *chan, long info)
169*4882a593Smuzhiyun {
170*4882a593Smuzhiyun 	switch (info) {
171*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
172*4882a593Smuzhiyun 		return AD5764_REG_DATA(chan->address);
173*4882a593Smuzhiyun 	case IIO_CHAN_INFO_CALIBBIAS:
174*4882a593Smuzhiyun 		return AD5764_REG_OFFSET(chan->address);
175*4882a593Smuzhiyun 	case IIO_CHAN_INFO_CALIBSCALE:
176*4882a593Smuzhiyun 		return AD5764_REG_FINE_GAIN(chan->address);
177*4882a593Smuzhiyun 	default:
178*4882a593Smuzhiyun 		break;
179*4882a593Smuzhiyun 	}
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	return 0;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun 
ad5764_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)184*4882a593Smuzhiyun static int ad5764_write_raw(struct iio_dev *indio_dev,
185*4882a593Smuzhiyun 	struct iio_chan_spec const *chan, int val, int val2, long info)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun 	const int max_val = (1 << chan->scan_type.realbits);
188*4882a593Smuzhiyun 	unsigned int reg;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	switch (info) {
191*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
192*4882a593Smuzhiyun 		if (val >= max_val || val < 0)
193*4882a593Smuzhiyun 			return -EINVAL;
194*4882a593Smuzhiyun 		val <<= chan->scan_type.shift;
195*4882a593Smuzhiyun 		break;
196*4882a593Smuzhiyun 	case IIO_CHAN_INFO_CALIBBIAS:
197*4882a593Smuzhiyun 		if (val >= 128 || val < -128)
198*4882a593Smuzhiyun 			return -EINVAL;
199*4882a593Smuzhiyun 		break;
200*4882a593Smuzhiyun 	case IIO_CHAN_INFO_CALIBSCALE:
201*4882a593Smuzhiyun 		if (val >= 32 || val < -32)
202*4882a593Smuzhiyun 			return -EINVAL;
203*4882a593Smuzhiyun 		break;
204*4882a593Smuzhiyun 	default:
205*4882a593Smuzhiyun 		return -EINVAL;
206*4882a593Smuzhiyun 	}
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	reg = ad5764_chan_info_to_reg(chan, info);
209*4882a593Smuzhiyun 	return ad5764_write(indio_dev, reg, (u16)val);
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun 
ad5764_get_channel_vref(struct ad5764_state * st,unsigned int channel)212*4882a593Smuzhiyun static int ad5764_get_channel_vref(struct ad5764_state *st,
213*4882a593Smuzhiyun 	unsigned int channel)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun 	if (st->chip_info->int_vref)
216*4882a593Smuzhiyun 		return st->chip_info->int_vref;
217*4882a593Smuzhiyun 	else
218*4882a593Smuzhiyun 		return regulator_get_voltage(st->vref_reg[channel / 2].consumer);
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun 
ad5764_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)221*4882a593Smuzhiyun static int ad5764_read_raw(struct iio_dev *indio_dev,
222*4882a593Smuzhiyun 	struct iio_chan_spec const *chan, int *val, int *val2, long info)
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun 	struct ad5764_state *st = iio_priv(indio_dev);
225*4882a593Smuzhiyun 	unsigned int reg;
226*4882a593Smuzhiyun 	int vref;
227*4882a593Smuzhiyun 	int ret;
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	switch (info) {
230*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
231*4882a593Smuzhiyun 		reg = AD5764_REG_DATA(chan->address);
232*4882a593Smuzhiyun 		ret = ad5764_read(indio_dev, reg, val);
233*4882a593Smuzhiyun 		if (ret < 0)
234*4882a593Smuzhiyun 			return ret;
235*4882a593Smuzhiyun 		*val >>= chan->scan_type.shift;
236*4882a593Smuzhiyun 		return IIO_VAL_INT;
237*4882a593Smuzhiyun 	case IIO_CHAN_INFO_CALIBBIAS:
238*4882a593Smuzhiyun 		reg = AD5764_REG_OFFSET(chan->address);
239*4882a593Smuzhiyun 		ret = ad5764_read(indio_dev, reg, val);
240*4882a593Smuzhiyun 		if (ret < 0)
241*4882a593Smuzhiyun 			return ret;
242*4882a593Smuzhiyun 		*val = sign_extend32(*val, 7);
243*4882a593Smuzhiyun 		return IIO_VAL_INT;
244*4882a593Smuzhiyun 	case IIO_CHAN_INFO_CALIBSCALE:
245*4882a593Smuzhiyun 		reg = AD5764_REG_FINE_GAIN(chan->address);
246*4882a593Smuzhiyun 		ret = ad5764_read(indio_dev, reg, val);
247*4882a593Smuzhiyun 		if (ret < 0)
248*4882a593Smuzhiyun 			return ret;
249*4882a593Smuzhiyun 		*val = sign_extend32(*val, 5);
250*4882a593Smuzhiyun 		return IIO_VAL_INT;
251*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
252*4882a593Smuzhiyun 		/* vout = 4 * vref + ((dac_code / 65536) - 0.5) */
253*4882a593Smuzhiyun 		vref = ad5764_get_channel_vref(st, chan->channel);
254*4882a593Smuzhiyun 		if (vref < 0)
255*4882a593Smuzhiyun 			return vref;
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 		*val = vref * 4 / 1000;
258*4882a593Smuzhiyun 		*val2 = chan->scan_type.realbits;
259*4882a593Smuzhiyun 		return IIO_VAL_FRACTIONAL_LOG2;
260*4882a593Smuzhiyun 	case IIO_CHAN_INFO_OFFSET:
261*4882a593Smuzhiyun 		*val = -(1 << chan->scan_type.realbits) / 2;
262*4882a593Smuzhiyun 		return IIO_VAL_INT;
263*4882a593Smuzhiyun 	}
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	return -EINVAL;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun static const struct iio_info ad5764_info = {
269*4882a593Smuzhiyun 	.read_raw = ad5764_read_raw,
270*4882a593Smuzhiyun 	.write_raw = ad5764_write_raw,
271*4882a593Smuzhiyun };
272*4882a593Smuzhiyun 
ad5764_probe(struct spi_device * spi)273*4882a593Smuzhiyun static int ad5764_probe(struct spi_device *spi)
274*4882a593Smuzhiyun {
275*4882a593Smuzhiyun 	enum ad5764_type type = spi_get_device_id(spi)->driver_data;
276*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
277*4882a593Smuzhiyun 	struct ad5764_state *st;
278*4882a593Smuzhiyun 	int ret;
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
281*4882a593Smuzhiyun 	if (indio_dev == NULL) {
282*4882a593Smuzhiyun 		dev_err(&spi->dev, "Failed to allocate iio device\n");
283*4882a593Smuzhiyun 		return -ENOMEM;
284*4882a593Smuzhiyun 	}
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	st = iio_priv(indio_dev);
287*4882a593Smuzhiyun 	spi_set_drvdata(spi, indio_dev);
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	st->spi = spi;
290*4882a593Smuzhiyun 	st->chip_info = &ad5764_chip_infos[type];
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	indio_dev->name = spi_get_device_id(spi)->name;
293*4882a593Smuzhiyun 	indio_dev->info = &ad5764_info;
294*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
295*4882a593Smuzhiyun 	indio_dev->num_channels = AD5764_NUM_CHANNELS;
296*4882a593Smuzhiyun 	indio_dev->channels = st->chip_info->channels;
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	mutex_init(&st->lock);
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	if (st->chip_info->int_vref == 0) {
301*4882a593Smuzhiyun 		st->vref_reg[0].supply = "vrefAB";
302*4882a593Smuzhiyun 		st->vref_reg[1].supply = "vrefCD";
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 		ret = devm_regulator_bulk_get(&st->spi->dev,
305*4882a593Smuzhiyun 			ARRAY_SIZE(st->vref_reg), st->vref_reg);
306*4882a593Smuzhiyun 		if (ret) {
307*4882a593Smuzhiyun 			dev_err(&spi->dev, "Failed to request vref regulators: %d\n",
308*4882a593Smuzhiyun 				ret);
309*4882a593Smuzhiyun 			return ret;
310*4882a593Smuzhiyun 		}
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 		ret = regulator_bulk_enable(ARRAY_SIZE(st->vref_reg),
313*4882a593Smuzhiyun 			st->vref_reg);
314*4882a593Smuzhiyun 		if (ret) {
315*4882a593Smuzhiyun 			dev_err(&spi->dev, "Failed to enable vref regulators: %d\n",
316*4882a593Smuzhiyun 				ret);
317*4882a593Smuzhiyun 			return ret;
318*4882a593Smuzhiyun 		}
319*4882a593Smuzhiyun 	}
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	ret = iio_device_register(indio_dev);
322*4882a593Smuzhiyun 	if (ret) {
323*4882a593Smuzhiyun 		dev_err(&spi->dev, "Failed to register iio device: %d\n", ret);
324*4882a593Smuzhiyun 		goto error_disable_reg;
325*4882a593Smuzhiyun 	}
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	return 0;
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun error_disable_reg:
330*4882a593Smuzhiyun 	if (st->chip_info->int_vref == 0)
331*4882a593Smuzhiyun 		regulator_bulk_disable(ARRAY_SIZE(st->vref_reg), st->vref_reg);
332*4882a593Smuzhiyun 	return ret;
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun 
ad5764_remove(struct spi_device * spi)335*4882a593Smuzhiyun static int ad5764_remove(struct spi_device *spi)
336*4882a593Smuzhiyun {
337*4882a593Smuzhiyun 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
338*4882a593Smuzhiyun 	struct ad5764_state *st = iio_priv(indio_dev);
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	iio_device_unregister(indio_dev);
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	if (st->chip_info->int_vref == 0)
343*4882a593Smuzhiyun 		regulator_bulk_disable(ARRAY_SIZE(st->vref_reg), st->vref_reg);
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	return 0;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun static const struct spi_device_id ad5764_ids[] = {
349*4882a593Smuzhiyun 	{ "ad5744", ID_AD5744 },
350*4882a593Smuzhiyun 	{ "ad5744r", ID_AD5744R },
351*4882a593Smuzhiyun 	{ "ad5764", ID_AD5764 },
352*4882a593Smuzhiyun 	{ "ad5764r", ID_AD5764R },
353*4882a593Smuzhiyun 	{ }
354*4882a593Smuzhiyun };
355*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ad5764_ids);
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun static struct spi_driver ad5764_driver = {
358*4882a593Smuzhiyun 	.driver = {
359*4882a593Smuzhiyun 		.name = "ad5764",
360*4882a593Smuzhiyun 	},
361*4882a593Smuzhiyun 	.probe = ad5764_probe,
362*4882a593Smuzhiyun 	.remove = ad5764_remove,
363*4882a593Smuzhiyun 	.id_table = ad5764_ids,
364*4882a593Smuzhiyun };
365*4882a593Smuzhiyun module_spi_driver(ad5764_driver);
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
368*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices AD5744/AD5744R/AD5764/AD5764R DAC");
369*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
370