1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * AD5721, AD5721R, AD5761, AD5761R, Voltage Output Digital to Analog Converter
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2016 Qtechnology A/S
6*4882a593Smuzhiyun * 2016 Ricardo Ribalda <ribalda@kernel.org>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/spi/spi.h>
11*4882a593Smuzhiyun #include <linux/bitops.h>
12*4882a593Smuzhiyun #include <linux/iio/iio.h>
13*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
14*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
15*4882a593Smuzhiyun #include <linux/platform_data/ad5761.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define AD5761_ADDR(addr) ((addr & 0xf) << 16)
18*4882a593Smuzhiyun #define AD5761_ADDR_NOOP 0x0
19*4882a593Smuzhiyun #define AD5761_ADDR_DAC_WRITE 0x3
20*4882a593Smuzhiyun #define AD5761_ADDR_CTRL_WRITE_REG 0x4
21*4882a593Smuzhiyun #define AD5761_ADDR_SW_DATA_RESET 0x7
22*4882a593Smuzhiyun #define AD5761_ADDR_DAC_READ 0xb
23*4882a593Smuzhiyun #define AD5761_ADDR_CTRL_READ_REG 0xc
24*4882a593Smuzhiyun #define AD5761_ADDR_SW_FULL_RESET 0xf
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define AD5761_CTRL_USE_INTVREF BIT(5)
27*4882a593Smuzhiyun #define AD5761_CTRL_ETS BIT(6)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /**
30*4882a593Smuzhiyun * struct ad5761_chip_info - chip specific information
31*4882a593Smuzhiyun * @int_vref: Value of the internal reference voltage in mV - 0 if external
32*4882a593Smuzhiyun * reference voltage is used
33*4882a593Smuzhiyun * @channel: channel specification
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun struct ad5761_chip_info {
37*4882a593Smuzhiyun unsigned long int_vref;
38*4882a593Smuzhiyun const struct iio_chan_spec channel;
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun struct ad5761_range_params {
42*4882a593Smuzhiyun int m;
43*4882a593Smuzhiyun int c;
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun enum ad5761_supported_device_ids {
47*4882a593Smuzhiyun ID_AD5721,
48*4882a593Smuzhiyun ID_AD5721R,
49*4882a593Smuzhiyun ID_AD5761,
50*4882a593Smuzhiyun ID_AD5761R,
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /**
54*4882a593Smuzhiyun * struct ad5761_state - driver instance specific data
55*4882a593Smuzhiyun * @spi: spi_device
56*4882a593Smuzhiyun * @vref_reg: reference voltage regulator
57*4882a593Smuzhiyun * @use_intref: true when the internal voltage reference is used
58*4882a593Smuzhiyun * @vref: actual voltage reference in mVolts
59*4882a593Smuzhiyun * @range: output range mode used
60*4882a593Smuzhiyun * @lock: lock to protect the data buffer during SPI ops
61*4882a593Smuzhiyun * @data: cache aligned spi buffer
62*4882a593Smuzhiyun */
63*4882a593Smuzhiyun struct ad5761_state {
64*4882a593Smuzhiyun struct spi_device *spi;
65*4882a593Smuzhiyun struct regulator *vref_reg;
66*4882a593Smuzhiyun struct mutex lock;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun bool use_intref;
69*4882a593Smuzhiyun int vref;
70*4882a593Smuzhiyun enum ad5761_voltage_range range;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /*
73*4882a593Smuzhiyun * DMA (thus cache coherency maintenance) requires the
74*4882a593Smuzhiyun * transfer buffers to live in their own cache lines.
75*4882a593Smuzhiyun */
76*4882a593Smuzhiyun union {
77*4882a593Smuzhiyun __be32 d32;
78*4882a593Smuzhiyun u8 d8[4];
79*4882a593Smuzhiyun } data[3] ____cacheline_aligned;
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static const struct ad5761_range_params ad5761_range_params[] = {
83*4882a593Smuzhiyun [AD5761_VOLTAGE_RANGE_M10V_10V] = {
84*4882a593Smuzhiyun .m = 80,
85*4882a593Smuzhiyun .c = 40,
86*4882a593Smuzhiyun },
87*4882a593Smuzhiyun [AD5761_VOLTAGE_RANGE_0V_10V] = {
88*4882a593Smuzhiyun .m = 40,
89*4882a593Smuzhiyun .c = 0,
90*4882a593Smuzhiyun },
91*4882a593Smuzhiyun [AD5761_VOLTAGE_RANGE_M5V_5V] = {
92*4882a593Smuzhiyun .m = 40,
93*4882a593Smuzhiyun .c = 20,
94*4882a593Smuzhiyun },
95*4882a593Smuzhiyun [AD5761_VOLTAGE_RANGE_0V_5V] = {
96*4882a593Smuzhiyun .m = 20,
97*4882a593Smuzhiyun .c = 0,
98*4882a593Smuzhiyun },
99*4882a593Smuzhiyun [AD5761_VOLTAGE_RANGE_M2V5_7V5] = {
100*4882a593Smuzhiyun .m = 40,
101*4882a593Smuzhiyun .c = 10,
102*4882a593Smuzhiyun },
103*4882a593Smuzhiyun [AD5761_VOLTAGE_RANGE_M3V_3V] = {
104*4882a593Smuzhiyun .m = 24,
105*4882a593Smuzhiyun .c = 12,
106*4882a593Smuzhiyun },
107*4882a593Smuzhiyun [AD5761_VOLTAGE_RANGE_0V_16V] = {
108*4882a593Smuzhiyun .m = 64,
109*4882a593Smuzhiyun .c = 0,
110*4882a593Smuzhiyun },
111*4882a593Smuzhiyun [AD5761_VOLTAGE_RANGE_0V_20V] = {
112*4882a593Smuzhiyun .m = 80,
113*4882a593Smuzhiyun .c = 0,
114*4882a593Smuzhiyun },
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun
_ad5761_spi_write(struct ad5761_state * st,u8 addr,u16 val)117*4882a593Smuzhiyun static int _ad5761_spi_write(struct ad5761_state *st, u8 addr, u16 val)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun st->data[0].d32 = cpu_to_be32(AD5761_ADDR(addr) | val);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun return spi_write(st->spi, &st->data[0].d8[1], 3);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
ad5761_spi_write(struct iio_dev * indio_dev,u8 addr,u16 val)124*4882a593Smuzhiyun static int ad5761_spi_write(struct iio_dev *indio_dev, u8 addr, u16 val)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun struct ad5761_state *st = iio_priv(indio_dev);
127*4882a593Smuzhiyun int ret;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun mutex_lock(&st->lock);
130*4882a593Smuzhiyun ret = _ad5761_spi_write(st, addr, val);
131*4882a593Smuzhiyun mutex_unlock(&st->lock);
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun return ret;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
_ad5761_spi_read(struct ad5761_state * st,u8 addr,u16 * val)136*4882a593Smuzhiyun static int _ad5761_spi_read(struct ad5761_state *st, u8 addr, u16 *val)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun int ret;
139*4882a593Smuzhiyun struct spi_transfer xfers[] = {
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun .tx_buf = &st->data[0].d8[1],
142*4882a593Smuzhiyun .bits_per_word = 8,
143*4882a593Smuzhiyun .len = 3,
144*4882a593Smuzhiyun .cs_change = true,
145*4882a593Smuzhiyun }, {
146*4882a593Smuzhiyun .tx_buf = &st->data[1].d8[1],
147*4882a593Smuzhiyun .rx_buf = &st->data[2].d8[1],
148*4882a593Smuzhiyun .bits_per_word = 8,
149*4882a593Smuzhiyun .len = 3,
150*4882a593Smuzhiyun },
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun st->data[0].d32 = cpu_to_be32(AD5761_ADDR(addr));
154*4882a593Smuzhiyun st->data[1].d32 = cpu_to_be32(AD5761_ADDR(AD5761_ADDR_NOOP));
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun ret = spi_sync_transfer(st->spi, xfers, ARRAY_SIZE(xfers));
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun *val = be32_to_cpu(st->data[2].d32);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun return ret;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
ad5761_spi_read(struct iio_dev * indio_dev,u8 addr,u16 * val)163*4882a593Smuzhiyun static int ad5761_spi_read(struct iio_dev *indio_dev, u8 addr, u16 *val)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun struct ad5761_state *st = iio_priv(indio_dev);
166*4882a593Smuzhiyun int ret;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun mutex_lock(&st->lock);
169*4882a593Smuzhiyun ret = _ad5761_spi_read(st, addr, val);
170*4882a593Smuzhiyun mutex_unlock(&st->lock);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun return ret;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
ad5761_spi_set_range(struct ad5761_state * st,enum ad5761_voltage_range range)175*4882a593Smuzhiyun static int ad5761_spi_set_range(struct ad5761_state *st,
176*4882a593Smuzhiyun enum ad5761_voltage_range range)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun u16 aux;
179*4882a593Smuzhiyun int ret;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun aux = (range & 0x7) | AD5761_CTRL_ETS;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun if (st->use_intref)
184*4882a593Smuzhiyun aux |= AD5761_CTRL_USE_INTVREF;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun ret = _ad5761_spi_write(st, AD5761_ADDR_SW_FULL_RESET, 0);
187*4882a593Smuzhiyun if (ret)
188*4882a593Smuzhiyun return ret;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun ret = _ad5761_spi_write(st, AD5761_ADDR_CTRL_WRITE_REG, aux);
191*4882a593Smuzhiyun if (ret)
192*4882a593Smuzhiyun return ret;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun st->range = range;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun return 0;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
ad5761_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)199*4882a593Smuzhiyun static int ad5761_read_raw(struct iio_dev *indio_dev,
200*4882a593Smuzhiyun struct iio_chan_spec const *chan,
201*4882a593Smuzhiyun int *val,
202*4882a593Smuzhiyun int *val2,
203*4882a593Smuzhiyun long mask)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun struct ad5761_state *st;
206*4882a593Smuzhiyun int ret;
207*4882a593Smuzhiyun u16 aux;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun switch (mask) {
210*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
211*4882a593Smuzhiyun ret = ad5761_spi_read(indio_dev, AD5761_ADDR_DAC_READ, &aux);
212*4882a593Smuzhiyun if (ret)
213*4882a593Smuzhiyun return ret;
214*4882a593Smuzhiyun *val = aux >> chan->scan_type.shift;
215*4882a593Smuzhiyun return IIO_VAL_INT;
216*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
217*4882a593Smuzhiyun st = iio_priv(indio_dev);
218*4882a593Smuzhiyun *val = st->vref * ad5761_range_params[st->range].m;
219*4882a593Smuzhiyun *val /= 10;
220*4882a593Smuzhiyun *val2 = chan->scan_type.realbits;
221*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL_LOG2;
222*4882a593Smuzhiyun case IIO_CHAN_INFO_OFFSET:
223*4882a593Smuzhiyun st = iio_priv(indio_dev);
224*4882a593Smuzhiyun *val = -(1 << chan->scan_type.realbits);
225*4882a593Smuzhiyun *val *= ad5761_range_params[st->range].c;
226*4882a593Smuzhiyun *val /= ad5761_range_params[st->range].m;
227*4882a593Smuzhiyun return IIO_VAL_INT;
228*4882a593Smuzhiyun default:
229*4882a593Smuzhiyun return -EINVAL;
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
ad5761_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)233*4882a593Smuzhiyun static int ad5761_write_raw(struct iio_dev *indio_dev,
234*4882a593Smuzhiyun struct iio_chan_spec const *chan,
235*4882a593Smuzhiyun int val,
236*4882a593Smuzhiyun int val2,
237*4882a593Smuzhiyun long mask)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun u16 aux;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun if (mask != IIO_CHAN_INFO_RAW)
242*4882a593Smuzhiyun return -EINVAL;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun if (val2 || (val << chan->scan_type.shift) > 0xffff || val < 0)
245*4882a593Smuzhiyun return -EINVAL;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun aux = val << chan->scan_type.shift;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun return ad5761_spi_write(indio_dev, AD5761_ADDR_DAC_WRITE, aux);
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun static const struct iio_info ad5761_info = {
253*4882a593Smuzhiyun .read_raw = &ad5761_read_raw,
254*4882a593Smuzhiyun .write_raw = &ad5761_write_raw,
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun #define AD5761_CHAN(_bits) { \
258*4882a593Smuzhiyun .type = IIO_VOLTAGE, \
259*4882a593Smuzhiyun .output = 1, \
260*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
261*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
262*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_OFFSET), \
263*4882a593Smuzhiyun .scan_type = { \
264*4882a593Smuzhiyun .sign = 'u', \
265*4882a593Smuzhiyun .realbits = (_bits), \
266*4882a593Smuzhiyun .storagebits = 16, \
267*4882a593Smuzhiyun .shift = 16 - (_bits), \
268*4882a593Smuzhiyun }, \
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun static const struct ad5761_chip_info ad5761_chip_infos[] = {
272*4882a593Smuzhiyun [ID_AD5721] = {
273*4882a593Smuzhiyun .int_vref = 0,
274*4882a593Smuzhiyun .channel = AD5761_CHAN(12),
275*4882a593Smuzhiyun },
276*4882a593Smuzhiyun [ID_AD5721R] = {
277*4882a593Smuzhiyun .int_vref = 2500,
278*4882a593Smuzhiyun .channel = AD5761_CHAN(12),
279*4882a593Smuzhiyun },
280*4882a593Smuzhiyun [ID_AD5761] = {
281*4882a593Smuzhiyun .int_vref = 0,
282*4882a593Smuzhiyun .channel = AD5761_CHAN(16),
283*4882a593Smuzhiyun },
284*4882a593Smuzhiyun [ID_AD5761R] = {
285*4882a593Smuzhiyun .int_vref = 2500,
286*4882a593Smuzhiyun .channel = AD5761_CHAN(16),
287*4882a593Smuzhiyun },
288*4882a593Smuzhiyun };
289*4882a593Smuzhiyun
ad5761_get_vref(struct ad5761_state * st,const struct ad5761_chip_info * chip_info)290*4882a593Smuzhiyun static int ad5761_get_vref(struct ad5761_state *st,
291*4882a593Smuzhiyun const struct ad5761_chip_info *chip_info)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun int ret;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun st->vref_reg = devm_regulator_get_optional(&st->spi->dev, "vref");
296*4882a593Smuzhiyun if (PTR_ERR(st->vref_reg) == -ENODEV) {
297*4882a593Smuzhiyun /* Use Internal regulator */
298*4882a593Smuzhiyun if (!chip_info->int_vref) {
299*4882a593Smuzhiyun dev_err(&st->spi->dev,
300*4882a593Smuzhiyun "Voltage reference not found\n");
301*4882a593Smuzhiyun return -EIO;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun st->use_intref = true;
305*4882a593Smuzhiyun st->vref = chip_info->int_vref;
306*4882a593Smuzhiyun return 0;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun if (IS_ERR(st->vref_reg)) {
310*4882a593Smuzhiyun dev_err(&st->spi->dev,
311*4882a593Smuzhiyun "Error getting voltage reference regulator\n");
312*4882a593Smuzhiyun return PTR_ERR(st->vref_reg);
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun ret = regulator_enable(st->vref_reg);
316*4882a593Smuzhiyun if (ret) {
317*4882a593Smuzhiyun dev_err(&st->spi->dev,
318*4882a593Smuzhiyun "Failed to enable voltage reference\n");
319*4882a593Smuzhiyun return ret;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun ret = regulator_get_voltage(st->vref_reg);
323*4882a593Smuzhiyun if (ret < 0) {
324*4882a593Smuzhiyun dev_err(&st->spi->dev,
325*4882a593Smuzhiyun "Failed to get voltage reference value\n");
326*4882a593Smuzhiyun goto disable_regulator_vref;
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun if (ret < 2000000 || ret > 3000000) {
330*4882a593Smuzhiyun dev_warn(&st->spi->dev,
331*4882a593Smuzhiyun "Invalid external voltage ref. value %d uV\n", ret);
332*4882a593Smuzhiyun ret = -EIO;
333*4882a593Smuzhiyun goto disable_regulator_vref;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun st->vref = ret / 1000;
337*4882a593Smuzhiyun st->use_intref = false;
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun return 0;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun disable_regulator_vref:
342*4882a593Smuzhiyun regulator_disable(st->vref_reg);
343*4882a593Smuzhiyun st->vref_reg = NULL;
344*4882a593Smuzhiyun return ret;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
ad5761_probe(struct spi_device * spi)347*4882a593Smuzhiyun static int ad5761_probe(struct spi_device *spi)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun struct iio_dev *iio_dev;
350*4882a593Smuzhiyun struct ad5761_state *st;
351*4882a593Smuzhiyun int ret;
352*4882a593Smuzhiyun const struct ad5761_chip_info *chip_info =
353*4882a593Smuzhiyun &ad5761_chip_infos[spi_get_device_id(spi)->driver_data];
354*4882a593Smuzhiyun enum ad5761_voltage_range voltage_range = AD5761_VOLTAGE_RANGE_0V_5V;
355*4882a593Smuzhiyun struct ad5761_platform_data *pdata = dev_get_platdata(&spi->dev);
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun iio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
358*4882a593Smuzhiyun if (!iio_dev)
359*4882a593Smuzhiyun return -ENOMEM;
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun st = iio_priv(iio_dev);
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun st->spi = spi;
364*4882a593Smuzhiyun spi_set_drvdata(spi, iio_dev);
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun ret = ad5761_get_vref(st, chip_info);
367*4882a593Smuzhiyun if (ret)
368*4882a593Smuzhiyun return ret;
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun if (pdata)
371*4882a593Smuzhiyun voltage_range = pdata->voltage_range;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun mutex_init(&st->lock);
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun ret = ad5761_spi_set_range(st, voltage_range);
376*4882a593Smuzhiyun if (ret)
377*4882a593Smuzhiyun goto disable_regulator_err;
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun iio_dev->info = &ad5761_info;
380*4882a593Smuzhiyun iio_dev->modes = INDIO_DIRECT_MODE;
381*4882a593Smuzhiyun iio_dev->channels = &chip_info->channel;
382*4882a593Smuzhiyun iio_dev->num_channels = 1;
383*4882a593Smuzhiyun iio_dev->name = spi_get_device_id(st->spi)->name;
384*4882a593Smuzhiyun ret = iio_device_register(iio_dev);
385*4882a593Smuzhiyun if (ret)
386*4882a593Smuzhiyun goto disable_regulator_err;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun return 0;
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun disable_regulator_err:
391*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(st->vref_reg))
392*4882a593Smuzhiyun regulator_disable(st->vref_reg);
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun return ret;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun
ad5761_remove(struct spi_device * spi)397*4882a593Smuzhiyun static int ad5761_remove(struct spi_device *spi)
398*4882a593Smuzhiyun {
399*4882a593Smuzhiyun struct iio_dev *iio_dev = spi_get_drvdata(spi);
400*4882a593Smuzhiyun struct ad5761_state *st = iio_priv(iio_dev);
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun iio_device_unregister(iio_dev);
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun if (!IS_ERR_OR_NULL(st->vref_reg))
405*4882a593Smuzhiyun regulator_disable(st->vref_reg);
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun return 0;
408*4882a593Smuzhiyun }
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun static const struct spi_device_id ad5761_id[] = {
411*4882a593Smuzhiyun {"ad5721", ID_AD5721},
412*4882a593Smuzhiyun {"ad5721r", ID_AD5721R},
413*4882a593Smuzhiyun {"ad5761", ID_AD5761},
414*4882a593Smuzhiyun {"ad5761r", ID_AD5761R},
415*4882a593Smuzhiyun {}
416*4882a593Smuzhiyun };
417*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ad5761_id);
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun static struct spi_driver ad5761_driver = {
420*4882a593Smuzhiyun .driver = {
421*4882a593Smuzhiyun .name = "ad5761",
422*4882a593Smuzhiyun },
423*4882a593Smuzhiyun .probe = ad5761_probe,
424*4882a593Smuzhiyun .remove = ad5761_remove,
425*4882a593Smuzhiyun .id_table = ad5761_id,
426*4882a593Smuzhiyun };
427*4882a593Smuzhiyun module_spi_driver(ad5761_driver);
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun MODULE_AUTHOR("Ricardo Ribalda <ribalda@kernel.org>");
430*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices AD5721, AD5721R, AD5761, AD5761R driver");
431*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
432