1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * This file is part of AD5686 DAC driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2018 Analog Devices Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __DRIVERS_IIO_DAC_AD5686_H__ 9*4882a593Smuzhiyun #define __DRIVERS_IIO_DAC_AD5686_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/types.h> 12*4882a593Smuzhiyun #include <linux/cache.h> 13*4882a593Smuzhiyun #include <linux/mutex.h> 14*4882a593Smuzhiyun #include <linux/kernel.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define AD5310_CMD(x) ((x) << 12) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define AD5683_DATA(x) ((x) << 4) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define AD5686_ADDR(x) ((x) << 16) 21*4882a593Smuzhiyun #define AD5686_CMD(x) ((x) << 20) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define AD5686_ADDR_DAC(chan) (0x1 << (chan)) 24*4882a593Smuzhiyun #define AD5686_ADDR_ALL_DAC 0xF 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define AD5686_CMD_NOOP 0x0 27*4882a593Smuzhiyun #define AD5686_CMD_WRITE_INPUT_N 0x1 28*4882a593Smuzhiyun #define AD5686_CMD_UPDATE_DAC_N 0x2 29*4882a593Smuzhiyun #define AD5686_CMD_WRITE_INPUT_N_UPDATE_N 0x3 30*4882a593Smuzhiyun #define AD5686_CMD_POWERDOWN_DAC 0x4 31*4882a593Smuzhiyun #define AD5686_CMD_LDAC_MASK 0x5 32*4882a593Smuzhiyun #define AD5686_CMD_RESET 0x6 33*4882a593Smuzhiyun #define AD5686_CMD_INTERNAL_REFER_SETUP 0x7 34*4882a593Smuzhiyun #define AD5686_CMD_DAISY_CHAIN_ENABLE 0x8 35*4882a593Smuzhiyun #define AD5686_CMD_READBACK_ENABLE 0x9 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define AD5686_LDAC_PWRDN_NONE 0x0 38*4882a593Smuzhiyun #define AD5686_LDAC_PWRDN_1K 0x1 39*4882a593Smuzhiyun #define AD5686_LDAC_PWRDN_100K 0x2 40*4882a593Smuzhiyun #define AD5686_LDAC_PWRDN_3STATE 0x3 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define AD5686_CMD_CONTROL_REG 0x4 43*4882a593Smuzhiyun #define AD5686_CMD_READBACK_ENABLE_V2 0x5 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define AD5310_REF_BIT_MSK BIT(8) 46*4882a593Smuzhiyun #define AD5683_REF_BIT_MSK BIT(12) 47*4882a593Smuzhiyun #define AD5693_REF_BIT_MSK BIT(12) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /** 50*4882a593Smuzhiyun * ad5686_supported_device_ids: 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun enum ad5686_supported_device_ids { 53*4882a593Smuzhiyun ID_AD5310R, 54*4882a593Smuzhiyun ID_AD5311R, 55*4882a593Smuzhiyun ID_AD5671R, 56*4882a593Smuzhiyun ID_AD5672R, 57*4882a593Smuzhiyun ID_AD5674R, 58*4882a593Smuzhiyun ID_AD5675R, 59*4882a593Smuzhiyun ID_AD5676, 60*4882a593Smuzhiyun ID_AD5676R, 61*4882a593Smuzhiyun ID_AD5679R, 62*4882a593Smuzhiyun ID_AD5681R, 63*4882a593Smuzhiyun ID_AD5682R, 64*4882a593Smuzhiyun ID_AD5683, 65*4882a593Smuzhiyun ID_AD5683R, 66*4882a593Smuzhiyun ID_AD5684, 67*4882a593Smuzhiyun ID_AD5684R, 68*4882a593Smuzhiyun ID_AD5685R, 69*4882a593Smuzhiyun ID_AD5686, 70*4882a593Smuzhiyun ID_AD5686R, 71*4882a593Smuzhiyun ID_AD5691R, 72*4882a593Smuzhiyun ID_AD5692R, 73*4882a593Smuzhiyun ID_AD5693, 74*4882a593Smuzhiyun ID_AD5693R, 75*4882a593Smuzhiyun ID_AD5694, 76*4882a593Smuzhiyun ID_AD5694R, 77*4882a593Smuzhiyun ID_AD5695R, 78*4882a593Smuzhiyun ID_AD5696, 79*4882a593Smuzhiyun ID_AD5696R, 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun enum ad5686_regmap_type { 83*4882a593Smuzhiyun AD5310_REGMAP, 84*4882a593Smuzhiyun AD5683_REGMAP, 85*4882a593Smuzhiyun AD5686_REGMAP, 86*4882a593Smuzhiyun AD5693_REGMAP 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun struct ad5686_state; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun typedef int (*ad5686_write_func)(struct ad5686_state *st, 92*4882a593Smuzhiyun u8 cmd, u8 addr, u16 val); 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun typedef int (*ad5686_read_func)(struct ad5686_state *st, u8 addr); 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /** 97*4882a593Smuzhiyun * struct ad5686_chip_info - chip specific information 98*4882a593Smuzhiyun * @int_vref_mv: AD5620/40/60: the internal reference voltage 99*4882a593Smuzhiyun * @num_channels: number of channels 100*4882a593Smuzhiyun * @channel: channel specification 101*4882a593Smuzhiyun * @regmap_type: register map layout variant 102*4882a593Smuzhiyun */ 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun struct ad5686_chip_info { 105*4882a593Smuzhiyun u16 int_vref_mv; 106*4882a593Smuzhiyun unsigned int num_channels; 107*4882a593Smuzhiyun const struct iio_chan_spec *channels; 108*4882a593Smuzhiyun enum ad5686_regmap_type regmap_type; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /** 112*4882a593Smuzhiyun * struct ad5446_state - driver instance specific data 113*4882a593Smuzhiyun * @spi: spi_device 114*4882a593Smuzhiyun * @chip_info: chip model specific constants, available modes etc 115*4882a593Smuzhiyun * @reg: supply regulator 116*4882a593Smuzhiyun * @vref_mv: actual reference voltage used 117*4882a593Smuzhiyun * @pwr_down_mask: power down mask 118*4882a593Smuzhiyun * @pwr_down_mode: current power down mode 119*4882a593Smuzhiyun * @use_internal_vref: set to true if the internal reference voltage is used 120*4882a593Smuzhiyun * @lock lock to protect the data buffer during regmap ops 121*4882a593Smuzhiyun * @data: spi transfer buffers 122*4882a593Smuzhiyun */ 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun struct ad5686_state { 125*4882a593Smuzhiyun struct device *dev; 126*4882a593Smuzhiyun const struct ad5686_chip_info *chip_info; 127*4882a593Smuzhiyun struct regulator *reg; 128*4882a593Smuzhiyun unsigned short vref_mv; 129*4882a593Smuzhiyun unsigned int pwr_down_mask; 130*4882a593Smuzhiyun unsigned int pwr_down_mode; 131*4882a593Smuzhiyun ad5686_write_func write; 132*4882a593Smuzhiyun ad5686_read_func read; 133*4882a593Smuzhiyun bool use_internal_vref; 134*4882a593Smuzhiyun struct mutex lock; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* 137*4882a593Smuzhiyun * DMA (thus cache coherency maintenance) requires the 138*4882a593Smuzhiyun * transfer buffers to live in their own cache lines. 139*4882a593Smuzhiyun */ 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun union { 142*4882a593Smuzhiyun __be32 d32; 143*4882a593Smuzhiyun __be16 d16; 144*4882a593Smuzhiyun u8 d8[4]; 145*4882a593Smuzhiyun } data[3] ____cacheline_aligned; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun int ad5686_probe(struct device *dev, 150*4882a593Smuzhiyun enum ad5686_supported_device_ids chip_type, 151*4882a593Smuzhiyun const char *name, ad5686_write_func write, 152*4882a593Smuzhiyun ad5686_read_func read); 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun int ad5686_remove(struct device *dev); 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #endif /* __DRIVERS_IIO_DAC_AD5686_H__ */ 158