1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * AD5624R, AD5644R, AD5664R Digital to analog convertors spi driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2010-2011 Analog Devices Inc.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/interrupt.h>
9*4882a593Smuzhiyun #include <linux/fs.h>
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/spi/spi.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/sysfs.h>
15*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <linux/iio/iio.h>
19*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <asm/unaligned.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include "ad5624r.h"
24*4882a593Smuzhiyun
ad5624r_spi_write(struct spi_device * spi,u8 cmd,u8 addr,u16 val,u8 shift)25*4882a593Smuzhiyun static int ad5624r_spi_write(struct spi_device *spi,
26*4882a593Smuzhiyun u8 cmd, u8 addr, u16 val, u8 shift)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun u32 data;
29*4882a593Smuzhiyun u8 msg[3];
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /*
32*4882a593Smuzhiyun * The input shift register is 24 bits wide. The first two bits are
33*4882a593Smuzhiyun * don't care bits. The next three are the command bits, C2 to C0,
34*4882a593Smuzhiyun * followed by the 3-bit DAC address, A2 to A0, and then the
35*4882a593Smuzhiyun * 16-, 14-, 12-bit data-word. The data-word comprises the 16-,
36*4882a593Smuzhiyun * 14-, 12-bit input code followed by 0, 2, or 4 don't care bits,
37*4882a593Smuzhiyun * for the AD5664R, AD5644R, and AD5624R, respectively.
38*4882a593Smuzhiyun */
39*4882a593Smuzhiyun data = (0 << 22) | (cmd << 19) | (addr << 16) | (val << shift);
40*4882a593Smuzhiyun put_unaligned_be24(data, &msg[0]);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return spi_write(spi, msg, sizeof(msg));
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
ad5624r_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)45*4882a593Smuzhiyun static int ad5624r_read_raw(struct iio_dev *indio_dev,
46*4882a593Smuzhiyun struct iio_chan_spec const *chan,
47*4882a593Smuzhiyun int *val,
48*4882a593Smuzhiyun int *val2,
49*4882a593Smuzhiyun long m)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun struct ad5624r_state *st = iio_priv(indio_dev);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun switch (m) {
54*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
55*4882a593Smuzhiyun *val = st->vref_mv;
56*4882a593Smuzhiyun *val2 = chan->scan_type.realbits;
57*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL_LOG2;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun return -EINVAL;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
ad5624r_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)62*4882a593Smuzhiyun static int ad5624r_write_raw(struct iio_dev *indio_dev,
63*4882a593Smuzhiyun struct iio_chan_spec const *chan,
64*4882a593Smuzhiyun int val,
65*4882a593Smuzhiyun int val2,
66*4882a593Smuzhiyun long mask)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct ad5624r_state *st = iio_priv(indio_dev);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun switch (mask) {
71*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
72*4882a593Smuzhiyun if (val >= (1 << chan->scan_type.realbits) || val < 0)
73*4882a593Smuzhiyun return -EINVAL;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun return ad5624r_spi_write(st->us,
76*4882a593Smuzhiyun AD5624R_CMD_WRITE_INPUT_N_UPDATE_N,
77*4882a593Smuzhiyun chan->address, val,
78*4882a593Smuzhiyun chan->scan_type.shift);
79*4882a593Smuzhiyun default:
80*4882a593Smuzhiyun return -EINVAL;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun static const char * const ad5624r_powerdown_modes[] = {
85*4882a593Smuzhiyun "1kohm_to_gnd",
86*4882a593Smuzhiyun "100kohm_to_gnd",
87*4882a593Smuzhiyun "three_state"
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
ad5624r_get_powerdown_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)90*4882a593Smuzhiyun static int ad5624r_get_powerdown_mode(struct iio_dev *indio_dev,
91*4882a593Smuzhiyun const struct iio_chan_spec *chan)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun struct ad5624r_state *st = iio_priv(indio_dev);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun return st->pwr_down_mode;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
ad5624r_set_powerdown_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)98*4882a593Smuzhiyun static int ad5624r_set_powerdown_mode(struct iio_dev *indio_dev,
99*4882a593Smuzhiyun const struct iio_chan_spec *chan, unsigned int mode)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun struct ad5624r_state *st = iio_priv(indio_dev);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun st->pwr_down_mode = mode;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun return 0;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun static const struct iio_enum ad5624r_powerdown_mode_enum = {
109*4882a593Smuzhiyun .items = ad5624r_powerdown_modes,
110*4882a593Smuzhiyun .num_items = ARRAY_SIZE(ad5624r_powerdown_modes),
111*4882a593Smuzhiyun .get = ad5624r_get_powerdown_mode,
112*4882a593Smuzhiyun .set = ad5624r_set_powerdown_mode,
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun
ad5624r_read_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)115*4882a593Smuzhiyun static ssize_t ad5624r_read_dac_powerdown(struct iio_dev *indio_dev,
116*4882a593Smuzhiyun uintptr_t private, const struct iio_chan_spec *chan, char *buf)
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun struct ad5624r_state *st = iio_priv(indio_dev);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun return sprintf(buf, "%d\n",
121*4882a593Smuzhiyun !!(st->pwr_down_mask & (1 << chan->channel)));
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
ad5624r_write_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)124*4882a593Smuzhiyun static ssize_t ad5624r_write_dac_powerdown(struct iio_dev *indio_dev,
125*4882a593Smuzhiyun uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
126*4882a593Smuzhiyun size_t len)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun bool pwr_down;
129*4882a593Smuzhiyun int ret;
130*4882a593Smuzhiyun struct ad5624r_state *st = iio_priv(indio_dev);
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun ret = strtobool(buf, &pwr_down);
133*4882a593Smuzhiyun if (ret)
134*4882a593Smuzhiyun return ret;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun if (pwr_down)
137*4882a593Smuzhiyun st->pwr_down_mask |= (1 << chan->channel);
138*4882a593Smuzhiyun else
139*4882a593Smuzhiyun st->pwr_down_mask &= ~(1 << chan->channel);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun ret = ad5624r_spi_write(st->us, AD5624R_CMD_POWERDOWN_DAC, 0,
142*4882a593Smuzhiyun (st->pwr_down_mode << 4) |
143*4882a593Smuzhiyun st->pwr_down_mask, 16);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun return ret ? ret : len;
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun static const struct iio_info ad5624r_info = {
149*4882a593Smuzhiyun .write_raw = ad5624r_write_raw,
150*4882a593Smuzhiyun .read_raw = ad5624r_read_raw,
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun static const struct iio_chan_spec_ext_info ad5624r_ext_info[] = {
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun .name = "powerdown",
156*4882a593Smuzhiyun .read = ad5624r_read_dac_powerdown,
157*4882a593Smuzhiyun .write = ad5624r_write_dac_powerdown,
158*4882a593Smuzhiyun .shared = IIO_SEPARATE,
159*4882a593Smuzhiyun },
160*4882a593Smuzhiyun IIO_ENUM("powerdown_mode", IIO_SHARED_BY_TYPE,
161*4882a593Smuzhiyun &ad5624r_powerdown_mode_enum),
162*4882a593Smuzhiyun IIO_ENUM_AVAILABLE("powerdown_mode", &ad5624r_powerdown_mode_enum),
163*4882a593Smuzhiyun { },
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun #define AD5624R_CHANNEL(_chan, _bits) { \
167*4882a593Smuzhiyun .type = IIO_VOLTAGE, \
168*4882a593Smuzhiyun .indexed = 1, \
169*4882a593Smuzhiyun .output = 1, \
170*4882a593Smuzhiyun .channel = (_chan), \
171*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
172*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
173*4882a593Smuzhiyun .address = (_chan), \
174*4882a593Smuzhiyun .scan_type = { \
175*4882a593Smuzhiyun .sign = 'u', \
176*4882a593Smuzhiyun .realbits = (_bits), \
177*4882a593Smuzhiyun .storagebits = 16, \
178*4882a593Smuzhiyun .shift = 16 - (_bits), \
179*4882a593Smuzhiyun }, \
180*4882a593Smuzhiyun .ext_info = ad5624r_ext_info, \
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun #define DECLARE_AD5624R_CHANNELS(_name, _bits) \
184*4882a593Smuzhiyun const struct iio_chan_spec _name##_channels[] = { \
185*4882a593Smuzhiyun AD5624R_CHANNEL(0, _bits), \
186*4882a593Smuzhiyun AD5624R_CHANNEL(1, _bits), \
187*4882a593Smuzhiyun AD5624R_CHANNEL(2, _bits), \
188*4882a593Smuzhiyun AD5624R_CHANNEL(3, _bits), \
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun static DECLARE_AD5624R_CHANNELS(ad5624r, 12);
192*4882a593Smuzhiyun static DECLARE_AD5624R_CHANNELS(ad5644r, 14);
193*4882a593Smuzhiyun static DECLARE_AD5624R_CHANNELS(ad5664r, 16);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun static const struct ad5624r_chip_info ad5624r_chip_info_tbl[] = {
196*4882a593Smuzhiyun [ID_AD5624R3] = {
197*4882a593Smuzhiyun .channels = ad5624r_channels,
198*4882a593Smuzhiyun .int_vref_mv = 1250,
199*4882a593Smuzhiyun },
200*4882a593Smuzhiyun [ID_AD5624R5] = {
201*4882a593Smuzhiyun .channels = ad5624r_channels,
202*4882a593Smuzhiyun .int_vref_mv = 2500,
203*4882a593Smuzhiyun },
204*4882a593Smuzhiyun [ID_AD5644R3] = {
205*4882a593Smuzhiyun .channels = ad5644r_channels,
206*4882a593Smuzhiyun .int_vref_mv = 1250,
207*4882a593Smuzhiyun },
208*4882a593Smuzhiyun [ID_AD5644R5] = {
209*4882a593Smuzhiyun .channels = ad5644r_channels,
210*4882a593Smuzhiyun .int_vref_mv = 2500,
211*4882a593Smuzhiyun },
212*4882a593Smuzhiyun [ID_AD5664R3] = {
213*4882a593Smuzhiyun .channels = ad5664r_channels,
214*4882a593Smuzhiyun .int_vref_mv = 1250,
215*4882a593Smuzhiyun },
216*4882a593Smuzhiyun [ID_AD5664R5] = {
217*4882a593Smuzhiyun .channels = ad5664r_channels,
218*4882a593Smuzhiyun .int_vref_mv = 2500,
219*4882a593Smuzhiyun },
220*4882a593Smuzhiyun };
221*4882a593Smuzhiyun
ad5624r_probe(struct spi_device * spi)222*4882a593Smuzhiyun static int ad5624r_probe(struct spi_device *spi)
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun struct ad5624r_state *st;
225*4882a593Smuzhiyun struct iio_dev *indio_dev;
226*4882a593Smuzhiyun int ret, voltage_uv = 0;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
229*4882a593Smuzhiyun if (!indio_dev)
230*4882a593Smuzhiyun return -ENOMEM;
231*4882a593Smuzhiyun st = iio_priv(indio_dev);
232*4882a593Smuzhiyun st->reg = devm_regulator_get_optional(&spi->dev, "vref");
233*4882a593Smuzhiyun if (!IS_ERR(st->reg)) {
234*4882a593Smuzhiyun ret = regulator_enable(st->reg);
235*4882a593Smuzhiyun if (ret)
236*4882a593Smuzhiyun return ret;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun ret = regulator_get_voltage(st->reg);
239*4882a593Smuzhiyun if (ret < 0)
240*4882a593Smuzhiyun goto error_disable_reg;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun voltage_uv = ret;
243*4882a593Smuzhiyun } else {
244*4882a593Smuzhiyun if (PTR_ERR(st->reg) != -ENODEV)
245*4882a593Smuzhiyun return PTR_ERR(st->reg);
246*4882a593Smuzhiyun /* Backwards compatibility. This naming is not correct */
247*4882a593Smuzhiyun st->reg = devm_regulator_get_optional(&spi->dev, "vcc");
248*4882a593Smuzhiyun if (!IS_ERR(st->reg)) {
249*4882a593Smuzhiyun ret = regulator_enable(st->reg);
250*4882a593Smuzhiyun if (ret)
251*4882a593Smuzhiyun return ret;
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun ret = regulator_get_voltage(st->reg);
254*4882a593Smuzhiyun if (ret < 0)
255*4882a593Smuzhiyun goto error_disable_reg;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun voltage_uv = ret;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun spi_set_drvdata(spi, indio_dev);
262*4882a593Smuzhiyun st->chip_info =
263*4882a593Smuzhiyun &ad5624r_chip_info_tbl[spi_get_device_id(spi)->driver_data];
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun if (voltage_uv)
266*4882a593Smuzhiyun st->vref_mv = voltage_uv / 1000;
267*4882a593Smuzhiyun else
268*4882a593Smuzhiyun st->vref_mv = st->chip_info->int_vref_mv;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun st->us = spi;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun indio_dev->name = spi_get_device_id(spi)->name;
273*4882a593Smuzhiyun indio_dev->info = &ad5624r_info;
274*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
275*4882a593Smuzhiyun indio_dev->channels = st->chip_info->channels;
276*4882a593Smuzhiyun indio_dev->num_channels = AD5624R_DAC_CHANNELS;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun ret = ad5624r_spi_write(spi, AD5624R_CMD_INTERNAL_REFER_SETUP, 0,
279*4882a593Smuzhiyun !!voltage_uv, 16);
280*4882a593Smuzhiyun if (ret)
281*4882a593Smuzhiyun goto error_disable_reg;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
284*4882a593Smuzhiyun if (ret)
285*4882a593Smuzhiyun goto error_disable_reg;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun return 0;
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun error_disable_reg:
290*4882a593Smuzhiyun if (!IS_ERR(st->reg))
291*4882a593Smuzhiyun regulator_disable(st->reg);
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun return ret;
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
ad5624r_remove(struct spi_device * spi)296*4882a593Smuzhiyun static int ad5624r_remove(struct spi_device *spi)
297*4882a593Smuzhiyun {
298*4882a593Smuzhiyun struct iio_dev *indio_dev = spi_get_drvdata(spi);
299*4882a593Smuzhiyun struct ad5624r_state *st = iio_priv(indio_dev);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun iio_device_unregister(indio_dev);
302*4882a593Smuzhiyun if (!IS_ERR(st->reg))
303*4882a593Smuzhiyun regulator_disable(st->reg);
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun return 0;
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun static const struct spi_device_id ad5624r_id[] = {
309*4882a593Smuzhiyun {"ad5624r3", ID_AD5624R3},
310*4882a593Smuzhiyun {"ad5644r3", ID_AD5644R3},
311*4882a593Smuzhiyun {"ad5664r3", ID_AD5664R3},
312*4882a593Smuzhiyun {"ad5624r5", ID_AD5624R5},
313*4882a593Smuzhiyun {"ad5644r5", ID_AD5644R5},
314*4882a593Smuzhiyun {"ad5664r5", ID_AD5664R5},
315*4882a593Smuzhiyun {}
316*4882a593Smuzhiyun };
317*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ad5624r_id);
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun static struct spi_driver ad5624r_driver = {
320*4882a593Smuzhiyun .driver = {
321*4882a593Smuzhiyun .name = "ad5624r",
322*4882a593Smuzhiyun },
323*4882a593Smuzhiyun .probe = ad5624r_probe,
324*4882a593Smuzhiyun .remove = ad5624r_remove,
325*4882a593Smuzhiyun .id_table = ad5624r_id,
326*4882a593Smuzhiyun };
327*4882a593Smuzhiyun module_spi_driver(ad5624r_driver);
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
330*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices AD5624/44/64R DAC spi driver");
331*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
332