1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * AD5624R SPI DAC driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2010-2011 Analog Devices Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef SPI_AD5624R_H_ 8*4882a593Smuzhiyun #define SPI_AD5624R_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define AD5624R_DAC_CHANNELS 4 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define AD5624R_ADDR_DAC0 0x0 13*4882a593Smuzhiyun #define AD5624R_ADDR_DAC1 0x1 14*4882a593Smuzhiyun #define AD5624R_ADDR_DAC2 0x2 15*4882a593Smuzhiyun #define AD5624R_ADDR_DAC3 0x3 16*4882a593Smuzhiyun #define AD5624R_ADDR_ALL_DAC 0x7 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define AD5624R_CMD_WRITE_INPUT_N 0x0 19*4882a593Smuzhiyun #define AD5624R_CMD_UPDATE_DAC_N 0x1 20*4882a593Smuzhiyun #define AD5624R_CMD_WRITE_INPUT_N_UPDATE_ALL 0x2 21*4882a593Smuzhiyun #define AD5624R_CMD_WRITE_INPUT_N_UPDATE_N 0x3 22*4882a593Smuzhiyun #define AD5624R_CMD_POWERDOWN_DAC 0x4 23*4882a593Smuzhiyun #define AD5624R_CMD_RESET 0x5 24*4882a593Smuzhiyun #define AD5624R_CMD_LDAC_SETUP 0x6 25*4882a593Smuzhiyun #define AD5624R_CMD_INTERNAL_REFER_SETUP 0x7 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define AD5624R_LDAC_PWRDN_NONE 0x0 28*4882a593Smuzhiyun #define AD5624R_LDAC_PWRDN_1K 0x1 29*4882a593Smuzhiyun #define AD5624R_LDAC_PWRDN_100K 0x2 30*4882a593Smuzhiyun #define AD5624R_LDAC_PWRDN_3STATE 0x3 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /** 33*4882a593Smuzhiyun * struct ad5624r_chip_info - chip specific information 34*4882a593Smuzhiyun * @channels: channel spec for the DAC 35*4882a593Smuzhiyun * @int_vref_mv: AD5620/40/60: the internal reference voltage 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun struct ad5624r_chip_info { 39*4882a593Smuzhiyun const struct iio_chan_spec *channels; 40*4882a593Smuzhiyun u16 int_vref_mv; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /** 44*4882a593Smuzhiyun * struct ad5446_state - driver instance specific data 45*4882a593Smuzhiyun * @indio_dev: the industrial I/O device 46*4882a593Smuzhiyun * @us: spi_device 47*4882a593Smuzhiyun * @chip_info: chip model specific constants, available modes etc 48*4882a593Smuzhiyun * @reg: supply regulator 49*4882a593Smuzhiyun * @vref_mv: actual reference voltage used 50*4882a593Smuzhiyun * @pwr_down_mask power down mask 51*4882a593Smuzhiyun * @pwr_down_mode current power down mode 52*4882a593Smuzhiyun */ 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun struct ad5624r_state { 55*4882a593Smuzhiyun struct spi_device *us; 56*4882a593Smuzhiyun const struct ad5624r_chip_info *chip_info; 57*4882a593Smuzhiyun struct regulator *reg; 58*4882a593Smuzhiyun unsigned short vref_mv; 59*4882a593Smuzhiyun unsigned pwr_down_mask; 60*4882a593Smuzhiyun unsigned pwr_down_mode; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /** 64*4882a593Smuzhiyun * ad5624r_supported_device_ids: 65*4882a593Smuzhiyun * The AD5624/44/64 parts are available in different 66*4882a593Smuzhiyun * fixed internal reference voltage options. 67*4882a593Smuzhiyun */ 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun enum ad5624r_supported_device_ids { 70*4882a593Smuzhiyun ID_AD5624R3, 71*4882a593Smuzhiyun ID_AD5644R3, 72*4882a593Smuzhiyun ID_AD5664R3, 73*4882a593Smuzhiyun ID_AD5624R5, 74*4882a593Smuzhiyun ID_AD5644R5, 75*4882a593Smuzhiyun ID_AD5664R5, 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #endif /* SPI_AD5624R_H_ */ 79