1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * AD5592R / AD5593R Digital <-> Analog converters driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2015-2016 Analog Devices Inc. 6*4882a593Smuzhiyun * Author: Paul Cercueil <paul.cercueil@analog.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __DRIVERS_IIO_DAC_AD5592R_BASE_H__ 10*4882a593Smuzhiyun #define __DRIVERS_IIO_DAC_AD5592R_BASE_H__ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/types.h> 13*4882a593Smuzhiyun #include <linux/cache.h> 14*4882a593Smuzhiyun #include <linux/mutex.h> 15*4882a593Smuzhiyun #include <linux/gpio/driver.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun struct device; 18*4882a593Smuzhiyun struct ad5592r_state; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun enum ad5592r_registers { 21*4882a593Smuzhiyun AD5592R_REG_NOOP = 0x0, 22*4882a593Smuzhiyun AD5592R_REG_DAC_READBACK = 0x1, 23*4882a593Smuzhiyun AD5592R_REG_ADC_SEQ = 0x2, 24*4882a593Smuzhiyun AD5592R_REG_CTRL = 0x3, 25*4882a593Smuzhiyun AD5592R_REG_ADC_EN = 0x4, 26*4882a593Smuzhiyun AD5592R_REG_DAC_EN = 0x5, 27*4882a593Smuzhiyun AD5592R_REG_PULLDOWN = 0x6, 28*4882a593Smuzhiyun AD5592R_REG_LDAC = 0x7, 29*4882a593Smuzhiyun AD5592R_REG_GPIO_OUT_EN = 0x8, 30*4882a593Smuzhiyun AD5592R_REG_GPIO_SET = 0x9, 31*4882a593Smuzhiyun AD5592R_REG_GPIO_IN_EN = 0xA, 32*4882a593Smuzhiyun AD5592R_REG_PD = 0xB, 33*4882a593Smuzhiyun AD5592R_REG_OPEN_DRAIN = 0xC, 34*4882a593Smuzhiyun AD5592R_REG_TRISTATE = 0xD, 35*4882a593Smuzhiyun AD5592R_REG_RESET = 0xF, 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define AD5592R_REG_PD_EN_REF BIT(9) 39*4882a593Smuzhiyun #define AD5592R_REG_CTRL_ADC_RANGE BIT(5) 40*4882a593Smuzhiyun #define AD5592R_REG_CTRL_DAC_RANGE BIT(4) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct ad5592r_rw_ops { 43*4882a593Smuzhiyun int (*write_dac)(struct ad5592r_state *st, unsigned chan, u16 value); 44*4882a593Smuzhiyun int (*read_adc)(struct ad5592r_state *st, unsigned chan, u16 *value); 45*4882a593Smuzhiyun int (*reg_write)(struct ad5592r_state *st, u8 reg, u16 value); 46*4882a593Smuzhiyun int (*reg_read)(struct ad5592r_state *st, u8 reg, u16 *value); 47*4882a593Smuzhiyun int (*gpio_read)(struct ad5592r_state *st, u8 *value); 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun struct ad5592r_state { 51*4882a593Smuzhiyun struct device *dev; 52*4882a593Smuzhiyun struct regulator *reg; 53*4882a593Smuzhiyun struct gpio_chip gpiochip; 54*4882a593Smuzhiyun struct mutex gpio_lock; /* Protect cached gpio_out, gpio_val, etc. */ 55*4882a593Smuzhiyun struct mutex lock; 56*4882a593Smuzhiyun unsigned int num_channels; 57*4882a593Smuzhiyun const struct ad5592r_rw_ops *ops; 58*4882a593Smuzhiyun int scale_avail[2][2]; 59*4882a593Smuzhiyun u16 cached_dac[8]; 60*4882a593Smuzhiyun u16 cached_gp_ctrl; 61*4882a593Smuzhiyun u8 channel_modes[8]; 62*4882a593Smuzhiyun u8 channel_offstate[8]; 63*4882a593Smuzhiyun u8 gpio_map; 64*4882a593Smuzhiyun u8 gpio_out; 65*4882a593Smuzhiyun u8 gpio_in; 66*4882a593Smuzhiyun u8 gpio_val; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun __be16 spi_msg ____cacheline_aligned; 69*4882a593Smuzhiyun __be16 spi_msg_nop; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun int ad5592r_probe(struct device *dev, const char *name, 73*4882a593Smuzhiyun const struct ad5592r_rw_ops *ops); 74*4882a593Smuzhiyun int ad5592r_remove(struct device *dev); 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif /* __DRIVERS_IIO_DAC_AD5592R_BASE_H__ */ 77