1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * AD5504, AD5501 High Voltage Digital to Analog Converter
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2011 Analog Devices Inc.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/interrupt.h>
9*4882a593Smuzhiyun #include <linux/fs.h>
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/spi/spi.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/sysfs.h>
15*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/bitops.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <linux/iio/iio.h>
20*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
21*4882a593Smuzhiyun #include <linux/iio/events.h>
22*4882a593Smuzhiyun #include <linux/iio/dac/ad5504.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define AD5504_RES_MASK GENMASK(11, 0)
25*4882a593Smuzhiyun #define AD5504_CMD_READ BIT(15)
26*4882a593Smuzhiyun #define AD5504_CMD_WRITE 0
27*4882a593Smuzhiyun #define AD5504_ADDR(addr) ((addr) << 12)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* Registers */
30*4882a593Smuzhiyun #define AD5504_ADDR_NOOP 0
31*4882a593Smuzhiyun #define AD5504_ADDR_DAC(x) ((x) + 1)
32*4882a593Smuzhiyun #define AD5504_ADDR_ALL_DAC 5
33*4882a593Smuzhiyun #define AD5504_ADDR_CTRL 7
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Control Register */
36*4882a593Smuzhiyun #define AD5504_DAC_PWR(ch) ((ch) << 2)
37*4882a593Smuzhiyun #define AD5504_DAC_PWRDWN_MODE(mode) ((mode) << 6)
38*4882a593Smuzhiyun #define AD5504_DAC_PWRDN_20K 0
39*4882a593Smuzhiyun #define AD5504_DAC_PWRDN_3STATE 1
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /**
42*4882a593Smuzhiyun * struct ad5446_state - driver instance specific data
43*4882a593Smuzhiyun * @spi: spi_device
44*4882a593Smuzhiyun * @reg: supply regulator
45*4882a593Smuzhiyun * @vref_mv: actual reference voltage used
46*4882a593Smuzhiyun * @pwr_down_mask: power down mask
47*4882a593Smuzhiyun * @pwr_down_mode: current power down mode
48*4882a593Smuzhiyun * @data: transfer buffer
49*4882a593Smuzhiyun */
50*4882a593Smuzhiyun struct ad5504_state {
51*4882a593Smuzhiyun struct spi_device *spi;
52*4882a593Smuzhiyun struct regulator *reg;
53*4882a593Smuzhiyun unsigned short vref_mv;
54*4882a593Smuzhiyun unsigned pwr_down_mask;
55*4882a593Smuzhiyun unsigned pwr_down_mode;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun __be16 data[2] ____cacheline_aligned;
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun * ad5504_supported_device_ids:
62*4882a593Smuzhiyun */
63*4882a593Smuzhiyun enum ad5504_supported_device_ids {
64*4882a593Smuzhiyun ID_AD5504,
65*4882a593Smuzhiyun ID_AD5501,
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
ad5504_spi_write(struct ad5504_state * st,u8 addr,u16 val)68*4882a593Smuzhiyun static int ad5504_spi_write(struct ad5504_state *st, u8 addr, u16 val)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun st->data[0] = cpu_to_be16(AD5504_CMD_WRITE | AD5504_ADDR(addr) |
71*4882a593Smuzhiyun (val & AD5504_RES_MASK));
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return spi_write(st->spi, &st->data[0], 2);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
ad5504_spi_read(struct ad5504_state * st,u8 addr)76*4882a593Smuzhiyun static int ad5504_spi_read(struct ad5504_state *st, u8 addr)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun int ret;
79*4882a593Smuzhiyun struct spi_transfer t = {
80*4882a593Smuzhiyun .tx_buf = &st->data[0],
81*4882a593Smuzhiyun .rx_buf = &st->data[1],
82*4882a593Smuzhiyun .len = 2,
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun st->data[0] = cpu_to_be16(AD5504_CMD_READ | AD5504_ADDR(addr));
86*4882a593Smuzhiyun ret = spi_sync_transfer(st->spi, &t, 1);
87*4882a593Smuzhiyun if (ret < 0)
88*4882a593Smuzhiyun return ret;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun return be16_to_cpu(st->data[1]) & AD5504_RES_MASK;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
ad5504_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)93*4882a593Smuzhiyun static int ad5504_read_raw(struct iio_dev *indio_dev,
94*4882a593Smuzhiyun struct iio_chan_spec const *chan,
95*4882a593Smuzhiyun int *val,
96*4882a593Smuzhiyun int *val2,
97*4882a593Smuzhiyun long m)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun struct ad5504_state *st = iio_priv(indio_dev);
100*4882a593Smuzhiyun int ret;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun switch (m) {
103*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
104*4882a593Smuzhiyun ret = ad5504_spi_read(st, chan->address);
105*4882a593Smuzhiyun if (ret < 0)
106*4882a593Smuzhiyun return ret;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun *val = ret;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun return IIO_VAL_INT;
111*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
112*4882a593Smuzhiyun *val = st->vref_mv;
113*4882a593Smuzhiyun *val2 = chan->scan_type.realbits;
114*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL_LOG2;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun return -EINVAL;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
ad5504_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)119*4882a593Smuzhiyun static int ad5504_write_raw(struct iio_dev *indio_dev,
120*4882a593Smuzhiyun struct iio_chan_spec const *chan,
121*4882a593Smuzhiyun int val,
122*4882a593Smuzhiyun int val2,
123*4882a593Smuzhiyun long mask)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun struct ad5504_state *st = iio_priv(indio_dev);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun switch (mask) {
128*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
129*4882a593Smuzhiyun if (val >= (1 << chan->scan_type.realbits) || val < 0)
130*4882a593Smuzhiyun return -EINVAL;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun return ad5504_spi_write(st, chan->address, val);
133*4882a593Smuzhiyun default:
134*4882a593Smuzhiyun return -EINVAL;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun static const char * const ad5504_powerdown_modes[] = {
139*4882a593Smuzhiyun "20kohm_to_gnd",
140*4882a593Smuzhiyun "three_state",
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun
ad5504_get_powerdown_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)143*4882a593Smuzhiyun static int ad5504_get_powerdown_mode(struct iio_dev *indio_dev,
144*4882a593Smuzhiyun const struct iio_chan_spec *chan)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun struct ad5504_state *st = iio_priv(indio_dev);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun return st->pwr_down_mode;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
ad5504_set_powerdown_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)151*4882a593Smuzhiyun static int ad5504_set_powerdown_mode(struct iio_dev *indio_dev,
152*4882a593Smuzhiyun const struct iio_chan_spec *chan, unsigned int mode)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun struct ad5504_state *st = iio_priv(indio_dev);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun st->pwr_down_mode = mode;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun return 0;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun static const struct iio_enum ad5504_powerdown_mode_enum = {
162*4882a593Smuzhiyun .items = ad5504_powerdown_modes,
163*4882a593Smuzhiyun .num_items = ARRAY_SIZE(ad5504_powerdown_modes),
164*4882a593Smuzhiyun .get = ad5504_get_powerdown_mode,
165*4882a593Smuzhiyun .set = ad5504_set_powerdown_mode,
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun
ad5504_read_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)168*4882a593Smuzhiyun static ssize_t ad5504_read_dac_powerdown(struct iio_dev *indio_dev,
169*4882a593Smuzhiyun uintptr_t private, const struct iio_chan_spec *chan, char *buf)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun struct ad5504_state *st = iio_priv(indio_dev);
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun return sprintf(buf, "%d\n",
174*4882a593Smuzhiyun !(st->pwr_down_mask & (1 << chan->channel)));
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
ad5504_write_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)177*4882a593Smuzhiyun static ssize_t ad5504_write_dac_powerdown(struct iio_dev *indio_dev,
178*4882a593Smuzhiyun uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
179*4882a593Smuzhiyun size_t len)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun bool pwr_down;
182*4882a593Smuzhiyun int ret;
183*4882a593Smuzhiyun struct ad5504_state *st = iio_priv(indio_dev);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun ret = strtobool(buf, &pwr_down);
186*4882a593Smuzhiyun if (ret)
187*4882a593Smuzhiyun return ret;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun if (pwr_down)
190*4882a593Smuzhiyun st->pwr_down_mask &= ~(1 << chan->channel);
191*4882a593Smuzhiyun else
192*4882a593Smuzhiyun st->pwr_down_mask |= (1 << chan->channel);
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun ret = ad5504_spi_write(st, AD5504_ADDR_CTRL,
195*4882a593Smuzhiyun AD5504_DAC_PWRDWN_MODE(st->pwr_down_mode) |
196*4882a593Smuzhiyun AD5504_DAC_PWR(st->pwr_down_mask));
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun /* writes to the CTRL register must be followed by a NOOP */
199*4882a593Smuzhiyun ad5504_spi_write(st, AD5504_ADDR_NOOP, 0);
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun return ret ? ret : len;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun static IIO_CONST_ATTR(temp0_thresh_rising_value, "110000");
205*4882a593Smuzhiyun static IIO_CONST_ATTR(temp0_thresh_rising_en, "1");
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun static struct attribute *ad5504_ev_attributes[] = {
208*4882a593Smuzhiyun &iio_const_attr_temp0_thresh_rising_value.dev_attr.attr,
209*4882a593Smuzhiyun &iio_const_attr_temp0_thresh_rising_en.dev_attr.attr,
210*4882a593Smuzhiyun NULL,
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun static const struct attribute_group ad5504_ev_attribute_group = {
214*4882a593Smuzhiyun .attrs = ad5504_ev_attributes,
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun
ad5504_event_handler(int irq,void * private)217*4882a593Smuzhiyun static irqreturn_t ad5504_event_handler(int irq, void *private)
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun iio_push_event(private,
220*4882a593Smuzhiyun IIO_UNMOD_EVENT_CODE(IIO_TEMP,
221*4882a593Smuzhiyun 0,
222*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
223*4882a593Smuzhiyun IIO_EV_DIR_RISING),
224*4882a593Smuzhiyun iio_get_time_ns(private));
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun return IRQ_HANDLED;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun static const struct iio_info ad5504_info = {
230*4882a593Smuzhiyun .write_raw = ad5504_write_raw,
231*4882a593Smuzhiyun .read_raw = ad5504_read_raw,
232*4882a593Smuzhiyun .event_attrs = &ad5504_ev_attribute_group,
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun static const struct iio_chan_spec_ext_info ad5504_ext_info[] = {
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun .name = "powerdown",
238*4882a593Smuzhiyun .read = ad5504_read_dac_powerdown,
239*4882a593Smuzhiyun .write = ad5504_write_dac_powerdown,
240*4882a593Smuzhiyun .shared = IIO_SEPARATE,
241*4882a593Smuzhiyun },
242*4882a593Smuzhiyun IIO_ENUM("powerdown_mode", IIO_SHARED_BY_TYPE,
243*4882a593Smuzhiyun &ad5504_powerdown_mode_enum),
244*4882a593Smuzhiyun IIO_ENUM_AVAILABLE("powerdown_mode", &ad5504_powerdown_mode_enum),
245*4882a593Smuzhiyun { },
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun #define AD5504_CHANNEL(_chan) { \
249*4882a593Smuzhiyun .type = IIO_VOLTAGE, \
250*4882a593Smuzhiyun .indexed = 1, \
251*4882a593Smuzhiyun .output = 1, \
252*4882a593Smuzhiyun .channel = (_chan), \
253*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
254*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
255*4882a593Smuzhiyun .address = AD5504_ADDR_DAC(_chan), \
256*4882a593Smuzhiyun .scan_type = { \
257*4882a593Smuzhiyun .sign = 'u', \
258*4882a593Smuzhiyun .realbits = 12, \
259*4882a593Smuzhiyun .storagebits = 16, \
260*4882a593Smuzhiyun }, \
261*4882a593Smuzhiyun .ext_info = ad5504_ext_info, \
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun static const struct iio_chan_spec ad5504_channels[] = {
265*4882a593Smuzhiyun AD5504_CHANNEL(0),
266*4882a593Smuzhiyun AD5504_CHANNEL(1),
267*4882a593Smuzhiyun AD5504_CHANNEL(2),
268*4882a593Smuzhiyun AD5504_CHANNEL(3),
269*4882a593Smuzhiyun };
270*4882a593Smuzhiyun
ad5504_probe(struct spi_device * spi)271*4882a593Smuzhiyun static int ad5504_probe(struct spi_device *spi)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun struct ad5504_platform_data *pdata = spi->dev.platform_data;
274*4882a593Smuzhiyun struct iio_dev *indio_dev;
275*4882a593Smuzhiyun struct ad5504_state *st;
276*4882a593Smuzhiyun struct regulator *reg;
277*4882a593Smuzhiyun int ret, voltage_uv = 0;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
280*4882a593Smuzhiyun if (!indio_dev)
281*4882a593Smuzhiyun return -ENOMEM;
282*4882a593Smuzhiyun reg = devm_regulator_get(&spi->dev, "vcc");
283*4882a593Smuzhiyun if (!IS_ERR(reg)) {
284*4882a593Smuzhiyun ret = regulator_enable(reg);
285*4882a593Smuzhiyun if (ret)
286*4882a593Smuzhiyun return ret;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun ret = regulator_get_voltage(reg);
289*4882a593Smuzhiyun if (ret < 0)
290*4882a593Smuzhiyun goto error_disable_reg;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun voltage_uv = ret;
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun spi_set_drvdata(spi, indio_dev);
296*4882a593Smuzhiyun st = iio_priv(indio_dev);
297*4882a593Smuzhiyun if (voltage_uv)
298*4882a593Smuzhiyun st->vref_mv = voltage_uv / 1000;
299*4882a593Smuzhiyun else if (pdata)
300*4882a593Smuzhiyun st->vref_mv = pdata->vref_mv;
301*4882a593Smuzhiyun else
302*4882a593Smuzhiyun dev_warn(&spi->dev, "reference voltage unspecified\n");
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun st->reg = reg;
305*4882a593Smuzhiyun st->spi = spi;
306*4882a593Smuzhiyun indio_dev->name = spi_get_device_id(st->spi)->name;
307*4882a593Smuzhiyun indio_dev->info = &ad5504_info;
308*4882a593Smuzhiyun if (spi_get_device_id(st->spi)->driver_data == ID_AD5501)
309*4882a593Smuzhiyun indio_dev->num_channels = 1;
310*4882a593Smuzhiyun else
311*4882a593Smuzhiyun indio_dev->num_channels = 4;
312*4882a593Smuzhiyun indio_dev->channels = ad5504_channels;
313*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun if (spi->irq) {
316*4882a593Smuzhiyun ret = devm_request_threaded_irq(&spi->dev, spi->irq,
317*4882a593Smuzhiyun NULL,
318*4882a593Smuzhiyun &ad5504_event_handler,
319*4882a593Smuzhiyun IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
320*4882a593Smuzhiyun spi_get_device_id(st->spi)->name,
321*4882a593Smuzhiyun indio_dev);
322*4882a593Smuzhiyun if (ret)
323*4882a593Smuzhiyun goto error_disable_reg;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
327*4882a593Smuzhiyun if (ret)
328*4882a593Smuzhiyun goto error_disable_reg;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun return 0;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun error_disable_reg:
333*4882a593Smuzhiyun if (!IS_ERR(reg))
334*4882a593Smuzhiyun regulator_disable(reg);
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun return ret;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun
ad5504_remove(struct spi_device * spi)339*4882a593Smuzhiyun static int ad5504_remove(struct spi_device *spi)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun struct iio_dev *indio_dev = spi_get_drvdata(spi);
342*4882a593Smuzhiyun struct ad5504_state *st = iio_priv(indio_dev);
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun iio_device_unregister(indio_dev);
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun if (!IS_ERR(st->reg))
347*4882a593Smuzhiyun regulator_disable(st->reg);
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun return 0;
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun static const struct spi_device_id ad5504_id[] = {
353*4882a593Smuzhiyun {"ad5504", ID_AD5504},
354*4882a593Smuzhiyun {"ad5501", ID_AD5501},
355*4882a593Smuzhiyun {}
356*4882a593Smuzhiyun };
357*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ad5504_id);
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun static struct spi_driver ad5504_driver = {
360*4882a593Smuzhiyun .driver = {
361*4882a593Smuzhiyun .name = "ad5504",
362*4882a593Smuzhiyun },
363*4882a593Smuzhiyun .probe = ad5504_probe,
364*4882a593Smuzhiyun .remove = ad5504_remove,
365*4882a593Smuzhiyun .id_table = ad5504_id,
366*4882a593Smuzhiyun };
367*4882a593Smuzhiyun module_spi_driver(ad5504_driver);
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
370*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices AD5501/AD5501 DAC");
371*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
372