1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * AD5415, AD5426, AD5429, AD5432, AD5439, AD5443, AD5449 Digital to Analog
4*4882a593Smuzhiyun * Converter driver.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright 2012 Analog Devices Inc.
7*4882a593Smuzhiyun * Author: Lars-Peter Clausen <lars@metafoo.de>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/err.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/spi/spi.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/sysfs.h>
17*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
18*4882a593Smuzhiyun #include <asm/unaligned.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <linux/iio/iio.h>
21*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <linux/platform_data/ad5449.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define AD5449_MAX_CHANNELS 2
26*4882a593Smuzhiyun #define AD5449_MAX_VREFS 2
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define AD5449_CMD_NOOP 0x0
29*4882a593Smuzhiyun #define AD5449_CMD_LOAD_AND_UPDATE(x) (0x1 + (x) * 3)
30*4882a593Smuzhiyun #define AD5449_CMD_READ(x) (0x2 + (x) * 3)
31*4882a593Smuzhiyun #define AD5449_CMD_LOAD(x) (0x3 + (x) * 3)
32*4882a593Smuzhiyun #define AD5449_CMD_CTRL 13
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define AD5449_CTRL_SDO_OFFSET 10
35*4882a593Smuzhiyun #define AD5449_CTRL_DAISY_CHAIN BIT(9)
36*4882a593Smuzhiyun #define AD5449_CTRL_HCLR_TO_MIDSCALE BIT(8)
37*4882a593Smuzhiyun #define AD5449_CTRL_SAMPLE_RISING BIT(7)
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /**
40*4882a593Smuzhiyun * struct ad5449_chip_info - chip specific information
41*4882a593Smuzhiyun * @channels: Channel specification
42*4882a593Smuzhiyun * @num_channels: Number of channels
43*4882a593Smuzhiyun * @has_ctrl: Chip has a control register
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun struct ad5449_chip_info {
46*4882a593Smuzhiyun const struct iio_chan_spec *channels;
47*4882a593Smuzhiyun unsigned int num_channels;
48*4882a593Smuzhiyun bool has_ctrl;
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /**
52*4882a593Smuzhiyun * struct ad5449 - driver instance specific data
53*4882a593Smuzhiyun * @spi: the SPI device for this driver instance
54*4882a593Smuzhiyun * @chip_info: chip model specific constants, available modes etc
55*4882a593Smuzhiyun * @vref_reg: vref supply regulators
56*4882a593Smuzhiyun * @has_sdo: whether the SDO line is connected
57*4882a593Smuzhiyun * @dac_cache: Cache for the DAC values
58*4882a593Smuzhiyun * @data: spi transfer buffers
59*4882a593Smuzhiyun * @lock: lock to protect the data buffer during SPI ops
60*4882a593Smuzhiyun */
61*4882a593Smuzhiyun struct ad5449 {
62*4882a593Smuzhiyun struct spi_device *spi;
63*4882a593Smuzhiyun const struct ad5449_chip_info *chip_info;
64*4882a593Smuzhiyun struct regulator_bulk_data vref_reg[AD5449_MAX_VREFS];
65*4882a593Smuzhiyun struct mutex lock;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun bool has_sdo;
68*4882a593Smuzhiyun uint16_t dac_cache[AD5449_MAX_CHANNELS];
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun * DMA (thus cache coherency maintenance) requires the
72*4882a593Smuzhiyun * transfer buffers to live in their own cache lines.
73*4882a593Smuzhiyun */
74*4882a593Smuzhiyun __be16 data[2] ____cacheline_aligned;
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun enum ad5449_type {
78*4882a593Smuzhiyun ID_AD5426,
79*4882a593Smuzhiyun ID_AD5429,
80*4882a593Smuzhiyun ID_AD5432,
81*4882a593Smuzhiyun ID_AD5439,
82*4882a593Smuzhiyun ID_AD5443,
83*4882a593Smuzhiyun ID_AD5449,
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
ad5449_write(struct iio_dev * indio_dev,unsigned int addr,unsigned int val)86*4882a593Smuzhiyun static int ad5449_write(struct iio_dev *indio_dev, unsigned int addr,
87*4882a593Smuzhiyun unsigned int val)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun struct ad5449 *st = iio_priv(indio_dev);
90*4882a593Smuzhiyun int ret;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun mutex_lock(&st->lock);
93*4882a593Smuzhiyun st->data[0] = cpu_to_be16((addr << 12) | val);
94*4882a593Smuzhiyun ret = spi_write(st->spi, st->data, 2);
95*4882a593Smuzhiyun mutex_unlock(&st->lock);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun return ret;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
ad5449_read(struct iio_dev * indio_dev,unsigned int addr,unsigned int * val)100*4882a593Smuzhiyun static int ad5449_read(struct iio_dev *indio_dev, unsigned int addr,
101*4882a593Smuzhiyun unsigned int *val)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun struct ad5449 *st = iio_priv(indio_dev);
104*4882a593Smuzhiyun int ret;
105*4882a593Smuzhiyun struct spi_transfer t[] = {
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun .tx_buf = &st->data[0],
108*4882a593Smuzhiyun .len = 2,
109*4882a593Smuzhiyun .cs_change = 1,
110*4882a593Smuzhiyun }, {
111*4882a593Smuzhiyun .tx_buf = &st->data[1],
112*4882a593Smuzhiyun .rx_buf = &st->data[1],
113*4882a593Smuzhiyun .len = 2,
114*4882a593Smuzhiyun },
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun mutex_lock(&st->lock);
118*4882a593Smuzhiyun st->data[0] = cpu_to_be16(addr << 12);
119*4882a593Smuzhiyun st->data[1] = cpu_to_be16(AD5449_CMD_NOOP);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
122*4882a593Smuzhiyun if (ret < 0)
123*4882a593Smuzhiyun goto out_unlock;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun *val = be16_to_cpu(st->data[1]);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun out_unlock:
128*4882a593Smuzhiyun mutex_unlock(&st->lock);
129*4882a593Smuzhiyun return ret;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
ad5449_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)132*4882a593Smuzhiyun static int ad5449_read_raw(struct iio_dev *indio_dev,
133*4882a593Smuzhiyun struct iio_chan_spec const *chan, int *val, int *val2, long info)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun struct ad5449 *st = iio_priv(indio_dev);
136*4882a593Smuzhiyun struct regulator_bulk_data *reg;
137*4882a593Smuzhiyun int scale_uv;
138*4882a593Smuzhiyun int ret;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun switch (info) {
141*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
142*4882a593Smuzhiyun if (st->has_sdo) {
143*4882a593Smuzhiyun ret = ad5449_read(indio_dev,
144*4882a593Smuzhiyun AD5449_CMD_READ(chan->address), val);
145*4882a593Smuzhiyun if (ret)
146*4882a593Smuzhiyun return ret;
147*4882a593Smuzhiyun *val &= 0xfff;
148*4882a593Smuzhiyun } else {
149*4882a593Smuzhiyun *val = st->dac_cache[chan->address];
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun return IIO_VAL_INT;
153*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
154*4882a593Smuzhiyun reg = &st->vref_reg[chan->channel];
155*4882a593Smuzhiyun scale_uv = regulator_get_voltage(reg->consumer);
156*4882a593Smuzhiyun if (scale_uv < 0)
157*4882a593Smuzhiyun return scale_uv;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun *val = scale_uv / 1000;
160*4882a593Smuzhiyun *val2 = chan->scan_type.realbits;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL_LOG2;
163*4882a593Smuzhiyun default:
164*4882a593Smuzhiyun break;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun return -EINVAL;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
ad5449_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)170*4882a593Smuzhiyun static int ad5449_write_raw(struct iio_dev *indio_dev,
171*4882a593Smuzhiyun struct iio_chan_spec const *chan, int val, int val2, long info)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun struct ad5449 *st = iio_priv(indio_dev);
174*4882a593Smuzhiyun int ret;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun switch (info) {
177*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
178*4882a593Smuzhiyun if (val < 0 || val >= (1 << chan->scan_type.realbits))
179*4882a593Smuzhiyun return -EINVAL;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun ret = ad5449_write(indio_dev,
182*4882a593Smuzhiyun AD5449_CMD_LOAD_AND_UPDATE(chan->address),
183*4882a593Smuzhiyun val << chan->scan_type.shift);
184*4882a593Smuzhiyun if (ret == 0)
185*4882a593Smuzhiyun st->dac_cache[chan->address] = val;
186*4882a593Smuzhiyun break;
187*4882a593Smuzhiyun default:
188*4882a593Smuzhiyun ret = -EINVAL;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun return ret;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun static const struct iio_info ad5449_info = {
195*4882a593Smuzhiyun .read_raw = ad5449_read_raw,
196*4882a593Smuzhiyun .write_raw = ad5449_write_raw,
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun #define AD5449_CHANNEL(chan, bits) { \
200*4882a593Smuzhiyun .type = IIO_VOLTAGE, \
201*4882a593Smuzhiyun .indexed = 1, \
202*4882a593Smuzhiyun .output = 1, \
203*4882a593Smuzhiyun .channel = (chan), \
204*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
205*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE), \
206*4882a593Smuzhiyun .address = (chan), \
207*4882a593Smuzhiyun .scan_type = { \
208*4882a593Smuzhiyun .sign = 'u', \
209*4882a593Smuzhiyun .realbits = (bits), \
210*4882a593Smuzhiyun .storagebits = 16, \
211*4882a593Smuzhiyun .shift = 12 - (bits), \
212*4882a593Smuzhiyun }, \
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun #define DECLARE_AD5449_CHANNELS(name, bits) \
216*4882a593Smuzhiyun const struct iio_chan_spec name[] = { \
217*4882a593Smuzhiyun AD5449_CHANNEL(0, bits), \
218*4882a593Smuzhiyun AD5449_CHANNEL(1, bits), \
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun static DECLARE_AD5449_CHANNELS(ad5429_channels, 8);
222*4882a593Smuzhiyun static DECLARE_AD5449_CHANNELS(ad5439_channels, 10);
223*4882a593Smuzhiyun static DECLARE_AD5449_CHANNELS(ad5449_channels, 12);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun static const struct ad5449_chip_info ad5449_chip_info[] = {
226*4882a593Smuzhiyun [ID_AD5426] = {
227*4882a593Smuzhiyun .channels = ad5429_channels,
228*4882a593Smuzhiyun .num_channels = 1,
229*4882a593Smuzhiyun .has_ctrl = false,
230*4882a593Smuzhiyun },
231*4882a593Smuzhiyun [ID_AD5429] = {
232*4882a593Smuzhiyun .channels = ad5429_channels,
233*4882a593Smuzhiyun .num_channels = 2,
234*4882a593Smuzhiyun .has_ctrl = true,
235*4882a593Smuzhiyun },
236*4882a593Smuzhiyun [ID_AD5432] = {
237*4882a593Smuzhiyun .channels = ad5439_channels,
238*4882a593Smuzhiyun .num_channels = 1,
239*4882a593Smuzhiyun .has_ctrl = false,
240*4882a593Smuzhiyun },
241*4882a593Smuzhiyun [ID_AD5439] = {
242*4882a593Smuzhiyun .channels = ad5439_channels,
243*4882a593Smuzhiyun .num_channels = 2,
244*4882a593Smuzhiyun .has_ctrl = true,
245*4882a593Smuzhiyun },
246*4882a593Smuzhiyun [ID_AD5443] = {
247*4882a593Smuzhiyun .channels = ad5449_channels,
248*4882a593Smuzhiyun .num_channels = 1,
249*4882a593Smuzhiyun .has_ctrl = false,
250*4882a593Smuzhiyun },
251*4882a593Smuzhiyun [ID_AD5449] = {
252*4882a593Smuzhiyun .channels = ad5449_channels,
253*4882a593Smuzhiyun .num_channels = 2,
254*4882a593Smuzhiyun .has_ctrl = true,
255*4882a593Smuzhiyun },
256*4882a593Smuzhiyun };
257*4882a593Smuzhiyun
ad5449_vref_name(struct ad5449 * st,int n)258*4882a593Smuzhiyun static const char *ad5449_vref_name(struct ad5449 *st, int n)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun if (st->chip_info->num_channels == 1)
261*4882a593Smuzhiyun return "VREF";
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun if (n == 0)
264*4882a593Smuzhiyun return "VREFA";
265*4882a593Smuzhiyun else
266*4882a593Smuzhiyun return "VREFB";
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
ad5449_spi_probe(struct spi_device * spi)269*4882a593Smuzhiyun static int ad5449_spi_probe(struct spi_device *spi)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun struct ad5449_platform_data *pdata = spi->dev.platform_data;
272*4882a593Smuzhiyun const struct spi_device_id *id = spi_get_device_id(spi);
273*4882a593Smuzhiyun struct iio_dev *indio_dev;
274*4882a593Smuzhiyun struct ad5449 *st;
275*4882a593Smuzhiyun unsigned int i;
276*4882a593Smuzhiyun int ret;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
279*4882a593Smuzhiyun if (indio_dev == NULL)
280*4882a593Smuzhiyun return -ENOMEM;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun st = iio_priv(indio_dev);
283*4882a593Smuzhiyun spi_set_drvdata(spi, indio_dev);
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun st->chip_info = &ad5449_chip_info[id->driver_data];
286*4882a593Smuzhiyun st->spi = spi;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun for (i = 0; i < st->chip_info->num_channels; ++i)
289*4882a593Smuzhiyun st->vref_reg[i].supply = ad5449_vref_name(st, i);
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun ret = devm_regulator_bulk_get(&spi->dev, st->chip_info->num_channels,
292*4882a593Smuzhiyun st->vref_reg);
293*4882a593Smuzhiyun if (ret)
294*4882a593Smuzhiyun return ret;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun ret = regulator_bulk_enable(st->chip_info->num_channels, st->vref_reg);
297*4882a593Smuzhiyun if (ret)
298*4882a593Smuzhiyun return ret;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun indio_dev->name = id->name;
301*4882a593Smuzhiyun indio_dev->info = &ad5449_info;
302*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
303*4882a593Smuzhiyun indio_dev->channels = st->chip_info->channels;
304*4882a593Smuzhiyun indio_dev->num_channels = st->chip_info->num_channels;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun mutex_init(&st->lock);
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun if (st->chip_info->has_ctrl) {
309*4882a593Smuzhiyun unsigned int ctrl = 0x00;
310*4882a593Smuzhiyun if (pdata) {
311*4882a593Smuzhiyun if (pdata->hardware_clear_to_midscale)
312*4882a593Smuzhiyun ctrl |= AD5449_CTRL_HCLR_TO_MIDSCALE;
313*4882a593Smuzhiyun ctrl |= pdata->sdo_mode << AD5449_CTRL_SDO_OFFSET;
314*4882a593Smuzhiyun st->has_sdo = pdata->sdo_mode != AD5449_SDO_DISABLED;
315*4882a593Smuzhiyun } else {
316*4882a593Smuzhiyun st->has_sdo = true;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun ad5449_write(indio_dev, AD5449_CMD_CTRL, ctrl);
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
322*4882a593Smuzhiyun if (ret)
323*4882a593Smuzhiyun goto error_disable_reg;
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun return 0;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun error_disable_reg:
328*4882a593Smuzhiyun regulator_bulk_disable(st->chip_info->num_channels, st->vref_reg);
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun return ret;
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun
ad5449_spi_remove(struct spi_device * spi)333*4882a593Smuzhiyun static int ad5449_spi_remove(struct spi_device *spi)
334*4882a593Smuzhiyun {
335*4882a593Smuzhiyun struct iio_dev *indio_dev = spi_get_drvdata(spi);
336*4882a593Smuzhiyun struct ad5449 *st = iio_priv(indio_dev);
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun iio_device_unregister(indio_dev);
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun regulator_bulk_disable(st->chip_info->num_channels, st->vref_reg);
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun return 0;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun static const struct spi_device_id ad5449_spi_ids[] = {
346*4882a593Smuzhiyun { "ad5415", ID_AD5449 },
347*4882a593Smuzhiyun { "ad5426", ID_AD5426 },
348*4882a593Smuzhiyun { "ad5429", ID_AD5429 },
349*4882a593Smuzhiyun { "ad5432", ID_AD5432 },
350*4882a593Smuzhiyun { "ad5439", ID_AD5439 },
351*4882a593Smuzhiyun { "ad5443", ID_AD5443 },
352*4882a593Smuzhiyun { "ad5449", ID_AD5449 },
353*4882a593Smuzhiyun {}
354*4882a593Smuzhiyun };
355*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ad5449_spi_ids);
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun static struct spi_driver ad5449_spi_driver = {
358*4882a593Smuzhiyun .driver = {
359*4882a593Smuzhiyun .name = "ad5449",
360*4882a593Smuzhiyun },
361*4882a593Smuzhiyun .probe = ad5449_spi_probe,
362*4882a593Smuzhiyun .remove = ad5449_spi_remove,
363*4882a593Smuzhiyun .id_table = ad5449_spi_ids,
364*4882a593Smuzhiyun };
365*4882a593Smuzhiyun module_spi_driver(ad5449_spi_driver);
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
368*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices AD5449 and similar DACs");
369*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
370