xref: /OK3568_Linux_fs/kernel/drivers/iio/dac/ad5446.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * AD5446 SPI DAC driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2010 Analog Devices Inc.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/interrupt.h>
9*4882a593Smuzhiyun #include <linux/workqueue.h>
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun #include <linux/sysfs.h>
14*4882a593Smuzhiyun #include <linux/list.h>
15*4882a593Smuzhiyun #include <linux/spi/spi.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
18*4882a593Smuzhiyun #include <linux/err.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #include <linux/iio/iio.h>
23*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #include <asm/unaligned.h>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define MODE_PWRDWN_1k		0x1
28*4882a593Smuzhiyun #define MODE_PWRDWN_100k	0x2
29*4882a593Smuzhiyun #define MODE_PWRDWN_TRISTATE	0x3
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun /**
32*4882a593Smuzhiyun  * struct ad5446_state - driver instance specific data
33*4882a593Smuzhiyun  * @dev:		this device
34*4882a593Smuzhiyun  * @chip_info:		chip model specific constants, available modes etc
35*4882a593Smuzhiyun  * @reg:		supply regulator
36*4882a593Smuzhiyun  * @vref_mv:		actual reference voltage used
37*4882a593Smuzhiyun  * @cached_val:		store/retrieve values during power down
38*4882a593Smuzhiyun  * @pwr_down_mode:	power down mode (1k, 100k or tristate)
39*4882a593Smuzhiyun  * @pwr_down:		true if the device is in power down
40*4882a593Smuzhiyun  * @lock:		lock to protect the data buffer during write ops
41*4882a593Smuzhiyun  */
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun struct ad5446_state {
44*4882a593Smuzhiyun 	struct device		*dev;
45*4882a593Smuzhiyun 	const struct ad5446_chip_info	*chip_info;
46*4882a593Smuzhiyun 	struct regulator		*reg;
47*4882a593Smuzhiyun 	unsigned short			vref_mv;
48*4882a593Smuzhiyun 	unsigned			cached_val;
49*4882a593Smuzhiyun 	unsigned			pwr_down_mode;
50*4882a593Smuzhiyun 	unsigned			pwr_down;
51*4882a593Smuzhiyun 	struct mutex			lock;
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /**
55*4882a593Smuzhiyun  * struct ad5446_chip_info - chip specific information
56*4882a593Smuzhiyun  * @channel:		channel spec for the DAC
57*4882a593Smuzhiyun  * @int_vref_mv:	AD5620/40/60: the internal reference voltage
58*4882a593Smuzhiyun  * @write:		chip specific helper function to write to the register
59*4882a593Smuzhiyun  */
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun struct ad5446_chip_info {
62*4882a593Smuzhiyun 	struct iio_chan_spec	channel;
63*4882a593Smuzhiyun 	u16			int_vref_mv;
64*4882a593Smuzhiyun 	int			(*write)(struct ad5446_state *st, unsigned val);
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun static const char * const ad5446_powerdown_modes[] = {
68*4882a593Smuzhiyun 	"1kohm_to_gnd", "100kohm_to_gnd", "three_state"
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun 
ad5446_set_powerdown_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)71*4882a593Smuzhiyun static int ad5446_set_powerdown_mode(struct iio_dev *indio_dev,
72*4882a593Smuzhiyun 	const struct iio_chan_spec *chan, unsigned int mode)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun 	struct ad5446_state *st = iio_priv(indio_dev);
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	st->pwr_down_mode = mode + 1;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	return 0;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun 
ad5446_get_powerdown_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)81*4882a593Smuzhiyun static int ad5446_get_powerdown_mode(struct iio_dev *indio_dev,
82*4882a593Smuzhiyun 	const struct iio_chan_spec *chan)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun 	struct ad5446_state *st = iio_priv(indio_dev);
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	return st->pwr_down_mode - 1;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun static const struct iio_enum ad5446_powerdown_mode_enum = {
90*4882a593Smuzhiyun 	.items = ad5446_powerdown_modes,
91*4882a593Smuzhiyun 	.num_items = ARRAY_SIZE(ad5446_powerdown_modes),
92*4882a593Smuzhiyun 	.get = ad5446_get_powerdown_mode,
93*4882a593Smuzhiyun 	.set = ad5446_set_powerdown_mode,
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun 
ad5446_read_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)96*4882a593Smuzhiyun static ssize_t ad5446_read_dac_powerdown(struct iio_dev *indio_dev,
97*4882a593Smuzhiyun 					   uintptr_t private,
98*4882a593Smuzhiyun 					   const struct iio_chan_spec *chan,
99*4882a593Smuzhiyun 					   char *buf)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun 	struct ad5446_state *st = iio_priv(indio_dev);
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	return sprintf(buf, "%d\n", st->pwr_down);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun 
ad5446_write_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)106*4882a593Smuzhiyun static ssize_t ad5446_write_dac_powerdown(struct iio_dev *indio_dev,
107*4882a593Smuzhiyun 					    uintptr_t private,
108*4882a593Smuzhiyun 					    const struct iio_chan_spec *chan,
109*4882a593Smuzhiyun 					    const char *buf, size_t len)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun 	struct ad5446_state *st = iio_priv(indio_dev);
112*4882a593Smuzhiyun 	unsigned int shift;
113*4882a593Smuzhiyun 	unsigned int val;
114*4882a593Smuzhiyun 	bool powerdown;
115*4882a593Smuzhiyun 	int ret;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	ret = strtobool(buf, &powerdown);
118*4882a593Smuzhiyun 	if (ret)
119*4882a593Smuzhiyun 		return ret;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	mutex_lock(&st->lock);
122*4882a593Smuzhiyun 	st->pwr_down = powerdown;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	if (st->pwr_down) {
125*4882a593Smuzhiyun 		shift = chan->scan_type.realbits + chan->scan_type.shift;
126*4882a593Smuzhiyun 		val = st->pwr_down_mode << shift;
127*4882a593Smuzhiyun 	} else {
128*4882a593Smuzhiyun 		val = st->cached_val;
129*4882a593Smuzhiyun 	}
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	ret = st->chip_info->write(st, val);
132*4882a593Smuzhiyun 	mutex_unlock(&st->lock);
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	return ret ? ret : len;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun static const struct iio_chan_spec_ext_info ad5446_ext_info_powerdown[] = {
138*4882a593Smuzhiyun 	{
139*4882a593Smuzhiyun 		.name = "powerdown",
140*4882a593Smuzhiyun 		.read = ad5446_read_dac_powerdown,
141*4882a593Smuzhiyun 		.write = ad5446_write_dac_powerdown,
142*4882a593Smuzhiyun 		.shared = IIO_SEPARATE,
143*4882a593Smuzhiyun 	},
144*4882a593Smuzhiyun 	IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad5446_powerdown_mode_enum),
145*4882a593Smuzhiyun 	IIO_ENUM_AVAILABLE("powerdown_mode", &ad5446_powerdown_mode_enum),
146*4882a593Smuzhiyun 	{ },
147*4882a593Smuzhiyun };
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun #define _AD5446_CHANNEL(bits, storage, _shift, ext) { \
150*4882a593Smuzhiyun 	.type = IIO_VOLTAGE, \
151*4882a593Smuzhiyun 	.indexed = 1, \
152*4882a593Smuzhiyun 	.output = 1, \
153*4882a593Smuzhiyun 	.channel = 0, \
154*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
155*4882a593Smuzhiyun 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
156*4882a593Smuzhiyun 	.scan_type = { \
157*4882a593Smuzhiyun 		.sign = 'u', \
158*4882a593Smuzhiyun 		.realbits = (bits), \
159*4882a593Smuzhiyun 		.storagebits = (storage), \
160*4882a593Smuzhiyun 		.shift = (_shift), \
161*4882a593Smuzhiyun 		}, \
162*4882a593Smuzhiyun 	.ext_info = (ext), \
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun #define AD5446_CHANNEL(bits, storage, shift) \
166*4882a593Smuzhiyun 	_AD5446_CHANNEL(bits, storage, shift, NULL)
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun #define AD5446_CHANNEL_POWERDOWN(bits, storage, shift) \
169*4882a593Smuzhiyun 	_AD5446_CHANNEL(bits, storage, shift, ad5446_ext_info_powerdown)
170*4882a593Smuzhiyun 
ad5446_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)171*4882a593Smuzhiyun static int ad5446_read_raw(struct iio_dev *indio_dev,
172*4882a593Smuzhiyun 			   struct iio_chan_spec const *chan,
173*4882a593Smuzhiyun 			   int *val,
174*4882a593Smuzhiyun 			   int *val2,
175*4882a593Smuzhiyun 			   long m)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun 	struct ad5446_state *st = iio_priv(indio_dev);
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	switch (m) {
180*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
181*4882a593Smuzhiyun 		*val = st->cached_val >> chan->scan_type.shift;
182*4882a593Smuzhiyun 		return IIO_VAL_INT;
183*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
184*4882a593Smuzhiyun 		*val = st->vref_mv;
185*4882a593Smuzhiyun 		*val2 = chan->scan_type.realbits;
186*4882a593Smuzhiyun 		return IIO_VAL_FRACTIONAL_LOG2;
187*4882a593Smuzhiyun 	}
188*4882a593Smuzhiyun 	return -EINVAL;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun 
ad5446_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)191*4882a593Smuzhiyun static int ad5446_write_raw(struct iio_dev *indio_dev,
192*4882a593Smuzhiyun 			       struct iio_chan_spec const *chan,
193*4882a593Smuzhiyun 			       int val,
194*4882a593Smuzhiyun 			       int val2,
195*4882a593Smuzhiyun 			       long mask)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun 	struct ad5446_state *st = iio_priv(indio_dev);
198*4882a593Smuzhiyun 	int ret = 0;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	switch (mask) {
201*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
202*4882a593Smuzhiyun 		if (val >= (1 << chan->scan_type.realbits) || val < 0)
203*4882a593Smuzhiyun 			return -EINVAL;
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 		val <<= chan->scan_type.shift;
206*4882a593Smuzhiyun 		mutex_lock(&st->lock);
207*4882a593Smuzhiyun 		st->cached_val = val;
208*4882a593Smuzhiyun 		if (!st->pwr_down)
209*4882a593Smuzhiyun 			ret = st->chip_info->write(st, val);
210*4882a593Smuzhiyun 		mutex_unlock(&st->lock);
211*4882a593Smuzhiyun 		break;
212*4882a593Smuzhiyun 	default:
213*4882a593Smuzhiyun 		ret = -EINVAL;
214*4882a593Smuzhiyun 	}
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	return ret;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun static const struct iio_info ad5446_info = {
220*4882a593Smuzhiyun 	.read_raw = ad5446_read_raw,
221*4882a593Smuzhiyun 	.write_raw = ad5446_write_raw,
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun 
ad5446_probe(struct device * dev,const char * name,const struct ad5446_chip_info * chip_info)224*4882a593Smuzhiyun static int ad5446_probe(struct device *dev, const char *name,
225*4882a593Smuzhiyun 			const struct ad5446_chip_info *chip_info)
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun 	struct ad5446_state *st;
228*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
229*4882a593Smuzhiyun 	struct regulator *reg;
230*4882a593Smuzhiyun 	int ret, voltage_uv = 0;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	reg = devm_regulator_get(dev, "vcc");
233*4882a593Smuzhiyun 	if (!IS_ERR(reg)) {
234*4882a593Smuzhiyun 		ret = regulator_enable(reg);
235*4882a593Smuzhiyun 		if (ret)
236*4882a593Smuzhiyun 			return ret;
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 		ret = regulator_get_voltage(reg);
239*4882a593Smuzhiyun 		if (ret < 0)
240*4882a593Smuzhiyun 			goto error_disable_reg;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 		voltage_uv = ret;
243*4882a593Smuzhiyun 	}
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
246*4882a593Smuzhiyun 	if (indio_dev == NULL) {
247*4882a593Smuzhiyun 		ret = -ENOMEM;
248*4882a593Smuzhiyun 		goto error_disable_reg;
249*4882a593Smuzhiyun 	}
250*4882a593Smuzhiyun 	st = iio_priv(indio_dev);
251*4882a593Smuzhiyun 	st->chip_info = chip_info;
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	dev_set_drvdata(dev, indio_dev);
254*4882a593Smuzhiyun 	st->reg = reg;
255*4882a593Smuzhiyun 	st->dev = dev;
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	indio_dev->name = name;
258*4882a593Smuzhiyun 	indio_dev->info = &ad5446_info;
259*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
260*4882a593Smuzhiyun 	indio_dev->channels = &st->chip_info->channel;
261*4882a593Smuzhiyun 	indio_dev->num_channels = 1;
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	mutex_init(&st->lock);
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	st->pwr_down_mode = MODE_PWRDWN_1k;
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	if (st->chip_info->int_vref_mv)
268*4882a593Smuzhiyun 		st->vref_mv = st->chip_info->int_vref_mv;
269*4882a593Smuzhiyun 	else if (voltage_uv)
270*4882a593Smuzhiyun 		st->vref_mv = voltage_uv / 1000;
271*4882a593Smuzhiyun 	else
272*4882a593Smuzhiyun 		dev_warn(dev, "reference voltage unspecified\n");
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	ret = iio_device_register(indio_dev);
275*4882a593Smuzhiyun 	if (ret)
276*4882a593Smuzhiyun 		goto error_disable_reg;
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	return 0;
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun error_disable_reg:
281*4882a593Smuzhiyun 	if (!IS_ERR(reg))
282*4882a593Smuzhiyun 		regulator_disable(reg);
283*4882a593Smuzhiyun 	return ret;
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun 
ad5446_remove(struct device * dev)286*4882a593Smuzhiyun static int ad5446_remove(struct device *dev)
287*4882a593Smuzhiyun {
288*4882a593Smuzhiyun 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
289*4882a593Smuzhiyun 	struct ad5446_state *st = iio_priv(indio_dev);
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	iio_device_unregister(indio_dev);
292*4882a593Smuzhiyun 	if (!IS_ERR(st->reg))
293*4882a593Smuzhiyun 		regulator_disable(st->reg);
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 	return 0;
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SPI_MASTER)
299*4882a593Smuzhiyun 
ad5446_write(struct ad5446_state * st,unsigned val)300*4882a593Smuzhiyun static int ad5446_write(struct ad5446_state *st, unsigned val)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun 	struct spi_device *spi = to_spi_device(st->dev);
303*4882a593Smuzhiyun 	__be16 data = cpu_to_be16(val);
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	return spi_write(spi, &data, sizeof(data));
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun 
ad5660_write(struct ad5446_state * st,unsigned val)308*4882a593Smuzhiyun static int ad5660_write(struct ad5446_state *st, unsigned val)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun 	struct spi_device *spi = to_spi_device(st->dev);
311*4882a593Smuzhiyun 	uint8_t data[3];
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	put_unaligned_be24(val, &data[0]);
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 	return spi_write(spi, data, sizeof(data));
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun /*
319*4882a593Smuzhiyun  * ad5446_supported_spi_device_ids:
320*4882a593Smuzhiyun  * The AD5620/40/60 parts are available in different fixed internal reference
321*4882a593Smuzhiyun  * voltage options. The actual part numbers may look differently
322*4882a593Smuzhiyun  * (and a bit cryptic), however this style is used to make clear which
323*4882a593Smuzhiyun  * parts are supported here.
324*4882a593Smuzhiyun  */
325*4882a593Smuzhiyun enum ad5446_supported_spi_device_ids {
326*4882a593Smuzhiyun 	ID_AD5300,
327*4882a593Smuzhiyun 	ID_AD5310,
328*4882a593Smuzhiyun 	ID_AD5320,
329*4882a593Smuzhiyun 	ID_AD5444,
330*4882a593Smuzhiyun 	ID_AD5446,
331*4882a593Smuzhiyun 	ID_AD5450,
332*4882a593Smuzhiyun 	ID_AD5451,
333*4882a593Smuzhiyun 	ID_AD5541A,
334*4882a593Smuzhiyun 	ID_AD5512A,
335*4882a593Smuzhiyun 	ID_AD5553,
336*4882a593Smuzhiyun 	ID_AD5600,
337*4882a593Smuzhiyun 	ID_AD5601,
338*4882a593Smuzhiyun 	ID_AD5611,
339*4882a593Smuzhiyun 	ID_AD5621,
340*4882a593Smuzhiyun 	ID_AD5641,
341*4882a593Smuzhiyun 	ID_AD5620_2500,
342*4882a593Smuzhiyun 	ID_AD5620_1250,
343*4882a593Smuzhiyun 	ID_AD5640_2500,
344*4882a593Smuzhiyun 	ID_AD5640_1250,
345*4882a593Smuzhiyun 	ID_AD5660_2500,
346*4882a593Smuzhiyun 	ID_AD5660_1250,
347*4882a593Smuzhiyun 	ID_AD5662,
348*4882a593Smuzhiyun };
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun static const struct ad5446_chip_info ad5446_spi_chip_info[] = {
351*4882a593Smuzhiyun 	[ID_AD5300] = {
352*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(8, 16, 4),
353*4882a593Smuzhiyun 		.write = ad5446_write,
354*4882a593Smuzhiyun 	},
355*4882a593Smuzhiyun 	[ID_AD5310] = {
356*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(10, 16, 2),
357*4882a593Smuzhiyun 		.write = ad5446_write,
358*4882a593Smuzhiyun 	},
359*4882a593Smuzhiyun 	[ID_AD5320] = {
360*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(12, 16, 0),
361*4882a593Smuzhiyun 		.write = ad5446_write,
362*4882a593Smuzhiyun 	},
363*4882a593Smuzhiyun 	[ID_AD5444] = {
364*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL(12, 16, 2),
365*4882a593Smuzhiyun 		.write = ad5446_write,
366*4882a593Smuzhiyun 	},
367*4882a593Smuzhiyun 	[ID_AD5446] = {
368*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL(14, 16, 0),
369*4882a593Smuzhiyun 		.write = ad5446_write,
370*4882a593Smuzhiyun 	},
371*4882a593Smuzhiyun 	[ID_AD5450] = {
372*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL(8, 16, 6),
373*4882a593Smuzhiyun 		.write = ad5446_write,
374*4882a593Smuzhiyun 	},
375*4882a593Smuzhiyun 	[ID_AD5451] = {
376*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL(10, 16, 4),
377*4882a593Smuzhiyun 		.write = ad5446_write,
378*4882a593Smuzhiyun 	},
379*4882a593Smuzhiyun 	[ID_AD5541A] = {
380*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL(16, 16, 0),
381*4882a593Smuzhiyun 		.write = ad5446_write,
382*4882a593Smuzhiyun 	},
383*4882a593Smuzhiyun 	[ID_AD5512A] = {
384*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL(12, 16, 4),
385*4882a593Smuzhiyun 		.write = ad5446_write,
386*4882a593Smuzhiyun 	},
387*4882a593Smuzhiyun 	[ID_AD5553] = {
388*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL(14, 16, 0),
389*4882a593Smuzhiyun 		.write = ad5446_write,
390*4882a593Smuzhiyun 	},
391*4882a593Smuzhiyun 	[ID_AD5600] = {
392*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL(16, 16, 0),
393*4882a593Smuzhiyun 		.write = ad5446_write,
394*4882a593Smuzhiyun 	},
395*4882a593Smuzhiyun 	[ID_AD5601] = {
396*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(8, 16, 6),
397*4882a593Smuzhiyun 		.write = ad5446_write,
398*4882a593Smuzhiyun 	},
399*4882a593Smuzhiyun 	[ID_AD5611] = {
400*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(10, 16, 4),
401*4882a593Smuzhiyun 		.write = ad5446_write,
402*4882a593Smuzhiyun 	},
403*4882a593Smuzhiyun 	[ID_AD5621] = {
404*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2),
405*4882a593Smuzhiyun 		.write = ad5446_write,
406*4882a593Smuzhiyun 	},
407*4882a593Smuzhiyun 	[ID_AD5641] = {
408*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0),
409*4882a593Smuzhiyun 		.write = ad5446_write,
410*4882a593Smuzhiyun 	},
411*4882a593Smuzhiyun 	[ID_AD5620_2500] = {
412*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2),
413*4882a593Smuzhiyun 		.int_vref_mv = 2500,
414*4882a593Smuzhiyun 		.write = ad5446_write,
415*4882a593Smuzhiyun 	},
416*4882a593Smuzhiyun 	[ID_AD5620_1250] = {
417*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(12, 16, 2),
418*4882a593Smuzhiyun 		.int_vref_mv = 1250,
419*4882a593Smuzhiyun 		.write = ad5446_write,
420*4882a593Smuzhiyun 	},
421*4882a593Smuzhiyun 	[ID_AD5640_2500] = {
422*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0),
423*4882a593Smuzhiyun 		.int_vref_mv = 2500,
424*4882a593Smuzhiyun 		.write = ad5446_write,
425*4882a593Smuzhiyun 	},
426*4882a593Smuzhiyun 	[ID_AD5640_1250] = {
427*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(14, 16, 0),
428*4882a593Smuzhiyun 		.int_vref_mv = 1250,
429*4882a593Smuzhiyun 		.write = ad5446_write,
430*4882a593Smuzhiyun 	},
431*4882a593Smuzhiyun 	[ID_AD5660_2500] = {
432*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0),
433*4882a593Smuzhiyun 		.int_vref_mv = 2500,
434*4882a593Smuzhiyun 		.write = ad5660_write,
435*4882a593Smuzhiyun 	},
436*4882a593Smuzhiyun 	[ID_AD5660_1250] = {
437*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0),
438*4882a593Smuzhiyun 		.int_vref_mv = 1250,
439*4882a593Smuzhiyun 		.write = ad5660_write,
440*4882a593Smuzhiyun 	},
441*4882a593Smuzhiyun 	[ID_AD5662] = {
442*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(16, 16, 0),
443*4882a593Smuzhiyun 		.write = ad5660_write,
444*4882a593Smuzhiyun 	},
445*4882a593Smuzhiyun };
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun static const struct spi_device_id ad5446_spi_ids[] = {
448*4882a593Smuzhiyun 	{"ad5300", ID_AD5300},
449*4882a593Smuzhiyun 	{"ad5310", ID_AD5310},
450*4882a593Smuzhiyun 	{"ad5320", ID_AD5320},
451*4882a593Smuzhiyun 	{"ad5444", ID_AD5444},
452*4882a593Smuzhiyun 	{"ad5446", ID_AD5446},
453*4882a593Smuzhiyun 	{"ad5450", ID_AD5450},
454*4882a593Smuzhiyun 	{"ad5451", ID_AD5451},
455*4882a593Smuzhiyun 	{"ad5452", ID_AD5444}, /* ad5452 is compatible to the ad5444 */
456*4882a593Smuzhiyun 	{"ad5453", ID_AD5446}, /* ad5453 is compatible to the ad5446 */
457*4882a593Smuzhiyun 	{"ad5512a", ID_AD5512A},
458*4882a593Smuzhiyun 	{"ad5541a", ID_AD5541A},
459*4882a593Smuzhiyun 	{"ad5542a", ID_AD5541A}, /* ad5541a and ad5542a are compatible */
460*4882a593Smuzhiyun 	{"ad5543", ID_AD5541A}, /* ad5541a and ad5543 are compatible */
461*4882a593Smuzhiyun 	{"ad5553", ID_AD5553},
462*4882a593Smuzhiyun 	{"ad5600", ID_AD5600},
463*4882a593Smuzhiyun 	{"ad5601", ID_AD5601},
464*4882a593Smuzhiyun 	{"ad5611", ID_AD5611},
465*4882a593Smuzhiyun 	{"ad5621", ID_AD5621},
466*4882a593Smuzhiyun 	{"ad5641", ID_AD5641},
467*4882a593Smuzhiyun 	{"ad5620-2500", ID_AD5620_2500}, /* AD5620/40/60: */
468*4882a593Smuzhiyun 	{"ad5620-1250", ID_AD5620_1250}, /* part numbers may look differently */
469*4882a593Smuzhiyun 	{"ad5640-2500", ID_AD5640_2500},
470*4882a593Smuzhiyun 	{"ad5640-1250", ID_AD5640_1250},
471*4882a593Smuzhiyun 	{"ad5660-2500", ID_AD5660_2500},
472*4882a593Smuzhiyun 	{"ad5660-1250", ID_AD5660_1250},
473*4882a593Smuzhiyun 	{"ad5662", ID_AD5662},
474*4882a593Smuzhiyun 	{"dac081s101", ID_AD5300}, /* compatible Texas Instruments chips */
475*4882a593Smuzhiyun 	{"dac101s101", ID_AD5310},
476*4882a593Smuzhiyun 	{"dac121s101", ID_AD5320},
477*4882a593Smuzhiyun 	{"dac7512", ID_AD5320},
478*4882a593Smuzhiyun 	{}
479*4882a593Smuzhiyun };
480*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ad5446_spi_ids);
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun static const struct of_device_id ad5446_of_ids[] = {
483*4882a593Smuzhiyun 	{ .compatible = "ti,dac7512" },
484*4882a593Smuzhiyun 	{ }
485*4882a593Smuzhiyun };
486*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ad5446_of_ids);
487*4882a593Smuzhiyun 
ad5446_spi_probe(struct spi_device * spi)488*4882a593Smuzhiyun static int ad5446_spi_probe(struct spi_device *spi)
489*4882a593Smuzhiyun {
490*4882a593Smuzhiyun 	const struct spi_device_id *id = spi_get_device_id(spi);
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	return ad5446_probe(&spi->dev, id->name,
493*4882a593Smuzhiyun 		&ad5446_spi_chip_info[id->driver_data]);
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun 
ad5446_spi_remove(struct spi_device * spi)496*4882a593Smuzhiyun static int ad5446_spi_remove(struct spi_device *spi)
497*4882a593Smuzhiyun {
498*4882a593Smuzhiyun 	return ad5446_remove(&spi->dev);
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun static struct spi_driver ad5446_spi_driver = {
502*4882a593Smuzhiyun 	.driver = {
503*4882a593Smuzhiyun 		.name	= "ad5446",
504*4882a593Smuzhiyun 		.of_match_table = ad5446_of_ids,
505*4882a593Smuzhiyun 	},
506*4882a593Smuzhiyun 	.probe		= ad5446_spi_probe,
507*4882a593Smuzhiyun 	.remove		= ad5446_spi_remove,
508*4882a593Smuzhiyun 	.id_table	= ad5446_spi_ids,
509*4882a593Smuzhiyun };
510*4882a593Smuzhiyun 
ad5446_spi_register_driver(void)511*4882a593Smuzhiyun static int __init ad5446_spi_register_driver(void)
512*4882a593Smuzhiyun {
513*4882a593Smuzhiyun 	return spi_register_driver(&ad5446_spi_driver);
514*4882a593Smuzhiyun }
515*4882a593Smuzhiyun 
ad5446_spi_unregister_driver(void)516*4882a593Smuzhiyun static void ad5446_spi_unregister_driver(void)
517*4882a593Smuzhiyun {
518*4882a593Smuzhiyun 	spi_unregister_driver(&ad5446_spi_driver);
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun #else
522*4882a593Smuzhiyun 
ad5446_spi_register_driver(void)523*4882a593Smuzhiyun static inline int ad5446_spi_register_driver(void) { return 0; }
ad5446_spi_unregister_driver(void)524*4882a593Smuzhiyun static inline void ad5446_spi_unregister_driver(void) { }
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun #endif
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C)
529*4882a593Smuzhiyun 
ad5622_write(struct ad5446_state * st,unsigned val)530*4882a593Smuzhiyun static int ad5622_write(struct ad5446_state *st, unsigned val)
531*4882a593Smuzhiyun {
532*4882a593Smuzhiyun 	struct i2c_client *client = to_i2c_client(st->dev);
533*4882a593Smuzhiyun 	__be16 data = cpu_to_be16(val);
534*4882a593Smuzhiyun 	int ret;
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun 	ret = i2c_master_send(client, (char *)&data, sizeof(data));
537*4882a593Smuzhiyun 	if (ret < 0)
538*4882a593Smuzhiyun 		return ret;
539*4882a593Smuzhiyun 	if (ret != sizeof(data))
540*4882a593Smuzhiyun 		return -EIO;
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	return 0;
543*4882a593Smuzhiyun }
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun /*
546*4882a593Smuzhiyun  * ad5446_supported_i2c_device_ids:
547*4882a593Smuzhiyun  * The AD5620/40/60 parts are available in different fixed internal reference
548*4882a593Smuzhiyun  * voltage options. The actual part numbers may look differently
549*4882a593Smuzhiyun  * (and a bit cryptic), however this style is used to make clear which
550*4882a593Smuzhiyun  * parts are supported here.
551*4882a593Smuzhiyun  */
552*4882a593Smuzhiyun enum ad5446_supported_i2c_device_ids {
553*4882a593Smuzhiyun 	ID_AD5602,
554*4882a593Smuzhiyun 	ID_AD5612,
555*4882a593Smuzhiyun 	ID_AD5622,
556*4882a593Smuzhiyun };
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun static const struct ad5446_chip_info ad5446_i2c_chip_info[] = {
559*4882a593Smuzhiyun 	[ID_AD5602] = {
560*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(8, 16, 4),
561*4882a593Smuzhiyun 		.write = ad5622_write,
562*4882a593Smuzhiyun 	},
563*4882a593Smuzhiyun 	[ID_AD5612] = {
564*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(10, 16, 2),
565*4882a593Smuzhiyun 		.write = ad5622_write,
566*4882a593Smuzhiyun 	},
567*4882a593Smuzhiyun 	[ID_AD5622] = {
568*4882a593Smuzhiyun 		.channel = AD5446_CHANNEL_POWERDOWN(12, 16, 0),
569*4882a593Smuzhiyun 		.write = ad5622_write,
570*4882a593Smuzhiyun 	},
571*4882a593Smuzhiyun };
572*4882a593Smuzhiyun 
ad5446_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)573*4882a593Smuzhiyun static int ad5446_i2c_probe(struct i2c_client *i2c,
574*4882a593Smuzhiyun 			    const struct i2c_device_id *id)
575*4882a593Smuzhiyun {
576*4882a593Smuzhiyun 	return ad5446_probe(&i2c->dev, id->name,
577*4882a593Smuzhiyun 		&ad5446_i2c_chip_info[id->driver_data]);
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun 
ad5446_i2c_remove(struct i2c_client * i2c)580*4882a593Smuzhiyun static int ad5446_i2c_remove(struct i2c_client *i2c)
581*4882a593Smuzhiyun {
582*4882a593Smuzhiyun 	return ad5446_remove(&i2c->dev);
583*4882a593Smuzhiyun }
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun static const struct i2c_device_id ad5446_i2c_ids[] = {
586*4882a593Smuzhiyun 	{"ad5301", ID_AD5602},
587*4882a593Smuzhiyun 	{"ad5311", ID_AD5612},
588*4882a593Smuzhiyun 	{"ad5321", ID_AD5622},
589*4882a593Smuzhiyun 	{"ad5602", ID_AD5602},
590*4882a593Smuzhiyun 	{"ad5612", ID_AD5612},
591*4882a593Smuzhiyun 	{"ad5622", ID_AD5622},
592*4882a593Smuzhiyun 	{}
593*4882a593Smuzhiyun };
594*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, ad5446_i2c_ids);
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun static struct i2c_driver ad5446_i2c_driver = {
597*4882a593Smuzhiyun 	.driver = {
598*4882a593Smuzhiyun 		   .name = "ad5446",
599*4882a593Smuzhiyun 	},
600*4882a593Smuzhiyun 	.probe = ad5446_i2c_probe,
601*4882a593Smuzhiyun 	.remove = ad5446_i2c_remove,
602*4882a593Smuzhiyun 	.id_table = ad5446_i2c_ids,
603*4882a593Smuzhiyun };
604*4882a593Smuzhiyun 
ad5446_i2c_register_driver(void)605*4882a593Smuzhiyun static int __init ad5446_i2c_register_driver(void)
606*4882a593Smuzhiyun {
607*4882a593Smuzhiyun 	return i2c_add_driver(&ad5446_i2c_driver);
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun 
ad5446_i2c_unregister_driver(void)610*4882a593Smuzhiyun static void __exit ad5446_i2c_unregister_driver(void)
611*4882a593Smuzhiyun {
612*4882a593Smuzhiyun 	i2c_del_driver(&ad5446_i2c_driver);
613*4882a593Smuzhiyun }
614*4882a593Smuzhiyun 
615*4882a593Smuzhiyun #else
616*4882a593Smuzhiyun 
ad5446_i2c_register_driver(void)617*4882a593Smuzhiyun static inline int ad5446_i2c_register_driver(void) { return 0; }
ad5446_i2c_unregister_driver(void)618*4882a593Smuzhiyun static inline void ad5446_i2c_unregister_driver(void) { }
619*4882a593Smuzhiyun 
620*4882a593Smuzhiyun #endif
621*4882a593Smuzhiyun 
ad5446_init(void)622*4882a593Smuzhiyun static int __init ad5446_init(void)
623*4882a593Smuzhiyun {
624*4882a593Smuzhiyun 	int ret;
625*4882a593Smuzhiyun 
626*4882a593Smuzhiyun 	ret = ad5446_spi_register_driver();
627*4882a593Smuzhiyun 	if (ret)
628*4882a593Smuzhiyun 		return ret;
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun 	ret = ad5446_i2c_register_driver();
631*4882a593Smuzhiyun 	if (ret) {
632*4882a593Smuzhiyun 		ad5446_spi_unregister_driver();
633*4882a593Smuzhiyun 		return ret;
634*4882a593Smuzhiyun 	}
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun 	return 0;
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun module_init(ad5446_init);
639*4882a593Smuzhiyun 
ad5446_exit(void)640*4882a593Smuzhiyun static void __exit ad5446_exit(void)
641*4882a593Smuzhiyun {
642*4882a593Smuzhiyun 	ad5446_i2c_unregister_driver();
643*4882a593Smuzhiyun 	ad5446_spi_unregister_driver();
644*4882a593Smuzhiyun }
645*4882a593Smuzhiyun module_exit(ad5446_exit);
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
648*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices AD5444/AD5446 DAC");
649*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
650