1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Analog devices AD5380, AD5381, AD5382, AD5383, AD5390, AD5391, AD5392
4*4882a593Smuzhiyun * multi-channel Digital to Analog Converters driver
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright 2011 Analog Devices Inc.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/err.h>
11*4882a593Smuzhiyun #include <linux/i2c.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/spi/spi.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/sysfs.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <linux/iio/iio.h>
21*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define AD5380_REG_DATA(x) (((x) << 2) | 3)
24*4882a593Smuzhiyun #define AD5380_REG_OFFSET(x) (((x) << 2) | 2)
25*4882a593Smuzhiyun #define AD5380_REG_GAIN(x) (((x) << 2) | 1)
26*4882a593Smuzhiyun #define AD5380_REG_SF_PWR_DOWN (8 << 2)
27*4882a593Smuzhiyun #define AD5380_REG_SF_PWR_UP (9 << 2)
28*4882a593Smuzhiyun #define AD5380_REG_SF_CTRL (12 << 2)
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define AD5380_CTRL_PWR_DOWN_MODE_OFFSET 13
31*4882a593Smuzhiyun #define AD5380_CTRL_INT_VREF_2V5 BIT(12)
32*4882a593Smuzhiyun #define AD5380_CTRL_INT_VREF_EN BIT(10)
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /**
35*4882a593Smuzhiyun * struct ad5380_chip_info - chip specific information
36*4882a593Smuzhiyun * @channel_template: channel specification template
37*4882a593Smuzhiyun * @num_channels: number of channels
38*4882a593Smuzhiyun * @int_vref: internal vref in uV
39*4882a593Smuzhiyun */
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun struct ad5380_chip_info {
42*4882a593Smuzhiyun struct iio_chan_spec channel_template;
43*4882a593Smuzhiyun unsigned int num_channels;
44*4882a593Smuzhiyun unsigned int int_vref;
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /**
48*4882a593Smuzhiyun * struct ad5380_state - driver instance specific data
49*4882a593Smuzhiyun * @regmap: regmap instance used by the device
50*4882a593Smuzhiyun * @chip_info: chip model specific constants, available modes etc
51*4882a593Smuzhiyun * @vref_reg: vref supply regulator
52*4882a593Smuzhiyun * @vref: actual reference voltage used in uA
53*4882a593Smuzhiyun * @pwr_down: whether the chip is currently in power down mode
54*4882a593Smuzhiyun * @lock: lock to protect the data buffer during regmap ops
55*4882a593Smuzhiyun */
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun struct ad5380_state {
58*4882a593Smuzhiyun struct regmap *regmap;
59*4882a593Smuzhiyun const struct ad5380_chip_info *chip_info;
60*4882a593Smuzhiyun struct regulator *vref_reg;
61*4882a593Smuzhiyun int vref;
62*4882a593Smuzhiyun bool pwr_down;
63*4882a593Smuzhiyun struct mutex lock;
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun enum ad5380_type {
67*4882a593Smuzhiyun ID_AD5380_3,
68*4882a593Smuzhiyun ID_AD5380_5,
69*4882a593Smuzhiyun ID_AD5381_3,
70*4882a593Smuzhiyun ID_AD5381_5,
71*4882a593Smuzhiyun ID_AD5382_3,
72*4882a593Smuzhiyun ID_AD5382_5,
73*4882a593Smuzhiyun ID_AD5383_3,
74*4882a593Smuzhiyun ID_AD5383_5,
75*4882a593Smuzhiyun ID_AD5390_3,
76*4882a593Smuzhiyun ID_AD5390_5,
77*4882a593Smuzhiyun ID_AD5391_3,
78*4882a593Smuzhiyun ID_AD5391_5,
79*4882a593Smuzhiyun ID_AD5392_3,
80*4882a593Smuzhiyun ID_AD5392_5,
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun
ad5380_read_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,char * buf)83*4882a593Smuzhiyun static ssize_t ad5380_read_dac_powerdown(struct iio_dev *indio_dev,
84*4882a593Smuzhiyun uintptr_t private, const struct iio_chan_spec *chan, char *buf)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun struct ad5380_state *st = iio_priv(indio_dev);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun return sprintf(buf, "%d\n", st->pwr_down);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
ad5380_write_dac_powerdown(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)91*4882a593Smuzhiyun static ssize_t ad5380_write_dac_powerdown(struct iio_dev *indio_dev,
92*4882a593Smuzhiyun uintptr_t private, const struct iio_chan_spec *chan, const char *buf,
93*4882a593Smuzhiyun size_t len)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun struct ad5380_state *st = iio_priv(indio_dev);
96*4882a593Smuzhiyun bool pwr_down;
97*4882a593Smuzhiyun int ret;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun ret = strtobool(buf, &pwr_down);
100*4882a593Smuzhiyun if (ret)
101*4882a593Smuzhiyun return ret;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun mutex_lock(&st->lock);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun if (pwr_down)
106*4882a593Smuzhiyun ret = regmap_write(st->regmap, AD5380_REG_SF_PWR_DOWN, 0);
107*4882a593Smuzhiyun else
108*4882a593Smuzhiyun ret = regmap_write(st->regmap, AD5380_REG_SF_PWR_UP, 0);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun st->pwr_down = pwr_down;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun mutex_unlock(&st->lock);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return ret ? ret : len;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun static const char * const ad5380_powerdown_modes[] = {
118*4882a593Smuzhiyun "100kohm_to_gnd",
119*4882a593Smuzhiyun "three_state",
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun
ad5380_get_powerdown_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)122*4882a593Smuzhiyun static int ad5380_get_powerdown_mode(struct iio_dev *indio_dev,
123*4882a593Smuzhiyun const struct iio_chan_spec *chan)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun struct ad5380_state *st = iio_priv(indio_dev);
126*4882a593Smuzhiyun unsigned int mode;
127*4882a593Smuzhiyun int ret;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun ret = regmap_read(st->regmap, AD5380_REG_SF_CTRL, &mode);
130*4882a593Smuzhiyun if (ret)
131*4882a593Smuzhiyun return ret;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun mode = (mode >> AD5380_CTRL_PWR_DOWN_MODE_OFFSET) & 1;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun return mode;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
ad5380_set_powerdown_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)138*4882a593Smuzhiyun static int ad5380_set_powerdown_mode(struct iio_dev *indio_dev,
139*4882a593Smuzhiyun const struct iio_chan_spec *chan, unsigned int mode)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun struct ad5380_state *st = iio_priv(indio_dev);
142*4882a593Smuzhiyun int ret;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun ret = regmap_update_bits(st->regmap, AD5380_REG_SF_CTRL,
145*4882a593Smuzhiyun 1 << AD5380_CTRL_PWR_DOWN_MODE_OFFSET,
146*4882a593Smuzhiyun mode << AD5380_CTRL_PWR_DOWN_MODE_OFFSET);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun return ret;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun static const struct iio_enum ad5380_powerdown_mode_enum = {
152*4882a593Smuzhiyun .items = ad5380_powerdown_modes,
153*4882a593Smuzhiyun .num_items = ARRAY_SIZE(ad5380_powerdown_modes),
154*4882a593Smuzhiyun .get = ad5380_get_powerdown_mode,
155*4882a593Smuzhiyun .set = ad5380_set_powerdown_mode,
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun
ad5380_info_to_reg(struct iio_chan_spec const * chan,long info)158*4882a593Smuzhiyun static unsigned int ad5380_info_to_reg(struct iio_chan_spec const *chan,
159*4882a593Smuzhiyun long info)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun switch (info) {
162*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
163*4882a593Smuzhiyun return AD5380_REG_DATA(chan->address);
164*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBBIAS:
165*4882a593Smuzhiyun return AD5380_REG_OFFSET(chan->address);
166*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBSCALE:
167*4882a593Smuzhiyun return AD5380_REG_GAIN(chan->address);
168*4882a593Smuzhiyun default:
169*4882a593Smuzhiyun break;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun return 0;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
ad5380_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)175*4882a593Smuzhiyun static int ad5380_write_raw(struct iio_dev *indio_dev,
176*4882a593Smuzhiyun struct iio_chan_spec const *chan, int val, int val2, long info)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun const unsigned int max_val = (1 << chan->scan_type.realbits);
179*4882a593Smuzhiyun struct ad5380_state *st = iio_priv(indio_dev);
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun switch (info) {
182*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
183*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBSCALE:
184*4882a593Smuzhiyun if (val >= max_val || val < 0)
185*4882a593Smuzhiyun return -EINVAL;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun return regmap_write(st->regmap,
188*4882a593Smuzhiyun ad5380_info_to_reg(chan, info),
189*4882a593Smuzhiyun val << chan->scan_type.shift);
190*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBBIAS:
191*4882a593Smuzhiyun val += (1 << chan->scan_type.realbits) / 2;
192*4882a593Smuzhiyun if (val >= max_val || val < 0)
193*4882a593Smuzhiyun return -EINVAL;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun return regmap_write(st->regmap,
196*4882a593Smuzhiyun AD5380_REG_OFFSET(chan->address),
197*4882a593Smuzhiyun val << chan->scan_type.shift);
198*4882a593Smuzhiyun default:
199*4882a593Smuzhiyun break;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun return -EINVAL;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
ad5380_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)204*4882a593Smuzhiyun static int ad5380_read_raw(struct iio_dev *indio_dev,
205*4882a593Smuzhiyun struct iio_chan_spec const *chan, int *val, int *val2, long info)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun struct ad5380_state *st = iio_priv(indio_dev);
208*4882a593Smuzhiyun int ret;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun switch (info) {
211*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
212*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBSCALE:
213*4882a593Smuzhiyun ret = regmap_read(st->regmap, ad5380_info_to_reg(chan, info),
214*4882a593Smuzhiyun val);
215*4882a593Smuzhiyun if (ret)
216*4882a593Smuzhiyun return ret;
217*4882a593Smuzhiyun *val >>= chan->scan_type.shift;
218*4882a593Smuzhiyun return IIO_VAL_INT;
219*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBBIAS:
220*4882a593Smuzhiyun ret = regmap_read(st->regmap, AD5380_REG_OFFSET(chan->address),
221*4882a593Smuzhiyun val);
222*4882a593Smuzhiyun if (ret)
223*4882a593Smuzhiyun return ret;
224*4882a593Smuzhiyun *val >>= chan->scan_type.shift;
225*4882a593Smuzhiyun *val -= (1 << chan->scan_type.realbits) / 2;
226*4882a593Smuzhiyun return IIO_VAL_INT;
227*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
228*4882a593Smuzhiyun *val = 2 * st->vref;
229*4882a593Smuzhiyun *val2 = chan->scan_type.realbits;
230*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL_LOG2;
231*4882a593Smuzhiyun default:
232*4882a593Smuzhiyun break;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun return -EINVAL;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun static const struct iio_info ad5380_info = {
239*4882a593Smuzhiyun .read_raw = ad5380_read_raw,
240*4882a593Smuzhiyun .write_raw = ad5380_write_raw,
241*4882a593Smuzhiyun };
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun static const struct iio_chan_spec_ext_info ad5380_ext_info[] = {
244*4882a593Smuzhiyun {
245*4882a593Smuzhiyun .name = "powerdown",
246*4882a593Smuzhiyun .read = ad5380_read_dac_powerdown,
247*4882a593Smuzhiyun .write = ad5380_write_dac_powerdown,
248*4882a593Smuzhiyun .shared = IIO_SEPARATE,
249*4882a593Smuzhiyun },
250*4882a593Smuzhiyun IIO_ENUM("powerdown_mode", IIO_SHARED_BY_TYPE,
251*4882a593Smuzhiyun &ad5380_powerdown_mode_enum),
252*4882a593Smuzhiyun IIO_ENUM_AVAILABLE("powerdown_mode", &ad5380_powerdown_mode_enum),
253*4882a593Smuzhiyun { },
254*4882a593Smuzhiyun };
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun #define AD5380_CHANNEL(_bits) { \
257*4882a593Smuzhiyun .type = IIO_VOLTAGE, \
258*4882a593Smuzhiyun .indexed = 1, \
259*4882a593Smuzhiyun .output = 1, \
260*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
261*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE) | \
262*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBBIAS), \
263*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
264*4882a593Smuzhiyun .scan_type = { \
265*4882a593Smuzhiyun .sign = 'u', \
266*4882a593Smuzhiyun .realbits = (_bits), \
267*4882a593Smuzhiyun .storagebits = 16, \
268*4882a593Smuzhiyun .shift = 14 - (_bits), \
269*4882a593Smuzhiyun }, \
270*4882a593Smuzhiyun .ext_info = ad5380_ext_info, \
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun static const struct ad5380_chip_info ad5380_chip_info_tbl[] = {
274*4882a593Smuzhiyun [ID_AD5380_3] = {
275*4882a593Smuzhiyun .channel_template = AD5380_CHANNEL(14),
276*4882a593Smuzhiyun .num_channels = 40,
277*4882a593Smuzhiyun .int_vref = 1250,
278*4882a593Smuzhiyun },
279*4882a593Smuzhiyun [ID_AD5380_5] = {
280*4882a593Smuzhiyun .channel_template = AD5380_CHANNEL(14),
281*4882a593Smuzhiyun .num_channels = 40,
282*4882a593Smuzhiyun .int_vref = 2500,
283*4882a593Smuzhiyun },
284*4882a593Smuzhiyun [ID_AD5381_3] = {
285*4882a593Smuzhiyun .channel_template = AD5380_CHANNEL(12),
286*4882a593Smuzhiyun .num_channels = 16,
287*4882a593Smuzhiyun .int_vref = 1250,
288*4882a593Smuzhiyun },
289*4882a593Smuzhiyun [ID_AD5381_5] = {
290*4882a593Smuzhiyun .channel_template = AD5380_CHANNEL(12),
291*4882a593Smuzhiyun .num_channels = 16,
292*4882a593Smuzhiyun .int_vref = 2500,
293*4882a593Smuzhiyun },
294*4882a593Smuzhiyun [ID_AD5382_3] = {
295*4882a593Smuzhiyun .channel_template = AD5380_CHANNEL(14),
296*4882a593Smuzhiyun .num_channels = 32,
297*4882a593Smuzhiyun .int_vref = 1250,
298*4882a593Smuzhiyun },
299*4882a593Smuzhiyun [ID_AD5382_5] = {
300*4882a593Smuzhiyun .channel_template = AD5380_CHANNEL(14),
301*4882a593Smuzhiyun .num_channels = 32,
302*4882a593Smuzhiyun .int_vref = 2500,
303*4882a593Smuzhiyun },
304*4882a593Smuzhiyun [ID_AD5383_3] = {
305*4882a593Smuzhiyun .channel_template = AD5380_CHANNEL(12),
306*4882a593Smuzhiyun .num_channels = 32,
307*4882a593Smuzhiyun .int_vref = 1250,
308*4882a593Smuzhiyun },
309*4882a593Smuzhiyun [ID_AD5383_5] = {
310*4882a593Smuzhiyun .channel_template = AD5380_CHANNEL(12),
311*4882a593Smuzhiyun .num_channels = 32,
312*4882a593Smuzhiyun .int_vref = 2500,
313*4882a593Smuzhiyun },
314*4882a593Smuzhiyun [ID_AD5390_3] = {
315*4882a593Smuzhiyun .channel_template = AD5380_CHANNEL(14),
316*4882a593Smuzhiyun .num_channels = 16,
317*4882a593Smuzhiyun .int_vref = 1250,
318*4882a593Smuzhiyun },
319*4882a593Smuzhiyun [ID_AD5390_5] = {
320*4882a593Smuzhiyun .channel_template = AD5380_CHANNEL(14),
321*4882a593Smuzhiyun .num_channels = 16,
322*4882a593Smuzhiyun .int_vref = 2500,
323*4882a593Smuzhiyun },
324*4882a593Smuzhiyun [ID_AD5391_3] = {
325*4882a593Smuzhiyun .channel_template = AD5380_CHANNEL(12),
326*4882a593Smuzhiyun .num_channels = 16,
327*4882a593Smuzhiyun .int_vref = 1250,
328*4882a593Smuzhiyun },
329*4882a593Smuzhiyun [ID_AD5391_5] = {
330*4882a593Smuzhiyun .channel_template = AD5380_CHANNEL(12),
331*4882a593Smuzhiyun .num_channels = 16,
332*4882a593Smuzhiyun .int_vref = 2500,
333*4882a593Smuzhiyun },
334*4882a593Smuzhiyun [ID_AD5392_3] = {
335*4882a593Smuzhiyun .channel_template = AD5380_CHANNEL(14),
336*4882a593Smuzhiyun .num_channels = 8,
337*4882a593Smuzhiyun .int_vref = 1250,
338*4882a593Smuzhiyun },
339*4882a593Smuzhiyun [ID_AD5392_5] = {
340*4882a593Smuzhiyun .channel_template = AD5380_CHANNEL(14),
341*4882a593Smuzhiyun .num_channels = 8,
342*4882a593Smuzhiyun .int_vref = 2500,
343*4882a593Smuzhiyun },
344*4882a593Smuzhiyun };
345*4882a593Smuzhiyun
ad5380_alloc_channels(struct iio_dev * indio_dev)346*4882a593Smuzhiyun static int ad5380_alloc_channels(struct iio_dev *indio_dev)
347*4882a593Smuzhiyun {
348*4882a593Smuzhiyun struct ad5380_state *st = iio_priv(indio_dev);
349*4882a593Smuzhiyun struct iio_chan_spec *channels;
350*4882a593Smuzhiyun unsigned int i;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun channels = kcalloc(st->chip_info->num_channels,
353*4882a593Smuzhiyun sizeof(struct iio_chan_spec), GFP_KERNEL);
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun if (!channels)
356*4882a593Smuzhiyun return -ENOMEM;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun for (i = 0; i < st->chip_info->num_channels; ++i) {
359*4882a593Smuzhiyun channels[i] = st->chip_info->channel_template;
360*4882a593Smuzhiyun channels[i].channel = i;
361*4882a593Smuzhiyun channels[i].address = i;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun indio_dev->channels = channels;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun return 0;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun
ad5380_probe(struct device * dev,struct regmap * regmap,enum ad5380_type type,const char * name)369*4882a593Smuzhiyun static int ad5380_probe(struct device *dev, struct regmap *regmap,
370*4882a593Smuzhiyun enum ad5380_type type, const char *name)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun struct iio_dev *indio_dev;
373*4882a593Smuzhiyun struct ad5380_state *st;
374*4882a593Smuzhiyun unsigned int ctrl = 0;
375*4882a593Smuzhiyun int ret;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
378*4882a593Smuzhiyun if (indio_dev == NULL) {
379*4882a593Smuzhiyun dev_err(dev, "Failed to allocate iio device\n");
380*4882a593Smuzhiyun return -ENOMEM;
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun st = iio_priv(indio_dev);
384*4882a593Smuzhiyun dev_set_drvdata(dev, indio_dev);
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun st->chip_info = &ad5380_chip_info_tbl[type];
387*4882a593Smuzhiyun st->regmap = regmap;
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun indio_dev->name = name;
390*4882a593Smuzhiyun indio_dev->info = &ad5380_info;
391*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
392*4882a593Smuzhiyun indio_dev->num_channels = st->chip_info->num_channels;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun mutex_init(&st->lock);
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun ret = ad5380_alloc_channels(indio_dev);
397*4882a593Smuzhiyun if (ret) {
398*4882a593Smuzhiyun dev_err(dev, "Failed to allocate channel spec: %d\n", ret);
399*4882a593Smuzhiyun return ret;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun if (st->chip_info->int_vref == 2500)
403*4882a593Smuzhiyun ctrl |= AD5380_CTRL_INT_VREF_2V5;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun st->vref_reg = devm_regulator_get(dev, "vref");
406*4882a593Smuzhiyun if (!IS_ERR(st->vref_reg)) {
407*4882a593Smuzhiyun ret = regulator_enable(st->vref_reg);
408*4882a593Smuzhiyun if (ret) {
409*4882a593Smuzhiyun dev_err(dev, "Failed to enable vref regulators: %d\n",
410*4882a593Smuzhiyun ret);
411*4882a593Smuzhiyun goto error_free_reg;
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun ret = regulator_get_voltage(st->vref_reg);
415*4882a593Smuzhiyun if (ret < 0)
416*4882a593Smuzhiyun goto error_disable_reg;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun st->vref = ret / 1000;
419*4882a593Smuzhiyun } else {
420*4882a593Smuzhiyun st->vref = st->chip_info->int_vref;
421*4882a593Smuzhiyun ctrl |= AD5380_CTRL_INT_VREF_EN;
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun ret = regmap_write(st->regmap, AD5380_REG_SF_CTRL, ctrl);
425*4882a593Smuzhiyun if (ret) {
426*4882a593Smuzhiyun dev_err(dev, "Failed to write to device: %d\n", ret);
427*4882a593Smuzhiyun goto error_disable_reg;
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
431*4882a593Smuzhiyun if (ret) {
432*4882a593Smuzhiyun dev_err(dev, "Failed to register iio device: %d\n", ret);
433*4882a593Smuzhiyun goto error_disable_reg;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun return 0;
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun error_disable_reg:
439*4882a593Smuzhiyun if (!IS_ERR(st->vref_reg))
440*4882a593Smuzhiyun regulator_disable(st->vref_reg);
441*4882a593Smuzhiyun error_free_reg:
442*4882a593Smuzhiyun kfree(indio_dev->channels);
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun return ret;
445*4882a593Smuzhiyun }
446*4882a593Smuzhiyun
ad5380_remove(struct device * dev)447*4882a593Smuzhiyun static int ad5380_remove(struct device *dev)
448*4882a593Smuzhiyun {
449*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_get_drvdata(dev);
450*4882a593Smuzhiyun struct ad5380_state *st = iio_priv(indio_dev);
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun iio_device_unregister(indio_dev);
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun kfree(indio_dev->channels);
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun if (!IS_ERR(st->vref_reg)) {
457*4882a593Smuzhiyun regulator_disable(st->vref_reg);
458*4882a593Smuzhiyun }
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun return 0;
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun
ad5380_reg_false(struct device * dev,unsigned int reg)463*4882a593Smuzhiyun static bool ad5380_reg_false(struct device *dev, unsigned int reg)
464*4882a593Smuzhiyun {
465*4882a593Smuzhiyun return false;
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun static const struct regmap_config ad5380_regmap_config = {
469*4882a593Smuzhiyun .reg_bits = 10,
470*4882a593Smuzhiyun .val_bits = 14,
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun .max_register = AD5380_REG_DATA(40),
473*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun .volatile_reg = ad5380_reg_false,
476*4882a593Smuzhiyun .readable_reg = ad5380_reg_false,
477*4882a593Smuzhiyun };
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_SPI_MASTER)
480*4882a593Smuzhiyun
ad5380_spi_probe(struct spi_device * spi)481*4882a593Smuzhiyun static int ad5380_spi_probe(struct spi_device *spi)
482*4882a593Smuzhiyun {
483*4882a593Smuzhiyun const struct spi_device_id *id = spi_get_device_id(spi);
484*4882a593Smuzhiyun struct regmap *regmap;
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun regmap = devm_regmap_init_spi(spi, &ad5380_regmap_config);
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun if (IS_ERR(regmap))
489*4882a593Smuzhiyun return PTR_ERR(regmap);
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun return ad5380_probe(&spi->dev, regmap, id->driver_data, id->name);
492*4882a593Smuzhiyun }
493*4882a593Smuzhiyun
ad5380_spi_remove(struct spi_device * spi)494*4882a593Smuzhiyun static int ad5380_spi_remove(struct spi_device *spi)
495*4882a593Smuzhiyun {
496*4882a593Smuzhiyun return ad5380_remove(&spi->dev);
497*4882a593Smuzhiyun }
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun static const struct spi_device_id ad5380_spi_ids[] = {
500*4882a593Smuzhiyun { "ad5380-3", ID_AD5380_3 },
501*4882a593Smuzhiyun { "ad5380-5", ID_AD5380_5 },
502*4882a593Smuzhiyun { "ad5381-3", ID_AD5381_3 },
503*4882a593Smuzhiyun { "ad5381-5", ID_AD5381_5 },
504*4882a593Smuzhiyun { "ad5382-3", ID_AD5382_3 },
505*4882a593Smuzhiyun { "ad5382-5", ID_AD5382_5 },
506*4882a593Smuzhiyun { "ad5383-3", ID_AD5383_3 },
507*4882a593Smuzhiyun { "ad5383-5", ID_AD5383_5 },
508*4882a593Smuzhiyun { "ad5384-3", ID_AD5380_3 },
509*4882a593Smuzhiyun { "ad5384-5", ID_AD5380_5 },
510*4882a593Smuzhiyun { "ad5390-3", ID_AD5390_3 },
511*4882a593Smuzhiyun { "ad5390-5", ID_AD5390_5 },
512*4882a593Smuzhiyun { "ad5391-3", ID_AD5391_3 },
513*4882a593Smuzhiyun { "ad5391-5", ID_AD5391_5 },
514*4882a593Smuzhiyun { "ad5392-3", ID_AD5392_3 },
515*4882a593Smuzhiyun { "ad5392-5", ID_AD5392_5 },
516*4882a593Smuzhiyun { }
517*4882a593Smuzhiyun };
518*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ad5380_spi_ids);
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun static struct spi_driver ad5380_spi_driver = {
521*4882a593Smuzhiyun .driver = {
522*4882a593Smuzhiyun .name = "ad5380",
523*4882a593Smuzhiyun },
524*4882a593Smuzhiyun .probe = ad5380_spi_probe,
525*4882a593Smuzhiyun .remove = ad5380_spi_remove,
526*4882a593Smuzhiyun .id_table = ad5380_spi_ids,
527*4882a593Smuzhiyun };
528*4882a593Smuzhiyun
ad5380_spi_register_driver(void)529*4882a593Smuzhiyun static inline int ad5380_spi_register_driver(void)
530*4882a593Smuzhiyun {
531*4882a593Smuzhiyun return spi_register_driver(&ad5380_spi_driver);
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun
ad5380_spi_unregister_driver(void)534*4882a593Smuzhiyun static inline void ad5380_spi_unregister_driver(void)
535*4882a593Smuzhiyun {
536*4882a593Smuzhiyun spi_unregister_driver(&ad5380_spi_driver);
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun #else
540*4882a593Smuzhiyun
ad5380_spi_register_driver(void)541*4882a593Smuzhiyun static inline int ad5380_spi_register_driver(void)
542*4882a593Smuzhiyun {
543*4882a593Smuzhiyun return 0;
544*4882a593Smuzhiyun }
545*4882a593Smuzhiyun
ad5380_spi_unregister_driver(void)546*4882a593Smuzhiyun static inline void ad5380_spi_unregister_driver(void)
547*4882a593Smuzhiyun {
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun #endif
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_I2C)
553*4882a593Smuzhiyun
ad5380_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)554*4882a593Smuzhiyun static int ad5380_i2c_probe(struct i2c_client *i2c,
555*4882a593Smuzhiyun const struct i2c_device_id *id)
556*4882a593Smuzhiyun {
557*4882a593Smuzhiyun struct regmap *regmap;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun regmap = devm_regmap_init_i2c(i2c, &ad5380_regmap_config);
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun if (IS_ERR(regmap))
562*4882a593Smuzhiyun return PTR_ERR(regmap);
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun return ad5380_probe(&i2c->dev, regmap, id->driver_data, id->name);
565*4882a593Smuzhiyun }
566*4882a593Smuzhiyun
ad5380_i2c_remove(struct i2c_client * i2c)567*4882a593Smuzhiyun static int ad5380_i2c_remove(struct i2c_client *i2c)
568*4882a593Smuzhiyun {
569*4882a593Smuzhiyun return ad5380_remove(&i2c->dev);
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun static const struct i2c_device_id ad5380_i2c_ids[] = {
573*4882a593Smuzhiyun { "ad5380-3", ID_AD5380_3 },
574*4882a593Smuzhiyun { "ad5380-5", ID_AD5380_5 },
575*4882a593Smuzhiyun { "ad5381-3", ID_AD5381_3 },
576*4882a593Smuzhiyun { "ad5381-5", ID_AD5381_5 },
577*4882a593Smuzhiyun { "ad5382-3", ID_AD5382_3 },
578*4882a593Smuzhiyun { "ad5382-5", ID_AD5382_5 },
579*4882a593Smuzhiyun { "ad5383-3", ID_AD5383_3 },
580*4882a593Smuzhiyun { "ad5383-5", ID_AD5383_5 },
581*4882a593Smuzhiyun { "ad5384-3", ID_AD5380_3 },
582*4882a593Smuzhiyun { "ad5384-5", ID_AD5380_5 },
583*4882a593Smuzhiyun { "ad5390-3", ID_AD5390_3 },
584*4882a593Smuzhiyun { "ad5390-5", ID_AD5390_5 },
585*4882a593Smuzhiyun { "ad5391-3", ID_AD5391_3 },
586*4882a593Smuzhiyun { "ad5391-5", ID_AD5391_5 },
587*4882a593Smuzhiyun { "ad5392-3", ID_AD5392_3 },
588*4882a593Smuzhiyun { "ad5392-5", ID_AD5392_5 },
589*4882a593Smuzhiyun { }
590*4882a593Smuzhiyun };
591*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, ad5380_i2c_ids);
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun static struct i2c_driver ad5380_i2c_driver = {
594*4882a593Smuzhiyun .driver = {
595*4882a593Smuzhiyun .name = "ad5380",
596*4882a593Smuzhiyun },
597*4882a593Smuzhiyun .probe = ad5380_i2c_probe,
598*4882a593Smuzhiyun .remove = ad5380_i2c_remove,
599*4882a593Smuzhiyun .id_table = ad5380_i2c_ids,
600*4882a593Smuzhiyun };
601*4882a593Smuzhiyun
ad5380_i2c_register_driver(void)602*4882a593Smuzhiyun static inline int ad5380_i2c_register_driver(void)
603*4882a593Smuzhiyun {
604*4882a593Smuzhiyun return i2c_add_driver(&ad5380_i2c_driver);
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun
ad5380_i2c_unregister_driver(void)607*4882a593Smuzhiyun static inline void ad5380_i2c_unregister_driver(void)
608*4882a593Smuzhiyun {
609*4882a593Smuzhiyun i2c_del_driver(&ad5380_i2c_driver);
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun #else
613*4882a593Smuzhiyun
ad5380_i2c_register_driver(void)614*4882a593Smuzhiyun static inline int ad5380_i2c_register_driver(void)
615*4882a593Smuzhiyun {
616*4882a593Smuzhiyun return 0;
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun
ad5380_i2c_unregister_driver(void)619*4882a593Smuzhiyun static inline void ad5380_i2c_unregister_driver(void)
620*4882a593Smuzhiyun {
621*4882a593Smuzhiyun }
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun #endif
624*4882a593Smuzhiyun
ad5380_spi_init(void)625*4882a593Smuzhiyun static int __init ad5380_spi_init(void)
626*4882a593Smuzhiyun {
627*4882a593Smuzhiyun int ret;
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun ret = ad5380_spi_register_driver();
630*4882a593Smuzhiyun if (ret)
631*4882a593Smuzhiyun return ret;
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun ret = ad5380_i2c_register_driver();
634*4882a593Smuzhiyun if (ret) {
635*4882a593Smuzhiyun ad5380_spi_unregister_driver();
636*4882a593Smuzhiyun return ret;
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun return 0;
640*4882a593Smuzhiyun }
641*4882a593Smuzhiyun module_init(ad5380_spi_init);
642*4882a593Smuzhiyun
ad5380_spi_exit(void)643*4882a593Smuzhiyun static void __exit ad5380_spi_exit(void)
644*4882a593Smuzhiyun {
645*4882a593Smuzhiyun ad5380_i2c_unregister_driver();
646*4882a593Smuzhiyun ad5380_spi_unregister_driver();
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun }
649*4882a593Smuzhiyun module_exit(ad5380_spi_exit);
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
652*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices AD5380/81/82/83/84/90/91/92 DAC");
653*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
654