1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * TI ADC108S102 SPI ADC driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2013-2015 Intel Corporation.
6*4882a593Smuzhiyun * Copyright (c) 2017 Siemens AG
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This IIO device driver is designed to work with the following
9*4882a593Smuzhiyun * analog to digital converters from Texas Instruments:
10*4882a593Smuzhiyun * ADC108S102
11*4882a593Smuzhiyun * ADC128S102
12*4882a593Smuzhiyun * The communication with ADC chip is via the SPI bus (mode 3).
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/acpi.h>
16*4882a593Smuzhiyun #include <linux/iio/iio.h>
17*4882a593Smuzhiyun #include <linux/iio/buffer.h>
18*4882a593Smuzhiyun #include <linux/iio/types.h>
19*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
20*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
21*4882a593Smuzhiyun #include <linux/interrupt.h>
22*4882a593Smuzhiyun #include <linux/module.h>
23*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
24*4882a593Smuzhiyun #include <linux/property.h>
25*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
26*4882a593Smuzhiyun #include <linux/spi/spi.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun * In case of ACPI, we use the hard-wired 5000 mV of the Galileo and IOT2000
30*4882a593Smuzhiyun * boards as default for the reference pin VA. Device tree users encode that
31*4882a593Smuzhiyun * via the vref-supply regulator.
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun #define ADC108S102_VA_MV_ACPI_DEFAULT 5000
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun * Defining the ADC resolution being 12 bits, we can use the same driver for
37*4882a593Smuzhiyun * both ADC108S102 (10 bits resolution) and ADC128S102 (12 bits resolution)
38*4882a593Smuzhiyun * chips. The ADC108S102 effectively returns a 12-bit result with the 2
39*4882a593Smuzhiyun * least-significant bits unset.
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun #define ADC108S102_BITS 12
42*4882a593Smuzhiyun #define ADC108S102_MAX_CHANNELS 8
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /*
45*4882a593Smuzhiyun * 16-bit SPI command format:
46*4882a593Smuzhiyun * [15:14] Ignored
47*4882a593Smuzhiyun * [13:11] 3-bit channel address
48*4882a593Smuzhiyun * [10:0] Ignored
49*4882a593Smuzhiyun */
50*4882a593Smuzhiyun #define ADC108S102_CMD(ch) ((u16)(ch) << 11)
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /*
53*4882a593Smuzhiyun * 16-bit SPI response format:
54*4882a593Smuzhiyun * [15:12] Zeros
55*4882a593Smuzhiyun * [11:0] 12-bit ADC sample (for ADC108S102, [1:0] will always be 0).
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun #define ADC108S102_RES_DATA(res) ((u16)res & GENMASK(11, 0))
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun struct adc108s102_state {
60*4882a593Smuzhiyun struct spi_device *spi;
61*4882a593Smuzhiyun struct regulator *reg;
62*4882a593Smuzhiyun u32 va_millivolt;
63*4882a593Smuzhiyun /* SPI transfer used by triggered buffer handler*/
64*4882a593Smuzhiyun struct spi_transfer ring_xfer;
65*4882a593Smuzhiyun /* SPI transfer used by direct scan */
66*4882a593Smuzhiyun struct spi_transfer scan_single_xfer;
67*4882a593Smuzhiyun /* SPI message used by ring_xfer SPI transfer */
68*4882a593Smuzhiyun struct spi_message ring_msg;
69*4882a593Smuzhiyun /* SPI message used by scan_single_xfer SPI transfer */
70*4882a593Smuzhiyun struct spi_message scan_single_msg;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /*
73*4882a593Smuzhiyun * SPI message buffers:
74*4882a593Smuzhiyun * tx_buf: |C0|C1|C2|C3|C4|C5|C6|C7|XX|
75*4882a593Smuzhiyun * rx_buf: |XX|R0|R1|R2|R3|R4|R5|R6|R7|tt|tt|tt|tt|
76*4882a593Smuzhiyun *
77*4882a593Smuzhiyun * tx_buf: 8 channel read commands, plus 1 dummy command
78*4882a593Smuzhiyun * rx_buf: 1 dummy response, 8 channel responses, plus 64-bit timestamp
79*4882a593Smuzhiyun */
80*4882a593Smuzhiyun __be16 rx_buf[13] ____cacheline_aligned;
81*4882a593Smuzhiyun __be16 tx_buf[9] ____cacheline_aligned;
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun #define ADC108S102_V_CHAN(index) \
85*4882a593Smuzhiyun { \
86*4882a593Smuzhiyun .type = IIO_VOLTAGE, \
87*4882a593Smuzhiyun .indexed = 1, \
88*4882a593Smuzhiyun .channel = index, \
89*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
90*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE), \
91*4882a593Smuzhiyun .address = index, \
92*4882a593Smuzhiyun .scan_index = index, \
93*4882a593Smuzhiyun .scan_type = { \
94*4882a593Smuzhiyun .sign = 'u', \
95*4882a593Smuzhiyun .realbits = ADC108S102_BITS, \
96*4882a593Smuzhiyun .storagebits = 16, \
97*4882a593Smuzhiyun .endianness = IIO_BE, \
98*4882a593Smuzhiyun }, \
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun static const struct iio_chan_spec adc108s102_channels[] = {
102*4882a593Smuzhiyun ADC108S102_V_CHAN(0),
103*4882a593Smuzhiyun ADC108S102_V_CHAN(1),
104*4882a593Smuzhiyun ADC108S102_V_CHAN(2),
105*4882a593Smuzhiyun ADC108S102_V_CHAN(3),
106*4882a593Smuzhiyun ADC108S102_V_CHAN(4),
107*4882a593Smuzhiyun ADC108S102_V_CHAN(5),
108*4882a593Smuzhiyun ADC108S102_V_CHAN(6),
109*4882a593Smuzhiyun ADC108S102_V_CHAN(7),
110*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(8),
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
adc108s102_update_scan_mode(struct iio_dev * indio_dev,unsigned long const * active_scan_mask)113*4882a593Smuzhiyun static int adc108s102_update_scan_mode(struct iio_dev *indio_dev,
114*4882a593Smuzhiyun unsigned long const *active_scan_mask)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun struct adc108s102_state *st = iio_priv(indio_dev);
117*4882a593Smuzhiyun unsigned int bit, cmds;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun /*
120*4882a593Smuzhiyun * Fill in the first x shorts of tx_buf with the number of channels
121*4882a593Smuzhiyun * enabled for sampling by the triggered buffer.
122*4882a593Smuzhiyun */
123*4882a593Smuzhiyun cmds = 0;
124*4882a593Smuzhiyun for_each_set_bit(bit, active_scan_mask, ADC108S102_MAX_CHANNELS)
125*4882a593Smuzhiyun st->tx_buf[cmds++] = cpu_to_be16(ADC108S102_CMD(bit));
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun /* One dummy command added, to clock in the last response */
128*4882a593Smuzhiyun st->tx_buf[cmds++] = 0x00;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /* build SPI ring message */
131*4882a593Smuzhiyun st->ring_xfer.tx_buf = &st->tx_buf[0];
132*4882a593Smuzhiyun st->ring_xfer.rx_buf = &st->rx_buf[0];
133*4882a593Smuzhiyun st->ring_xfer.len = cmds * sizeof(st->tx_buf[0]);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun spi_message_init_with_transfers(&st->ring_msg, &st->ring_xfer, 1);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun return 0;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
adc108s102_trigger_handler(int irq,void * p)140*4882a593Smuzhiyun static irqreturn_t adc108s102_trigger_handler(int irq, void *p)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun struct iio_poll_func *pf = p;
143*4882a593Smuzhiyun struct iio_dev *indio_dev = pf->indio_dev;
144*4882a593Smuzhiyun struct adc108s102_state *st = iio_priv(indio_dev);
145*4882a593Smuzhiyun int ret;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun ret = spi_sync(st->spi, &st->ring_msg);
148*4882a593Smuzhiyun if (ret < 0)
149*4882a593Smuzhiyun goto out_notify;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun /* Skip the dummy response in the first slot */
152*4882a593Smuzhiyun iio_push_to_buffers_with_timestamp(indio_dev,
153*4882a593Smuzhiyun (u8 *)&st->rx_buf[1],
154*4882a593Smuzhiyun iio_get_time_ns(indio_dev));
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun out_notify:
157*4882a593Smuzhiyun iio_trigger_notify_done(indio_dev->trig);
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun return IRQ_HANDLED;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
adc108s102_scan_direct(struct adc108s102_state * st,unsigned int ch)162*4882a593Smuzhiyun static int adc108s102_scan_direct(struct adc108s102_state *st, unsigned int ch)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun int ret;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun st->tx_buf[0] = cpu_to_be16(ADC108S102_CMD(ch));
167*4882a593Smuzhiyun ret = spi_sync(st->spi, &st->scan_single_msg);
168*4882a593Smuzhiyun if (ret)
169*4882a593Smuzhiyun return ret;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun /* Skip the dummy response in the first slot */
172*4882a593Smuzhiyun return be16_to_cpu(st->rx_buf[1]);
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
adc108s102_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)175*4882a593Smuzhiyun static int adc108s102_read_raw(struct iio_dev *indio_dev,
176*4882a593Smuzhiyun struct iio_chan_spec const *chan,
177*4882a593Smuzhiyun int *val, int *val2, long m)
178*4882a593Smuzhiyun {
179*4882a593Smuzhiyun struct adc108s102_state *st = iio_priv(indio_dev);
180*4882a593Smuzhiyun int ret;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun switch (m) {
183*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
184*4882a593Smuzhiyun ret = iio_device_claim_direct_mode(indio_dev);
185*4882a593Smuzhiyun if (ret)
186*4882a593Smuzhiyun return ret;
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun ret = adc108s102_scan_direct(st, chan->address);
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun iio_device_release_direct_mode(indio_dev);
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun if (ret < 0)
193*4882a593Smuzhiyun return ret;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun *val = ADC108S102_RES_DATA(ret);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun return IIO_VAL_INT;
198*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
199*4882a593Smuzhiyun if (chan->type != IIO_VOLTAGE)
200*4882a593Smuzhiyun break;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun *val = st->va_millivolt;
203*4882a593Smuzhiyun *val2 = chan->scan_type.realbits;
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL_LOG2;
206*4882a593Smuzhiyun default:
207*4882a593Smuzhiyun break;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun return -EINVAL;
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun static const struct iio_info adc108s102_info = {
214*4882a593Smuzhiyun .read_raw = &adc108s102_read_raw,
215*4882a593Smuzhiyun .update_scan_mode = &adc108s102_update_scan_mode,
216*4882a593Smuzhiyun };
217*4882a593Smuzhiyun
adc108s102_probe(struct spi_device * spi)218*4882a593Smuzhiyun static int adc108s102_probe(struct spi_device *spi)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun struct adc108s102_state *st;
221*4882a593Smuzhiyun struct iio_dev *indio_dev;
222*4882a593Smuzhiyun int ret;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
225*4882a593Smuzhiyun if (!indio_dev)
226*4882a593Smuzhiyun return -ENOMEM;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun st = iio_priv(indio_dev);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun if (ACPI_COMPANION(&spi->dev)) {
231*4882a593Smuzhiyun st->va_millivolt = ADC108S102_VA_MV_ACPI_DEFAULT;
232*4882a593Smuzhiyun } else {
233*4882a593Smuzhiyun st->reg = devm_regulator_get(&spi->dev, "vref");
234*4882a593Smuzhiyun if (IS_ERR(st->reg))
235*4882a593Smuzhiyun return PTR_ERR(st->reg);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun ret = regulator_enable(st->reg);
238*4882a593Smuzhiyun if (ret < 0) {
239*4882a593Smuzhiyun dev_err(&spi->dev, "Cannot enable vref regulator\n");
240*4882a593Smuzhiyun return ret;
241*4882a593Smuzhiyun }
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun ret = regulator_get_voltage(st->reg);
244*4882a593Smuzhiyun if (ret < 0) {
245*4882a593Smuzhiyun dev_err(&spi->dev, "vref get voltage failed\n");
246*4882a593Smuzhiyun return ret;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun st->va_millivolt = ret / 1000;
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun spi_set_drvdata(spi, indio_dev);
253*4882a593Smuzhiyun st->spi = spi;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun indio_dev->name = spi->modalias;
256*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
257*4882a593Smuzhiyun indio_dev->channels = adc108s102_channels;
258*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(adc108s102_channels);
259*4882a593Smuzhiyun indio_dev->info = &adc108s102_info;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun /* Setup default message */
262*4882a593Smuzhiyun st->scan_single_xfer.tx_buf = st->tx_buf;
263*4882a593Smuzhiyun st->scan_single_xfer.rx_buf = st->rx_buf;
264*4882a593Smuzhiyun st->scan_single_xfer.len = 2 * sizeof(st->tx_buf[0]);
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun spi_message_init_with_transfers(&st->scan_single_msg,
267*4882a593Smuzhiyun &st->scan_single_xfer, 1);
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun ret = iio_triggered_buffer_setup(indio_dev, NULL,
270*4882a593Smuzhiyun &adc108s102_trigger_handler, NULL);
271*4882a593Smuzhiyun if (ret)
272*4882a593Smuzhiyun goto error_disable_reg;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
275*4882a593Smuzhiyun if (ret) {
276*4882a593Smuzhiyun dev_err(&spi->dev, "Failed to register IIO device\n");
277*4882a593Smuzhiyun goto error_cleanup_triggered_buffer;
278*4882a593Smuzhiyun }
279*4882a593Smuzhiyun return 0;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun error_cleanup_triggered_buffer:
282*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun error_disable_reg:
285*4882a593Smuzhiyun regulator_disable(st->reg);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun return ret;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
adc108s102_remove(struct spi_device * spi)290*4882a593Smuzhiyun static int adc108s102_remove(struct spi_device *spi)
291*4882a593Smuzhiyun {
292*4882a593Smuzhiyun struct iio_dev *indio_dev = spi_get_drvdata(spi);
293*4882a593Smuzhiyun struct adc108s102_state *st = iio_priv(indio_dev);
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun iio_device_unregister(indio_dev);
296*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun regulator_disable(st->reg);
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun return 0;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun static const struct of_device_id adc108s102_of_match[] = {
304*4882a593Smuzhiyun { .compatible = "ti,adc108s102" },
305*4882a593Smuzhiyun { }
306*4882a593Smuzhiyun };
307*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, adc108s102_of_match);
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun #ifdef CONFIG_ACPI
310*4882a593Smuzhiyun static const struct acpi_device_id adc108s102_acpi_ids[] = {
311*4882a593Smuzhiyun { "INT3495", 0 },
312*4882a593Smuzhiyun { }
313*4882a593Smuzhiyun };
314*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, adc108s102_acpi_ids);
315*4882a593Smuzhiyun #endif
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun static const struct spi_device_id adc108s102_id[] = {
318*4882a593Smuzhiyun { "adc108s102", 0 },
319*4882a593Smuzhiyun { }
320*4882a593Smuzhiyun };
321*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, adc108s102_id);
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun static struct spi_driver adc108s102_driver = {
324*4882a593Smuzhiyun .driver = {
325*4882a593Smuzhiyun .name = "adc108s102",
326*4882a593Smuzhiyun .of_match_table = adc108s102_of_match,
327*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(adc108s102_acpi_ids),
328*4882a593Smuzhiyun },
329*4882a593Smuzhiyun .probe = adc108s102_probe,
330*4882a593Smuzhiyun .remove = adc108s102_remove,
331*4882a593Smuzhiyun .id_table = adc108s102_id,
332*4882a593Smuzhiyun };
333*4882a593Smuzhiyun module_spi_driver(adc108s102_driver);
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun MODULE_AUTHOR("Bogdan Pricop <bogdan.pricop@emutex.com>");
336*4882a593Smuzhiyun MODULE_DESCRIPTION("Texas Instruments ADC108S102 and ADC128S102 driver");
337*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
338