xref: /OK3568_Linux_fs/kernel/drivers/iio/adc/ti-adc084s021.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /**
3*4882a593Smuzhiyun  * Copyright (C) 2017 Axis Communications AB
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Driver for Texas Instruments' ADC084S021 ADC chip.
6*4882a593Smuzhiyun  * Datasheets can be found here:
7*4882a593Smuzhiyun  * https://www.ti.com/lit/ds/symlink/adc084s021.pdf
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/err.h>
11*4882a593Smuzhiyun #include <linux/spi/spi.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
14*4882a593Smuzhiyun #include <linux/interrupt.h>
15*4882a593Smuzhiyun #include <linux/iio/iio.h>
16*4882a593Smuzhiyun #include <linux/iio/buffer.h>
17*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
18*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
19*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define ADC084S021_DRIVER_NAME "adc084s021"
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun struct adc084s021 {
24*4882a593Smuzhiyun 	struct spi_device *spi;
25*4882a593Smuzhiyun 	struct spi_message message;
26*4882a593Smuzhiyun 	struct spi_transfer spi_trans;
27*4882a593Smuzhiyun 	struct regulator *reg;
28*4882a593Smuzhiyun 	struct mutex lock;
29*4882a593Smuzhiyun 	/* Buffer used to align data */
30*4882a593Smuzhiyun 	struct {
31*4882a593Smuzhiyun 		__be16 channels[4];
32*4882a593Smuzhiyun 		s64 ts __aligned(8);
33*4882a593Smuzhiyun 	} scan;
34*4882a593Smuzhiyun 	/*
35*4882a593Smuzhiyun 	 * DMA (thus cache coherency maintenance) requires the
36*4882a593Smuzhiyun 	 * transfer buffers to live in their own cache line.
37*4882a593Smuzhiyun 	 */
38*4882a593Smuzhiyun 	u16 tx_buf[4] ____cacheline_aligned;
39*4882a593Smuzhiyun 	__be16 rx_buf[5]; /* First 16-bits are trash */
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #define ADC084S021_VOLTAGE_CHANNEL(num)                  \
43*4882a593Smuzhiyun 	{                                                      \
44*4882a593Smuzhiyun 		.type = IIO_VOLTAGE,                                 \
45*4882a593Smuzhiyun 		.channel = (num),                                    \
46*4882a593Smuzhiyun 		.indexed = 1,                                        \
47*4882a593Smuzhiyun 		.scan_index = (num),                                 \
48*4882a593Smuzhiyun 		.scan_type = {                                       \
49*4882a593Smuzhiyun 			.sign = 'u',                                       \
50*4882a593Smuzhiyun 			.realbits = 8,                                     \
51*4882a593Smuzhiyun 			.storagebits = 16,                                 \
52*4882a593Smuzhiyun 			.shift = 4,                                        \
53*4882a593Smuzhiyun 			.endianness = IIO_BE,                              \
54*4882a593Smuzhiyun 		},                                                   \
55*4882a593Smuzhiyun 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),        \
56*4882a593Smuzhiyun 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),\
57*4882a593Smuzhiyun 	}
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun static const struct iio_chan_spec adc084s021_channels[] = {
60*4882a593Smuzhiyun 	ADC084S021_VOLTAGE_CHANNEL(0),
61*4882a593Smuzhiyun 	ADC084S021_VOLTAGE_CHANNEL(1),
62*4882a593Smuzhiyun 	ADC084S021_VOLTAGE_CHANNEL(2),
63*4882a593Smuzhiyun 	ADC084S021_VOLTAGE_CHANNEL(3),
64*4882a593Smuzhiyun 	IIO_CHAN_SOFT_TIMESTAMP(4),
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun /**
68*4882a593Smuzhiyun  * Read an ADC channel and return its value.
69*4882a593Smuzhiyun  *
70*4882a593Smuzhiyun  * @adc: The ADC SPI data.
71*4882a593Smuzhiyun  * @data: Buffer for converted data.
72*4882a593Smuzhiyun  */
adc084s021_adc_conversion(struct adc084s021 * adc,void * data)73*4882a593Smuzhiyun static int adc084s021_adc_conversion(struct adc084s021 *adc, void *data)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun 	int n_words = (adc->spi_trans.len >> 1) - 1; /* Discard first word */
76*4882a593Smuzhiyun 	int ret, i = 0;
77*4882a593Smuzhiyun 	u16 *p = data;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	/* Do the transfer */
80*4882a593Smuzhiyun 	ret = spi_sync(adc->spi, &adc->message);
81*4882a593Smuzhiyun 	if (ret < 0)
82*4882a593Smuzhiyun 		return ret;
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 	for (; i < n_words; i++)
85*4882a593Smuzhiyun 		*(p + i) = adc->rx_buf[i + 1];
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	return ret;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun 
adc084s021_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * channel,int * val,int * val2,long mask)90*4882a593Smuzhiyun static int adc084s021_read_raw(struct iio_dev *indio_dev,
91*4882a593Smuzhiyun 			   struct iio_chan_spec const *channel, int *val,
92*4882a593Smuzhiyun 			   int *val2, long mask)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun 	struct adc084s021 *adc = iio_priv(indio_dev);
95*4882a593Smuzhiyun 	int ret;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	switch (mask) {
98*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
99*4882a593Smuzhiyun 		ret = iio_device_claim_direct_mode(indio_dev);
100*4882a593Smuzhiyun 		if (ret < 0)
101*4882a593Smuzhiyun 			return ret;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 		ret = regulator_enable(adc->reg);
104*4882a593Smuzhiyun 		if (ret) {
105*4882a593Smuzhiyun 			iio_device_release_direct_mode(indio_dev);
106*4882a593Smuzhiyun 			return ret;
107*4882a593Smuzhiyun 		}
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 		adc->tx_buf[0] = channel->channel << 3;
110*4882a593Smuzhiyun 		ret = adc084s021_adc_conversion(adc, val);
111*4882a593Smuzhiyun 		iio_device_release_direct_mode(indio_dev);
112*4882a593Smuzhiyun 		regulator_disable(adc->reg);
113*4882a593Smuzhiyun 		if (ret < 0)
114*4882a593Smuzhiyun 			return ret;
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 		*val = be16_to_cpu(*val);
117*4882a593Smuzhiyun 		*val = (*val >> channel->scan_type.shift) & 0xff;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 		return IIO_VAL_INT;
120*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
121*4882a593Smuzhiyun 		ret = regulator_enable(adc->reg);
122*4882a593Smuzhiyun 		if (ret)
123*4882a593Smuzhiyun 			return ret;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 		ret = regulator_get_voltage(adc->reg);
126*4882a593Smuzhiyun 		regulator_disable(adc->reg);
127*4882a593Smuzhiyun 		if (ret < 0)
128*4882a593Smuzhiyun 			return ret;
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 		*val = ret / 1000;
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 		return IIO_VAL_INT;
133*4882a593Smuzhiyun 	default:
134*4882a593Smuzhiyun 		return -EINVAL;
135*4882a593Smuzhiyun 	}
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun /**
139*4882a593Smuzhiyun  * Read enabled ADC channels and push data to the buffer.
140*4882a593Smuzhiyun  *
141*4882a593Smuzhiyun  * @irq: The interrupt number (not used).
142*4882a593Smuzhiyun  * @pollfunc: Pointer to the poll func.
143*4882a593Smuzhiyun  */
adc084s021_buffer_trigger_handler(int irq,void * pollfunc)144*4882a593Smuzhiyun static irqreturn_t adc084s021_buffer_trigger_handler(int irq, void *pollfunc)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun 	struct iio_poll_func *pf = pollfunc;
147*4882a593Smuzhiyun 	struct iio_dev *indio_dev = pf->indio_dev;
148*4882a593Smuzhiyun 	struct adc084s021 *adc = iio_priv(indio_dev);
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	mutex_lock(&adc->lock);
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 	if (adc084s021_adc_conversion(adc, adc->scan.channels) < 0)
153*4882a593Smuzhiyun 		dev_err(&adc->spi->dev, "Failed to read data\n");
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	iio_push_to_buffers_with_timestamp(indio_dev, &adc->scan,
156*4882a593Smuzhiyun 					   iio_get_time_ns(indio_dev));
157*4882a593Smuzhiyun 	mutex_unlock(&adc->lock);
158*4882a593Smuzhiyun 	iio_trigger_notify_done(indio_dev->trig);
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	return IRQ_HANDLED;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun 
adc084s021_buffer_preenable(struct iio_dev * indio_dev)163*4882a593Smuzhiyun static int adc084s021_buffer_preenable(struct iio_dev *indio_dev)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun 	struct adc084s021 *adc = iio_priv(indio_dev);
166*4882a593Smuzhiyun 	int scan_index;
167*4882a593Smuzhiyun 	int i = 0;
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	for_each_set_bit(scan_index, indio_dev->active_scan_mask,
170*4882a593Smuzhiyun 			 indio_dev->masklength) {
171*4882a593Smuzhiyun 		const struct iio_chan_spec *channel =
172*4882a593Smuzhiyun 			&indio_dev->channels[scan_index];
173*4882a593Smuzhiyun 		adc->tx_buf[i++] = channel->channel << 3;
174*4882a593Smuzhiyun 	}
175*4882a593Smuzhiyun 	adc->spi_trans.len = 2 + (i * sizeof(__be16)); /* Trash + channels */
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	return regulator_enable(adc->reg);
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun 
adc084s021_buffer_postdisable(struct iio_dev * indio_dev)180*4882a593Smuzhiyun static int adc084s021_buffer_postdisable(struct iio_dev *indio_dev)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun 	struct adc084s021 *adc = iio_priv(indio_dev);
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	adc->spi_trans.len = 4; /* Trash + single channel */
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	return regulator_disable(adc->reg);
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun static const struct iio_info adc084s021_info = {
190*4882a593Smuzhiyun 	.read_raw = adc084s021_read_raw,
191*4882a593Smuzhiyun };
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun static const struct iio_buffer_setup_ops adc084s021_buffer_setup_ops = {
194*4882a593Smuzhiyun 	.preenable = adc084s021_buffer_preenable,
195*4882a593Smuzhiyun 	.postdisable = adc084s021_buffer_postdisable,
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun 
adc084s021_probe(struct spi_device * spi)198*4882a593Smuzhiyun static int adc084s021_probe(struct spi_device *spi)
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
201*4882a593Smuzhiyun 	struct adc084s021 *adc;
202*4882a593Smuzhiyun 	int ret;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
205*4882a593Smuzhiyun 	if (!indio_dev) {
206*4882a593Smuzhiyun 		dev_err(&spi->dev, "Failed to allocate IIO device\n");
207*4882a593Smuzhiyun 		return -ENOMEM;
208*4882a593Smuzhiyun 	}
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	adc = iio_priv(indio_dev);
211*4882a593Smuzhiyun 	adc->spi = spi;
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	/* Connect the SPI device and the iio dev */
214*4882a593Smuzhiyun 	spi_set_drvdata(spi, indio_dev);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	/* Initiate the Industrial I/O device */
217*4882a593Smuzhiyun 	indio_dev->name = spi_get_device_id(spi)->name;
218*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
219*4882a593Smuzhiyun 	indio_dev->info = &adc084s021_info;
220*4882a593Smuzhiyun 	indio_dev->channels = adc084s021_channels;
221*4882a593Smuzhiyun 	indio_dev->num_channels = ARRAY_SIZE(adc084s021_channels);
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	/* Create SPI transfer for channel reads */
224*4882a593Smuzhiyun 	adc->spi_trans.tx_buf = adc->tx_buf;
225*4882a593Smuzhiyun 	adc->spi_trans.rx_buf = adc->rx_buf;
226*4882a593Smuzhiyun 	adc->spi_trans.len = 4; /* Trash + single channel */
227*4882a593Smuzhiyun 	spi_message_init_with_transfers(&adc->message, &adc->spi_trans, 1);
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	adc->reg = devm_regulator_get(&spi->dev, "vref");
230*4882a593Smuzhiyun 	if (IS_ERR(adc->reg))
231*4882a593Smuzhiyun 		return PTR_ERR(adc->reg);
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	mutex_init(&adc->lock);
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	/* Setup triggered buffer with pollfunction */
236*4882a593Smuzhiyun 	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
237*4882a593Smuzhiyun 					    adc084s021_buffer_trigger_handler,
238*4882a593Smuzhiyun 					    &adc084s021_buffer_setup_ops);
239*4882a593Smuzhiyun 	if (ret) {
240*4882a593Smuzhiyun 		dev_err(&spi->dev, "Failed to setup triggered buffer\n");
241*4882a593Smuzhiyun 		return ret;
242*4882a593Smuzhiyun 	}
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	return devm_iio_device_register(&spi->dev, indio_dev);
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun static const struct of_device_id adc084s021_of_match[] = {
248*4882a593Smuzhiyun 	{ .compatible = "ti,adc084s021", },
249*4882a593Smuzhiyun 	{},
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, adc084s021_of_match);
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun static const struct spi_device_id adc084s021_id[] = {
254*4882a593Smuzhiyun 	{ ADC084S021_DRIVER_NAME, 0},
255*4882a593Smuzhiyun 	{}
256*4882a593Smuzhiyun };
257*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, adc084s021_id);
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun static struct spi_driver adc084s021_driver = {
260*4882a593Smuzhiyun 	.driver = {
261*4882a593Smuzhiyun 		.name = ADC084S021_DRIVER_NAME,
262*4882a593Smuzhiyun 		.of_match_table = adc084s021_of_match,
263*4882a593Smuzhiyun 	},
264*4882a593Smuzhiyun 	.probe = adc084s021_probe,
265*4882a593Smuzhiyun 	.id_table = adc084s021_id,
266*4882a593Smuzhiyun };
267*4882a593Smuzhiyun module_spi_driver(adc084s021_driver);
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun MODULE_AUTHOR("Mårten Lindahl <martenli@axis.com>");
270*4882a593Smuzhiyun MODULE_DESCRIPTION("Texas Instruments ADC084S021");
271*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
272*4882a593Smuzhiyun MODULE_VERSION("1.0");
273