1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ADC0831/ADC0832/ADC0834/ADC0838 8-bit ADC driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2016 Akinobu Mita <akinobu.mita@gmail.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Datasheet: https://www.ti.com/lit/ds/symlink/adc0832-n.pdf
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
12*4882a593Smuzhiyun #include <linux/spi/spi.h>
13*4882a593Smuzhiyun #include <linux/iio/iio.h>
14*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
15*4882a593Smuzhiyun #include <linux/iio/buffer.h>
16*4882a593Smuzhiyun #include <linux/iio/trigger.h>
17*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
18*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun enum {
21*4882a593Smuzhiyun adc0831,
22*4882a593Smuzhiyun adc0832,
23*4882a593Smuzhiyun adc0834,
24*4882a593Smuzhiyun adc0838,
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct adc0832 {
28*4882a593Smuzhiyun struct spi_device *spi;
29*4882a593Smuzhiyun struct regulator *reg;
30*4882a593Smuzhiyun struct mutex lock;
31*4882a593Smuzhiyun u8 mux_bits;
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun * Max size needed: 16x 1 byte ADC data + 8 bytes timestamp
34*4882a593Smuzhiyun * May be shorter if not all channels are enabled subject
35*4882a593Smuzhiyun * to the timestamp remaining 8 byte aligned.
36*4882a593Smuzhiyun */
37*4882a593Smuzhiyun u8 data[24] __aligned(8);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun u8 tx_buf[2] ____cacheline_aligned;
40*4882a593Smuzhiyun u8 rx_buf[2];
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define ADC0832_VOLTAGE_CHANNEL(chan) \
44*4882a593Smuzhiyun { \
45*4882a593Smuzhiyun .type = IIO_VOLTAGE, \
46*4882a593Smuzhiyun .indexed = 1, \
47*4882a593Smuzhiyun .channel = chan, \
48*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
49*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
50*4882a593Smuzhiyun .scan_index = chan, \
51*4882a593Smuzhiyun .scan_type = { \
52*4882a593Smuzhiyun .sign = 'u', \
53*4882a593Smuzhiyun .realbits = 8, \
54*4882a593Smuzhiyun .storagebits = 8, \
55*4882a593Smuzhiyun }, \
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define ADC0832_VOLTAGE_CHANNEL_DIFF(chan1, chan2, si) \
59*4882a593Smuzhiyun { \
60*4882a593Smuzhiyun .type = IIO_VOLTAGE, \
61*4882a593Smuzhiyun .indexed = 1, \
62*4882a593Smuzhiyun .channel = (chan1), \
63*4882a593Smuzhiyun .channel2 = (chan2), \
64*4882a593Smuzhiyun .differential = 1, \
65*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
66*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
67*4882a593Smuzhiyun .scan_index = si, \
68*4882a593Smuzhiyun .scan_type = { \
69*4882a593Smuzhiyun .sign = 'u', \
70*4882a593Smuzhiyun .realbits = 8, \
71*4882a593Smuzhiyun .storagebits = 8, \
72*4882a593Smuzhiyun }, \
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun static const struct iio_chan_spec adc0831_channels[] = {
76*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1, 0),
77*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(1),
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun static const struct iio_chan_spec adc0832_channels[] = {
81*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL(0),
82*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL(1),
83*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1, 2),
84*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL_DIFF(1, 0, 3),
85*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(4),
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun static const struct iio_chan_spec adc0834_channels[] = {
89*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL(0),
90*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL(1),
91*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL(2),
92*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL(3),
93*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1, 4),
94*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL_DIFF(1, 0, 5),
95*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL_DIFF(2, 3, 6),
96*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL_DIFF(3, 2, 7),
97*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(8),
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun static const struct iio_chan_spec adc0838_channels[] = {
101*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL(0),
102*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL(1),
103*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL(2),
104*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL(3),
105*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL(4),
106*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL(5),
107*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL(6),
108*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL(7),
109*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL_DIFF(0, 1, 8),
110*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL_DIFF(1, 0, 9),
111*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL_DIFF(2, 3, 10),
112*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL_DIFF(3, 2, 11),
113*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL_DIFF(4, 5, 12),
114*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL_DIFF(5, 4, 13),
115*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL_DIFF(6, 7, 14),
116*4882a593Smuzhiyun ADC0832_VOLTAGE_CHANNEL_DIFF(7, 6, 15),
117*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(16),
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
adc0831_adc_conversion(struct adc0832 * adc)120*4882a593Smuzhiyun static int adc0831_adc_conversion(struct adc0832 *adc)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun struct spi_device *spi = adc->spi;
123*4882a593Smuzhiyun int ret;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun ret = spi_read(spi, &adc->rx_buf, 2);
126*4882a593Smuzhiyun if (ret)
127*4882a593Smuzhiyun return ret;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /*
130*4882a593Smuzhiyun * Skip TRI-STATE and a leading zero
131*4882a593Smuzhiyun */
132*4882a593Smuzhiyun return (adc->rx_buf[0] << 2 & 0xff) | (adc->rx_buf[1] >> 6);
133*4882a593Smuzhiyun }
134*4882a593Smuzhiyun
adc0832_adc_conversion(struct adc0832 * adc,int channel,bool differential)135*4882a593Smuzhiyun static int adc0832_adc_conversion(struct adc0832 *adc, int channel,
136*4882a593Smuzhiyun bool differential)
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun struct spi_device *spi = adc->spi;
139*4882a593Smuzhiyun struct spi_transfer xfer = {
140*4882a593Smuzhiyun .tx_buf = adc->tx_buf,
141*4882a593Smuzhiyun .rx_buf = adc->rx_buf,
142*4882a593Smuzhiyun .len = 2,
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun int ret;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun if (!adc->mux_bits)
147*4882a593Smuzhiyun return adc0831_adc_conversion(adc);
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun /* start bit */
150*4882a593Smuzhiyun adc->tx_buf[0] = 1 << (adc->mux_bits + 1);
151*4882a593Smuzhiyun /* single-ended or differential */
152*4882a593Smuzhiyun adc->tx_buf[0] |= differential ? 0 : (1 << adc->mux_bits);
153*4882a593Smuzhiyun /* odd / sign */
154*4882a593Smuzhiyun adc->tx_buf[0] |= (channel % 2) << (adc->mux_bits - 1);
155*4882a593Smuzhiyun /* select */
156*4882a593Smuzhiyun if (adc->mux_bits > 1)
157*4882a593Smuzhiyun adc->tx_buf[0] |= channel / 2;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun /* align Data output BIT7 (MSB) to 8-bit boundary */
160*4882a593Smuzhiyun adc->tx_buf[0] <<= 1;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun ret = spi_sync_transfer(spi, &xfer, 1);
163*4882a593Smuzhiyun if (ret)
164*4882a593Smuzhiyun return ret;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun return adc->rx_buf[1];
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
adc0832_read_raw(struct iio_dev * iio,struct iio_chan_spec const * channel,int * value,int * shift,long mask)169*4882a593Smuzhiyun static int adc0832_read_raw(struct iio_dev *iio,
170*4882a593Smuzhiyun struct iio_chan_spec const *channel, int *value,
171*4882a593Smuzhiyun int *shift, long mask)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun struct adc0832 *adc = iio_priv(iio);
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun switch (mask) {
176*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
177*4882a593Smuzhiyun mutex_lock(&adc->lock);
178*4882a593Smuzhiyun *value = adc0832_adc_conversion(adc, channel->channel,
179*4882a593Smuzhiyun channel->differential);
180*4882a593Smuzhiyun mutex_unlock(&adc->lock);
181*4882a593Smuzhiyun if (*value < 0)
182*4882a593Smuzhiyun return *value;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun return IIO_VAL_INT;
185*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
186*4882a593Smuzhiyun *value = regulator_get_voltage(adc->reg);
187*4882a593Smuzhiyun if (*value < 0)
188*4882a593Smuzhiyun return *value;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun /* convert regulator output voltage to mV */
191*4882a593Smuzhiyun *value /= 1000;
192*4882a593Smuzhiyun *shift = 8;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL_LOG2;
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun return -EINVAL;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun static const struct iio_info adc0832_info = {
201*4882a593Smuzhiyun .read_raw = adc0832_read_raw,
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun
adc0832_trigger_handler(int irq,void * p)204*4882a593Smuzhiyun static irqreturn_t adc0832_trigger_handler(int irq, void *p)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun struct iio_poll_func *pf = p;
207*4882a593Smuzhiyun struct iio_dev *indio_dev = pf->indio_dev;
208*4882a593Smuzhiyun struct adc0832 *adc = iio_priv(indio_dev);
209*4882a593Smuzhiyun int scan_index;
210*4882a593Smuzhiyun int i = 0;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun mutex_lock(&adc->lock);
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun for_each_set_bit(scan_index, indio_dev->active_scan_mask,
215*4882a593Smuzhiyun indio_dev->masklength) {
216*4882a593Smuzhiyun const struct iio_chan_spec *scan_chan =
217*4882a593Smuzhiyun &indio_dev->channels[scan_index];
218*4882a593Smuzhiyun int ret = adc0832_adc_conversion(adc, scan_chan->channel,
219*4882a593Smuzhiyun scan_chan->differential);
220*4882a593Smuzhiyun if (ret < 0) {
221*4882a593Smuzhiyun dev_warn(&adc->spi->dev,
222*4882a593Smuzhiyun "failed to get conversion data\n");
223*4882a593Smuzhiyun goto out;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun adc->data[i] = ret;
227*4882a593Smuzhiyun i++;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun iio_push_to_buffers_with_timestamp(indio_dev, adc->data,
230*4882a593Smuzhiyun iio_get_time_ns(indio_dev));
231*4882a593Smuzhiyun out:
232*4882a593Smuzhiyun mutex_unlock(&adc->lock);
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun iio_trigger_notify_done(indio_dev->trig);
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun return IRQ_HANDLED;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
adc0832_probe(struct spi_device * spi)239*4882a593Smuzhiyun static int adc0832_probe(struct spi_device *spi)
240*4882a593Smuzhiyun {
241*4882a593Smuzhiyun struct iio_dev *indio_dev;
242*4882a593Smuzhiyun struct adc0832 *adc;
243*4882a593Smuzhiyun int ret;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*adc));
246*4882a593Smuzhiyun if (!indio_dev)
247*4882a593Smuzhiyun return -ENOMEM;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun adc = iio_priv(indio_dev);
250*4882a593Smuzhiyun adc->spi = spi;
251*4882a593Smuzhiyun mutex_init(&adc->lock);
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun indio_dev->name = spi_get_device_id(spi)->name;
254*4882a593Smuzhiyun indio_dev->info = &adc0832_info;
255*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun switch (spi_get_device_id(spi)->driver_data) {
258*4882a593Smuzhiyun case adc0831:
259*4882a593Smuzhiyun adc->mux_bits = 0;
260*4882a593Smuzhiyun indio_dev->channels = adc0831_channels;
261*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(adc0831_channels);
262*4882a593Smuzhiyun break;
263*4882a593Smuzhiyun case adc0832:
264*4882a593Smuzhiyun adc->mux_bits = 1;
265*4882a593Smuzhiyun indio_dev->channels = adc0832_channels;
266*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(adc0832_channels);
267*4882a593Smuzhiyun break;
268*4882a593Smuzhiyun case adc0834:
269*4882a593Smuzhiyun adc->mux_bits = 2;
270*4882a593Smuzhiyun indio_dev->channels = adc0834_channels;
271*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(adc0834_channels);
272*4882a593Smuzhiyun break;
273*4882a593Smuzhiyun case adc0838:
274*4882a593Smuzhiyun adc->mux_bits = 3;
275*4882a593Smuzhiyun indio_dev->channels = adc0838_channels;
276*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(adc0838_channels);
277*4882a593Smuzhiyun break;
278*4882a593Smuzhiyun default:
279*4882a593Smuzhiyun return -EINVAL;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun adc->reg = devm_regulator_get(&spi->dev, "vref");
283*4882a593Smuzhiyun if (IS_ERR(adc->reg))
284*4882a593Smuzhiyun return PTR_ERR(adc->reg);
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun ret = regulator_enable(adc->reg);
287*4882a593Smuzhiyun if (ret)
288*4882a593Smuzhiyun return ret;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun spi_set_drvdata(spi, indio_dev);
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun ret = iio_triggered_buffer_setup(indio_dev, NULL,
293*4882a593Smuzhiyun adc0832_trigger_handler, NULL);
294*4882a593Smuzhiyun if (ret)
295*4882a593Smuzhiyun goto err_reg_disable;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
298*4882a593Smuzhiyun if (ret)
299*4882a593Smuzhiyun goto err_buffer_cleanup;
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun return 0;
302*4882a593Smuzhiyun err_buffer_cleanup:
303*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
304*4882a593Smuzhiyun err_reg_disable:
305*4882a593Smuzhiyun regulator_disable(adc->reg);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun return ret;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
adc0832_remove(struct spi_device * spi)310*4882a593Smuzhiyun static int adc0832_remove(struct spi_device *spi)
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun struct iio_dev *indio_dev = spi_get_drvdata(spi);
313*4882a593Smuzhiyun struct adc0832 *adc = iio_priv(indio_dev);
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun iio_device_unregister(indio_dev);
316*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
317*4882a593Smuzhiyun regulator_disable(adc->reg);
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun return 0;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun static const struct of_device_id adc0832_dt_ids[] = {
323*4882a593Smuzhiyun { .compatible = "ti,adc0831", },
324*4882a593Smuzhiyun { .compatible = "ti,adc0832", },
325*4882a593Smuzhiyun { .compatible = "ti,adc0834", },
326*4882a593Smuzhiyun { .compatible = "ti,adc0838", },
327*4882a593Smuzhiyun {}
328*4882a593Smuzhiyun };
329*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, adc0832_dt_ids);
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun static const struct spi_device_id adc0832_id[] = {
332*4882a593Smuzhiyun { "adc0831", adc0831 },
333*4882a593Smuzhiyun { "adc0832", adc0832 },
334*4882a593Smuzhiyun { "adc0834", adc0834 },
335*4882a593Smuzhiyun { "adc0838", adc0838 },
336*4882a593Smuzhiyun {}
337*4882a593Smuzhiyun };
338*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, adc0832_id);
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun static struct spi_driver adc0832_driver = {
341*4882a593Smuzhiyun .driver = {
342*4882a593Smuzhiyun .name = "adc0832",
343*4882a593Smuzhiyun .of_match_table = adc0832_dt_ids,
344*4882a593Smuzhiyun },
345*4882a593Smuzhiyun .probe = adc0832_probe,
346*4882a593Smuzhiyun .remove = adc0832_remove,
347*4882a593Smuzhiyun .id_table = adc0832_id,
348*4882a593Smuzhiyun };
349*4882a593Smuzhiyun module_spi_driver(adc0832_driver);
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun MODULE_AUTHOR("Akinobu Mita <akinobu.mita@gmail.com>");
352*4882a593Smuzhiyun MODULE_DESCRIPTION("ADC0831/ADC0832/ADC0834/ADC0838 driver");
353*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
354