xref: /OK3568_Linux_fs/kernel/drivers/iio/adc/ti-adc081c.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * TI ADC081C/ADC101C/ADC121C 8/10/12-bit ADC driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2012 Avionic Design GmbH
6*4882a593Smuzhiyun  * Copyright (C) 2016 Intel
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Datasheets:
9*4882a593Smuzhiyun  *	https://www.ti.com/lit/ds/symlink/adc081c021.pdf
10*4882a593Smuzhiyun  *	https://www.ti.com/lit/ds/symlink/adc101c021.pdf
11*4882a593Smuzhiyun  *	https://www.ti.com/lit/ds/symlink/adc121c021.pdf
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * The devices have a very similar interface and differ mostly in the number of
14*4882a593Smuzhiyun  * bits handled. For the 8-bit and 10-bit models the least-significant 4 or 2
15*4882a593Smuzhiyun  * bits of value registers are reserved.
16*4882a593Smuzhiyun  */
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <linux/err.h>
19*4882a593Smuzhiyun #include <linux/i2c.h>
20*4882a593Smuzhiyun #include <linux/module.h>
21*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
22*4882a593Smuzhiyun #include <linux/property.h>
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #include <linux/iio/iio.h>
25*4882a593Smuzhiyun #include <linux/iio/buffer.h>
26*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
27*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
28*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun struct adc081c {
31*4882a593Smuzhiyun 	struct i2c_client *i2c;
32*4882a593Smuzhiyun 	struct regulator *ref;
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun 	/* 8, 10 or 12 */
35*4882a593Smuzhiyun 	int bits;
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	/* Ensure natural alignment of buffer elements */
38*4882a593Smuzhiyun 	struct {
39*4882a593Smuzhiyun 		u16 channel;
40*4882a593Smuzhiyun 		s64 ts __aligned(8);
41*4882a593Smuzhiyun 	} scan;
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #define REG_CONV_RES 0x00
45*4882a593Smuzhiyun 
adc081c_read_raw(struct iio_dev * iio,struct iio_chan_spec const * channel,int * value,int * shift,long mask)46*4882a593Smuzhiyun static int adc081c_read_raw(struct iio_dev *iio,
47*4882a593Smuzhiyun 			    struct iio_chan_spec const *channel, int *value,
48*4882a593Smuzhiyun 			    int *shift, long mask)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun 	struct adc081c *adc = iio_priv(iio);
51*4882a593Smuzhiyun 	int err;
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	switch (mask) {
54*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
55*4882a593Smuzhiyun 		err = i2c_smbus_read_word_swapped(adc->i2c, REG_CONV_RES);
56*4882a593Smuzhiyun 		if (err < 0)
57*4882a593Smuzhiyun 			return err;
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 		*value = (err & 0xFFF) >> (12 - adc->bits);
60*4882a593Smuzhiyun 		return IIO_VAL_INT;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
63*4882a593Smuzhiyun 		err = regulator_get_voltage(adc->ref);
64*4882a593Smuzhiyun 		if (err < 0)
65*4882a593Smuzhiyun 			return err;
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 		*value = err / 1000;
68*4882a593Smuzhiyun 		*shift = adc->bits;
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun 		return IIO_VAL_FRACTIONAL_LOG2;
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun 	default:
73*4882a593Smuzhiyun 		break;
74*4882a593Smuzhiyun 	}
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 	return -EINVAL;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun #define ADCxx1C_CHAN(_bits) {					\
80*4882a593Smuzhiyun 	.type = IIO_VOLTAGE,					\
81*4882a593Smuzhiyun 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
82*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
83*4882a593Smuzhiyun 	.scan_type = {						\
84*4882a593Smuzhiyun 		.sign = 'u',					\
85*4882a593Smuzhiyun 		.realbits = (_bits),				\
86*4882a593Smuzhiyun 		.storagebits = 16,				\
87*4882a593Smuzhiyun 		.shift = 12 - (_bits),				\
88*4882a593Smuzhiyun 		.endianness = IIO_CPU,				\
89*4882a593Smuzhiyun 	},							\
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun #define DEFINE_ADCxx1C_CHANNELS(_name, _bits)				\
93*4882a593Smuzhiyun 	static const struct iio_chan_spec _name ## _channels[] = {	\
94*4882a593Smuzhiyun 		ADCxx1C_CHAN((_bits)),					\
95*4882a593Smuzhiyun 		IIO_CHAN_SOFT_TIMESTAMP(1),				\
96*4882a593Smuzhiyun 	};								\
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun #define ADC081C_NUM_CHANNELS 2
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun struct adcxx1c_model {
101*4882a593Smuzhiyun 	const struct iio_chan_spec* channels;
102*4882a593Smuzhiyun 	int bits;
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun #define ADCxx1C_MODEL(_name, _bits)					\
106*4882a593Smuzhiyun 	{								\
107*4882a593Smuzhiyun 		.channels = _name ## _channels,				\
108*4882a593Smuzhiyun 		.bits = (_bits),					\
109*4882a593Smuzhiyun 	}
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun DEFINE_ADCxx1C_CHANNELS(adc081c,  8);
112*4882a593Smuzhiyun DEFINE_ADCxx1C_CHANNELS(adc101c, 10);
113*4882a593Smuzhiyun DEFINE_ADCxx1C_CHANNELS(adc121c, 12);
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun /* Model ids are indexes in _models array */
116*4882a593Smuzhiyun enum adcxx1c_model_id {
117*4882a593Smuzhiyun 	ADC081C = 0,
118*4882a593Smuzhiyun 	ADC101C = 1,
119*4882a593Smuzhiyun 	ADC121C = 2,
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun static struct adcxx1c_model adcxx1c_models[] = {
123*4882a593Smuzhiyun 	ADCxx1C_MODEL(adc081c,  8),
124*4882a593Smuzhiyun 	ADCxx1C_MODEL(adc101c, 10),
125*4882a593Smuzhiyun 	ADCxx1C_MODEL(adc121c, 12),
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun static const struct iio_info adc081c_info = {
129*4882a593Smuzhiyun 	.read_raw = adc081c_read_raw,
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun 
adc081c_trigger_handler(int irq,void * p)132*4882a593Smuzhiyun static irqreturn_t adc081c_trigger_handler(int irq, void *p)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun 	struct iio_poll_func *pf = p;
135*4882a593Smuzhiyun 	struct iio_dev *indio_dev = pf->indio_dev;
136*4882a593Smuzhiyun 	struct adc081c *data = iio_priv(indio_dev);
137*4882a593Smuzhiyun 	int ret;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	ret = i2c_smbus_read_word_swapped(data->i2c, REG_CONV_RES);
140*4882a593Smuzhiyun 	if (ret < 0)
141*4882a593Smuzhiyun 		goto out;
142*4882a593Smuzhiyun 	data->scan.channel = ret;
143*4882a593Smuzhiyun 	iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
144*4882a593Smuzhiyun 					   iio_get_time_ns(indio_dev));
145*4882a593Smuzhiyun out:
146*4882a593Smuzhiyun 	iio_trigger_notify_done(indio_dev->trig);
147*4882a593Smuzhiyun 	return IRQ_HANDLED;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
adc081c_probe(struct i2c_client * client,const struct i2c_device_id * id)150*4882a593Smuzhiyun static int adc081c_probe(struct i2c_client *client,
151*4882a593Smuzhiyun 			 const struct i2c_device_id *id)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	struct iio_dev *iio;
154*4882a593Smuzhiyun 	struct adc081c *adc;
155*4882a593Smuzhiyun 	const struct adcxx1c_model *model;
156*4882a593Smuzhiyun 	int err;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_WORD_DATA))
159*4882a593Smuzhiyun 		return -EOPNOTSUPP;
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	if (dev_fwnode(&client->dev))
162*4882a593Smuzhiyun 		model = device_get_match_data(&client->dev);
163*4882a593Smuzhiyun 	else
164*4882a593Smuzhiyun 		model = &adcxx1c_models[id->driver_data];
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	iio = devm_iio_device_alloc(&client->dev, sizeof(*adc));
167*4882a593Smuzhiyun 	if (!iio)
168*4882a593Smuzhiyun 		return -ENOMEM;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	adc = iio_priv(iio);
171*4882a593Smuzhiyun 	adc->i2c = client;
172*4882a593Smuzhiyun 	adc->bits = model->bits;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	adc->ref = devm_regulator_get(&client->dev, "vref");
175*4882a593Smuzhiyun 	if (IS_ERR(adc->ref))
176*4882a593Smuzhiyun 		return PTR_ERR(adc->ref);
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	err = regulator_enable(adc->ref);
179*4882a593Smuzhiyun 	if (err < 0)
180*4882a593Smuzhiyun 		return err;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	iio->name = dev_name(&client->dev);
183*4882a593Smuzhiyun 	iio->modes = INDIO_DIRECT_MODE;
184*4882a593Smuzhiyun 	iio->info = &adc081c_info;
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun 	iio->channels = model->channels;
187*4882a593Smuzhiyun 	iio->num_channels = ADC081C_NUM_CHANNELS;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	err = iio_triggered_buffer_setup(iio, NULL, adc081c_trigger_handler, NULL);
190*4882a593Smuzhiyun 	if (err < 0) {
191*4882a593Smuzhiyun 		dev_err(&client->dev, "iio triggered buffer setup failed\n");
192*4882a593Smuzhiyun 		goto err_regulator_disable;
193*4882a593Smuzhiyun 	}
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	err = iio_device_register(iio);
196*4882a593Smuzhiyun 	if (err < 0)
197*4882a593Smuzhiyun 		goto err_buffer_cleanup;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	i2c_set_clientdata(client, iio);
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	return 0;
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun err_buffer_cleanup:
204*4882a593Smuzhiyun 	iio_triggered_buffer_cleanup(iio);
205*4882a593Smuzhiyun err_regulator_disable:
206*4882a593Smuzhiyun 	regulator_disable(adc->ref);
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	return err;
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun 
adc081c_remove(struct i2c_client * client)211*4882a593Smuzhiyun static int adc081c_remove(struct i2c_client *client)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun 	struct iio_dev *iio = i2c_get_clientdata(client);
214*4882a593Smuzhiyun 	struct adc081c *adc = iio_priv(iio);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	iio_device_unregister(iio);
217*4882a593Smuzhiyun 	iio_triggered_buffer_cleanup(iio);
218*4882a593Smuzhiyun 	regulator_disable(adc->ref);
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	return 0;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun static const struct i2c_device_id adc081c_id[] = {
224*4882a593Smuzhiyun 	{ "adc081c", ADC081C },
225*4882a593Smuzhiyun 	{ "adc101c", ADC101C },
226*4882a593Smuzhiyun 	{ "adc121c", ADC121C },
227*4882a593Smuzhiyun 	{ }
228*4882a593Smuzhiyun };
229*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, adc081c_id);
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun static const struct acpi_device_id adc081c_acpi_match[] = {
232*4882a593Smuzhiyun 	/* Used on some AAEON boards */
233*4882a593Smuzhiyun 	{ "ADC081C", (kernel_ulong_t)&adcxx1c_models[ADC081C] },
234*4882a593Smuzhiyun 	{ }
235*4882a593Smuzhiyun };
236*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, adc081c_acpi_match);
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun static const struct of_device_id adc081c_of_match[] = {
239*4882a593Smuzhiyun 	{ .compatible = "ti,adc081c", .data = &adcxx1c_models[ADC081C] },
240*4882a593Smuzhiyun 	{ .compatible = "ti,adc101c", .data = &adcxx1c_models[ADC101C] },
241*4882a593Smuzhiyun 	{ .compatible = "ti,adc121c", .data = &adcxx1c_models[ADC121C] },
242*4882a593Smuzhiyun 	{ }
243*4882a593Smuzhiyun };
244*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, adc081c_of_match);
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun static struct i2c_driver adc081c_driver = {
247*4882a593Smuzhiyun 	.driver = {
248*4882a593Smuzhiyun 		.name = "adc081c",
249*4882a593Smuzhiyun 		.of_match_table = adc081c_of_match,
250*4882a593Smuzhiyun 		.acpi_match_table = adc081c_acpi_match,
251*4882a593Smuzhiyun 	},
252*4882a593Smuzhiyun 	.probe = adc081c_probe,
253*4882a593Smuzhiyun 	.remove = adc081c_remove,
254*4882a593Smuzhiyun 	.id_table = adc081c_id,
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun module_i2c_driver(adc081c_driver);
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
259*4882a593Smuzhiyun MODULE_DESCRIPTION("Texas Instruments ADC081C/ADC101C/ADC121C driver");
260*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
261