1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* ADC driver for sunxi platforms' (A10, A13 and A31) GPADC
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (c) 2016 Quentin Schulz <quentin.schulz@free-electrons.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * The Allwinner SoCs all have an ADC that can also act as a touchscreen
7*4882a593Smuzhiyun * controller and a thermal sensor.
8*4882a593Smuzhiyun * The thermal sensor works only when the ADC acts as a touchscreen controller
9*4882a593Smuzhiyun * and is configured to throw an interrupt every fixed periods of time (let say
10*4882a593Smuzhiyun * every X seconds).
11*4882a593Smuzhiyun * One would be tempted to disable the IP on the hardware side rather than
12*4882a593Smuzhiyun * disabling interrupts to save some power but that resets the internal clock of
13*4882a593Smuzhiyun * the IP, resulting in having to wait X seconds every time we want to read the
14*4882a593Smuzhiyun * value of the thermal sensor.
15*4882a593Smuzhiyun * This is also the reason of using autosuspend in pm_runtime. If there was no
16*4882a593Smuzhiyun * autosuspend, the thermal sensor would need X seconds after every
17*4882a593Smuzhiyun * pm_runtime_get_sync to get a value from the ADC. The autosuspend allows the
18*4882a593Smuzhiyun * thermal sensor to be requested again in a certain time span before it gets
19*4882a593Smuzhiyun * shutdown for not being used.
20*4882a593Smuzhiyun */
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #include <linux/completion.h>
23*4882a593Smuzhiyun #include <linux/interrupt.h>
24*4882a593Smuzhiyun #include <linux/io.h>
25*4882a593Smuzhiyun #include <linux/module.h>
26*4882a593Smuzhiyun #include <linux/of.h>
27*4882a593Smuzhiyun #include <linux/of_device.h>
28*4882a593Smuzhiyun #include <linux/platform_device.h>
29*4882a593Smuzhiyun #include <linux/pm_runtime.h>
30*4882a593Smuzhiyun #include <linux/regmap.h>
31*4882a593Smuzhiyun #include <linux/thermal.h>
32*4882a593Smuzhiyun #include <linux/delay.h>
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #include <linux/iio/iio.h>
35*4882a593Smuzhiyun #include <linux/iio/driver.h>
36*4882a593Smuzhiyun #include <linux/iio/machine.h>
37*4882a593Smuzhiyun #include <linux/mfd/sun4i-gpadc.h>
38*4882a593Smuzhiyun
sun4i_gpadc_chan_select(unsigned int chan)39*4882a593Smuzhiyun static unsigned int sun4i_gpadc_chan_select(unsigned int chan)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun return SUN4I_GPADC_CTRL1_ADC_CHAN_SELECT(chan);
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
sun6i_gpadc_chan_select(unsigned int chan)44*4882a593Smuzhiyun static unsigned int sun6i_gpadc_chan_select(unsigned int chan)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun return SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(chan);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun struct gpadc_data {
50*4882a593Smuzhiyun int temp_offset;
51*4882a593Smuzhiyun int temp_scale;
52*4882a593Smuzhiyun unsigned int tp_mode_en;
53*4882a593Smuzhiyun unsigned int tp_adc_select;
54*4882a593Smuzhiyun unsigned int (*adc_chan_select)(unsigned int chan);
55*4882a593Smuzhiyun unsigned int adc_chan_mask;
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun static const struct gpadc_data sun4i_gpadc_data = {
59*4882a593Smuzhiyun .temp_offset = -1932,
60*4882a593Smuzhiyun .temp_scale = 133,
61*4882a593Smuzhiyun .tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN,
62*4882a593Smuzhiyun .tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
63*4882a593Smuzhiyun .adc_chan_select = &sun4i_gpadc_chan_select,
64*4882a593Smuzhiyun .adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static const struct gpadc_data sun5i_gpadc_data = {
68*4882a593Smuzhiyun .temp_offset = -1447,
69*4882a593Smuzhiyun .temp_scale = 100,
70*4882a593Smuzhiyun .tp_mode_en = SUN4I_GPADC_CTRL1_TP_MODE_EN,
71*4882a593Smuzhiyun .tp_adc_select = SUN4I_GPADC_CTRL1_TP_ADC_SELECT,
72*4882a593Smuzhiyun .adc_chan_select = &sun4i_gpadc_chan_select,
73*4882a593Smuzhiyun .adc_chan_mask = SUN4I_GPADC_CTRL1_ADC_CHAN_MASK,
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun static const struct gpadc_data sun6i_gpadc_data = {
77*4882a593Smuzhiyun .temp_offset = -1623,
78*4882a593Smuzhiyun .temp_scale = 167,
79*4882a593Smuzhiyun .tp_mode_en = SUN6I_GPADC_CTRL1_TP_MODE_EN,
80*4882a593Smuzhiyun .tp_adc_select = SUN6I_GPADC_CTRL1_TP_ADC_SELECT,
81*4882a593Smuzhiyun .adc_chan_select = &sun6i_gpadc_chan_select,
82*4882a593Smuzhiyun .adc_chan_mask = SUN6I_GPADC_CTRL1_ADC_CHAN_MASK,
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun static const struct gpadc_data sun8i_a33_gpadc_data = {
86*4882a593Smuzhiyun .temp_offset = -1662,
87*4882a593Smuzhiyun .temp_scale = 162,
88*4882a593Smuzhiyun .tp_mode_en = SUN8I_GPADC_CTRL1_CHOP_TEMP_EN,
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun struct sun4i_gpadc_iio {
92*4882a593Smuzhiyun struct iio_dev *indio_dev;
93*4882a593Smuzhiyun struct completion completion;
94*4882a593Smuzhiyun int temp_data;
95*4882a593Smuzhiyun u32 adc_data;
96*4882a593Smuzhiyun struct regmap *regmap;
97*4882a593Smuzhiyun unsigned int fifo_data_irq;
98*4882a593Smuzhiyun atomic_t ignore_fifo_data_irq;
99*4882a593Smuzhiyun unsigned int temp_data_irq;
100*4882a593Smuzhiyun atomic_t ignore_temp_data_irq;
101*4882a593Smuzhiyun const struct gpadc_data *data;
102*4882a593Smuzhiyun bool no_irq;
103*4882a593Smuzhiyun /* prevents concurrent reads of temperature and ADC */
104*4882a593Smuzhiyun struct mutex mutex;
105*4882a593Smuzhiyun struct thermal_zone_device *tzd;
106*4882a593Smuzhiyun struct device *sensor_device;
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun #define SUN4I_GPADC_ADC_CHANNEL(_channel, _name) { \
110*4882a593Smuzhiyun .type = IIO_VOLTAGE, \
111*4882a593Smuzhiyun .indexed = 1, \
112*4882a593Smuzhiyun .channel = _channel, \
113*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
114*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
115*4882a593Smuzhiyun .datasheet_name = _name, \
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun static struct iio_map sun4i_gpadc_hwmon_maps[] = {
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun .adc_channel_label = "temp_adc",
121*4882a593Smuzhiyun .consumer_dev_name = "iio_hwmon.0",
122*4882a593Smuzhiyun },
123*4882a593Smuzhiyun { /* sentinel */ },
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun static const struct iio_chan_spec sun4i_gpadc_channels[] = {
127*4882a593Smuzhiyun SUN4I_GPADC_ADC_CHANNEL(0, "adc_chan0"),
128*4882a593Smuzhiyun SUN4I_GPADC_ADC_CHANNEL(1, "adc_chan1"),
129*4882a593Smuzhiyun SUN4I_GPADC_ADC_CHANNEL(2, "adc_chan2"),
130*4882a593Smuzhiyun SUN4I_GPADC_ADC_CHANNEL(3, "adc_chan3"),
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun .type = IIO_TEMP,
133*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
134*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE) |
135*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_OFFSET),
136*4882a593Smuzhiyun .datasheet_name = "temp_adc",
137*4882a593Smuzhiyun },
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun static const struct iio_chan_spec sun4i_gpadc_channels_no_temp[] = {
141*4882a593Smuzhiyun SUN4I_GPADC_ADC_CHANNEL(0, "adc_chan0"),
142*4882a593Smuzhiyun SUN4I_GPADC_ADC_CHANNEL(1, "adc_chan1"),
143*4882a593Smuzhiyun SUN4I_GPADC_ADC_CHANNEL(2, "adc_chan2"),
144*4882a593Smuzhiyun SUN4I_GPADC_ADC_CHANNEL(3, "adc_chan3"),
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun static const struct iio_chan_spec sun8i_a33_gpadc_channels[] = {
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun .type = IIO_TEMP,
150*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
151*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE) |
152*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_OFFSET),
153*4882a593Smuzhiyun .datasheet_name = "temp_adc",
154*4882a593Smuzhiyun },
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun static const struct regmap_config sun4i_gpadc_regmap_config = {
158*4882a593Smuzhiyun .reg_bits = 32,
159*4882a593Smuzhiyun .val_bits = 32,
160*4882a593Smuzhiyun .reg_stride = 4,
161*4882a593Smuzhiyun .fast_io = true,
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun
sun4i_prepare_for_irq(struct iio_dev * indio_dev,int channel,unsigned int irq)164*4882a593Smuzhiyun static int sun4i_prepare_for_irq(struct iio_dev *indio_dev, int channel,
165*4882a593Smuzhiyun unsigned int irq)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
168*4882a593Smuzhiyun int ret;
169*4882a593Smuzhiyun u32 reg;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun pm_runtime_get_sync(indio_dev->dev.parent);
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun reinit_completion(&info->completion);
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun ret = regmap_write(info->regmap, SUN4I_GPADC_INT_FIFOC,
176*4882a593Smuzhiyun SUN4I_GPADC_INT_FIFOC_TP_FIFO_TRIG_LEVEL(1) |
177*4882a593Smuzhiyun SUN4I_GPADC_INT_FIFOC_TP_FIFO_FLUSH);
178*4882a593Smuzhiyun if (ret)
179*4882a593Smuzhiyun return ret;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun ret = regmap_read(info->regmap, SUN4I_GPADC_CTRL1, ®);
182*4882a593Smuzhiyun if (ret)
183*4882a593Smuzhiyun return ret;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun if (irq == info->fifo_data_irq) {
186*4882a593Smuzhiyun ret = regmap_write(info->regmap, SUN4I_GPADC_CTRL1,
187*4882a593Smuzhiyun info->data->tp_mode_en |
188*4882a593Smuzhiyun info->data->tp_adc_select |
189*4882a593Smuzhiyun info->data->adc_chan_select(channel));
190*4882a593Smuzhiyun /*
191*4882a593Smuzhiyun * When the IP changes channel, it needs a bit of time to get
192*4882a593Smuzhiyun * correct values.
193*4882a593Smuzhiyun */
194*4882a593Smuzhiyun if ((reg & info->data->adc_chan_mask) !=
195*4882a593Smuzhiyun info->data->adc_chan_select(channel))
196*4882a593Smuzhiyun mdelay(10);
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun } else {
199*4882a593Smuzhiyun /*
200*4882a593Smuzhiyun * The temperature sensor returns valid data only when the ADC
201*4882a593Smuzhiyun * operates in touchscreen mode.
202*4882a593Smuzhiyun */
203*4882a593Smuzhiyun ret = regmap_write(info->regmap, SUN4I_GPADC_CTRL1,
204*4882a593Smuzhiyun info->data->tp_mode_en);
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun if (ret)
208*4882a593Smuzhiyun return ret;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun /*
211*4882a593Smuzhiyun * When the IP changes mode between ADC or touchscreen, it
212*4882a593Smuzhiyun * needs a bit of time to get correct values.
213*4882a593Smuzhiyun */
214*4882a593Smuzhiyun if ((reg & info->data->tp_adc_select) != info->data->tp_adc_select)
215*4882a593Smuzhiyun mdelay(100);
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun return 0;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
sun4i_gpadc_read(struct iio_dev * indio_dev,int channel,int * val,unsigned int irq)220*4882a593Smuzhiyun static int sun4i_gpadc_read(struct iio_dev *indio_dev, int channel, int *val,
221*4882a593Smuzhiyun unsigned int irq)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
224*4882a593Smuzhiyun int ret;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun mutex_lock(&info->mutex);
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun ret = sun4i_prepare_for_irq(indio_dev, channel, irq);
229*4882a593Smuzhiyun if (ret)
230*4882a593Smuzhiyun goto err;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun enable_irq(irq);
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /*
235*4882a593Smuzhiyun * The temperature sensor throws an interruption periodically (currently
236*4882a593Smuzhiyun * set at periods of ~0.6s in sun4i_gpadc_runtime_resume). A 1s delay
237*4882a593Smuzhiyun * makes sure an interruption occurs in normal conditions. If it doesn't
238*4882a593Smuzhiyun * occur, then there is a timeout.
239*4882a593Smuzhiyun */
240*4882a593Smuzhiyun if (!wait_for_completion_timeout(&info->completion,
241*4882a593Smuzhiyun msecs_to_jiffies(1000))) {
242*4882a593Smuzhiyun ret = -ETIMEDOUT;
243*4882a593Smuzhiyun goto err;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun if (irq == info->fifo_data_irq)
247*4882a593Smuzhiyun *val = info->adc_data;
248*4882a593Smuzhiyun else
249*4882a593Smuzhiyun *val = info->temp_data;
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun ret = 0;
252*4882a593Smuzhiyun pm_runtime_mark_last_busy(indio_dev->dev.parent);
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun err:
255*4882a593Smuzhiyun pm_runtime_put_autosuspend(indio_dev->dev.parent);
256*4882a593Smuzhiyun disable_irq(irq);
257*4882a593Smuzhiyun mutex_unlock(&info->mutex);
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun return ret;
260*4882a593Smuzhiyun }
261*4882a593Smuzhiyun
sun4i_gpadc_adc_read(struct iio_dev * indio_dev,int channel,int * val)262*4882a593Smuzhiyun static int sun4i_gpadc_adc_read(struct iio_dev *indio_dev, int channel,
263*4882a593Smuzhiyun int *val)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun return sun4i_gpadc_read(indio_dev, channel, val, info->fifo_data_irq);
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun
sun4i_gpadc_temp_read(struct iio_dev * indio_dev,int * val)270*4882a593Smuzhiyun static int sun4i_gpadc_temp_read(struct iio_dev *indio_dev, int *val)
271*4882a593Smuzhiyun {
272*4882a593Smuzhiyun struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun if (info->no_irq) {
275*4882a593Smuzhiyun pm_runtime_get_sync(indio_dev->dev.parent);
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, val);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun pm_runtime_mark_last_busy(indio_dev->dev.parent);
280*4882a593Smuzhiyun pm_runtime_put_autosuspend(indio_dev->dev.parent);
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun return 0;
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun return sun4i_gpadc_read(indio_dev, 0, val, info->temp_data_irq);
286*4882a593Smuzhiyun }
287*4882a593Smuzhiyun
sun4i_gpadc_temp_offset(struct iio_dev * indio_dev,int * val)288*4882a593Smuzhiyun static int sun4i_gpadc_temp_offset(struct iio_dev *indio_dev, int *val)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun *val = info->data->temp_offset;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun return 0;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
sun4i_gpadc_temp_scale(struct iio_dev * indio_dev,int * val)297*4882a593Smuzhiyun static int sun4i_gpadc_temp_scale(struct iio_dev *indio_dev, int *val)
298*4882a593Smuzhiyun {
299*4882a593Smuzhiyun struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun *val = info->data->temp_scale;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun return 0;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun
sun4i_gpadc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)306*4882a593Smuzhiyun static int sun4i_gpadc_read_raw(struct iio_dev *indio_dev,
307*4882a593Smuzhiyun struct iio_chan_spec const *chan, int *val,
308*4882a593Smuzhiyun int *val2, long mask)
309*4882a593Smuzhiyun {
310*4882a593Smuzhiyun int ret;
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun switch (mask) {
313*4882a593Smuzhiyun case IIO_CHAN_INFO_OFFSET:
314*4882a593Smuzhiyun ret = sun4i_gpadc_temp_offset(indio_dev, val);
315*4882a593Smuzhiyun if (ret)
316*4882a593Smuzhiyun return ret;
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun return IIO_VAL_INT;
319*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
320*4882a593Smuzhiyun if (chan->type == IIO_VOLTAGE)
321*4882a593Smuzhiyun ret = sun4i_gpadc_adc_read(indio_dev, chan->channel,
322*4882a593Smuzhiyun val);
323*4882a593Smuzhiyun else
324*4882a593Smuzhiyun ret = sun4i_gpadc_temp_read(indio_dev, val);
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun if (ret)
327*4882a593Smuzhiyun return ret;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun return IIO_VAL_INT;
330*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
331*4882a593Smuzhiyun if (chan->type == IIO_VOLTAGE) {
332*4882a593Smuzhiyun /* 3000mV / 4096 * raw */
333*4882a593Smuzhiyun *val = 0;
334*4882a593Smuzhiyun *val2 = 732421875;
335*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_NANO;
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun ret = sun4i_gpadc_temp_scale(indio_dev, val);
339*4882a593Smuzhiyun if (ret)
340*4882a593Smuzhiyun return ret;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun return IIO_VAL_INT;
343*4882a593Smuzhiyun default:
344*4882a593Smuzhiyun return -EINVAL;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun return -EINVAL;
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun static const struct iio_info sun4i_gpadc_iio_info = {
351*4882a593Smuzhiyun .read_raw = sun4i_gpadc_read_raw,
352*4882a593Smuzhiyun };
353*4882a593Smuzhiyun
sun4i_gpadc_temp_data_irq_handler(int irq,void * dev_id)354*4882a593Smuzhiyun static irqreturn_t sun4i_gpadc_temp_data_irq_handler(int irq, void *dev_id)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun struct sun4i_gpadc_iio *info = dev_id;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun if (atomic_read(&info->ignore_temp_data_irq))
359*4882a593Smuzhiyun goto out;
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun if (!regmap_read(info->regmap, SUN4I_GPADC_TEMP_DATA, &info->temp_data))
362*4882a593Smuzhiyun complete(&info->completion);
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun out:
365*4882a593Smuzhiyun return IRQ_HANDLED;
366*4882a593Smuzhiyun }
367*4882a593Smuzhiyun
sun4i_gpadc_fifo_data_irq_handler(int irq,void * dev_id)368*4882a593Smuzhiyun static irqreturn_t sun4i_gpadc_fifo_data_irq_handler(int irq, void *dev_id)
369*4882a593Smuzhiyun {
370*4882a593Smuzhiyun struct sun4i_gpadc_iio *info = dev_id;
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun if (atomic_read(&info->ignore_fifo_data_irq))
373*4882a593Smuzhiyun goto out;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun if (!regmap_read(info->regmap, SUN4I_GPADC_DATA, &info->adc_data))
376*4882a593Smuzhiyun complete(&info->completion);
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun out:
379*4882a593Smuzhiyun return IRQ_HANDLED;
380*4882a593Smuzhiyun }
381*4882a593Smuzhiyun
sun4i_gpadc_runtime_suspend(struct device * dev)382*4882a593Smuzhiyun static int sun4i_gpadc_runtime_suspend(struct device *dev)
383*4882a593Smuzhiyun {
384*4882a593Smuzhiyun struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun /* Disable the ADC on IP */
387*4882a593Smuzhiyun regmap_write(info->regmap, SUN4I_GPADC_CTRL1, 0);
388*4882a593Smuzhiyun /* Disable temperature sensor on IP */
389*4882a593Smuzhiyun regmap_write(info->regmap, SUN4I_GPADC_TPR, 0);
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun return 0;
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun
sun4i_gpadc_runtime_resume(struct device * dev)394*4882a593Smuzhiyun static int sun4i_gpadc_runtime_resume(struct device *dev)
395*4882a593Smuzhiyun {
396*4882a593Smuzhiyun struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(dev));
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun /* clkin = 6MHz */
399*4882a593Smuzhiyun regmap_write(info->regmap, SUN4I_GPADC_CTRL0,
400*4882a593Smuzhiyun SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(2) |
401*4882a593Smuzhiyun SUN4I_GPADC_CTRL0_FS_DIV(7) |
402*4882a593Smuzhiyun SUN4I_GPADC_CTRL0_T_ACQ(63));
403*4882a593Smuzhiyun regmap_write(info->regmap, SUN4I_GPADC_CTRL1, info->data->tp_mode_en);
404*4882a593Smuzhiyun regmap_write(info->regmap, SUN4I_GPADC_CTRL3,
405*4882a593Smuzhiyun SUN4I_GPADC_CTRL3_FILTER_EN |
406*4882a593Smuzhiyun SUN4I_GPADC_CTRL3_FILTER_TYPE(1));
407*4882a593Smuzhiyun /* period = SUN4I_GPADC_TPR_TEMP_PERIOD * 256 * 16 / clkin; ~0.6s */
408*4882a593Smuzhiyun regmap_write(info->regmap, SUN4I_GPADC_TPR,
409*4882a593Smuzhiyun SUN4I_GPADC_TPR_TEMP_ENABLE |
410*4882a593Smuzhiyun SUN4I_GPADC_TPR_TEMP_PERIOD(800));
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun return 0;
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun
sun4i_gpadc_get_temp(void * data,int * temp)415*4882a593Smuzhiyun static int sun4i_gpadc_get_temp(void *data, int *temp)
416*4882a593Smuzhiyun {
417*4882a593Smuzhiyun struct sun4i_gpadc_iio *info = data;
418*4882a593Smuzhiyun int val, scale, offset;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun if (sun4i_gpadc_temp_read(info->indio_dev, &val))
421*4882a593Smuzhiyun return -ETIMEDOUT;
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun sun4i_gpadc_temp_scale(info->indio_dev, &scale);
424*4882a593Smuzhiyun sun4i_gpadc_temp_offset(info->indio_dev, &offset);
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun *temp = (val + offset) * scale;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun return 0;
429*4882a593Smuzhiyun }
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun static const struct thermal_zone_of_device_ops sun4i_ts_tz_ops = {
432*4882a593Smuzhiyun .get_temp = &sun4i_gpadc_get_temp,
433*4882a593Smuzhiyun };
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun static const struct dev_pm_ops sun4i_gpadc_pm_ops = {
436*4882a593Smuzhiyun .runtime_suspend = &sun4i_gpadc_runtime_suspend,
437*4882a593Smuzhiyun .runtime_resume = &sun4i_gpadc_runtime_resume,
438*4882a593Smuzhiyun };
439*4882a593Smuzhiyun
sun4i_irq_init(struct platform_device * pdev,const char * name,irq_handler_t handler,const char * devname,unsigned int * irq,atomic_t * atomic)440*4882a593Smuzhiyun static int sun4i_irq_init(struct platform_device *pdev, const char *name,
441*4882a593Smuzhiyun irq_handler_t handler, const char *devname,
442*4882a593Smuzhiyun unsigned int *irq, atomic_t *atomic)
443*4882a593Smuzhiyun {
444*4882a593Smuzhiyun int ret;
445*4882a593Smuzhiyun struct sun4i_gpadc_dev *mfd_dev = dev_get_drvdata(pdev->dev.parent);
446*4882a593Smuzhiyun struct sun4i_gpadc_iio *info = iio_priv(dev_get_drvdata(&pdev->dev));
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun /*
449*4882a593Smuzhiyun * Once the interrupt is activated, the IP continuously performs
450*4882a593Smuzhiyun * conversions thus throws interrupts. The interrupt is activated right
451*4882a593Smuzhiyun * after being requested but we want to control when these interrupts
452*4882a593Smuzhiyun * occur thus we disable it right after being requested. However, an
453*4882a593Smuzhiyun * interrupt might occur between these two instructions and we have to
454*4882a593Smuzhiyun * make sure that does not happen, by using atomic flags. We set the
455*4882a593Smuzhiyun * flag before requesting the interrupt and unset it right after
456*4882a593Smuzhiyun * disabling the interrupt. When an interrupt occurs between these two
457*4882a593Smuzhiyun * instructions, reading the atomic flag will tell us to ignore the
458*4882a593Smuzhiyun * interrupt.
459*4882a593Smuzhiyun */
460*4882a593Smuzhiyun atomic_set(atomic, 1);
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun ret = platform_get_irq_byname(pdev, name);
463*4882a593Smuzhiyun if (ret < 0)
464*4882a593Smuzhiyun return ret;
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun ret = regmap_irq_get_virq(mfd_dev->regmap_irqc, ret);
467*4882a593Smuzhiyun if (ret < 0) {
468*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get virq for irq %s\n", name);
469*4882a593Smuzhiyun return ret;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun *irq = ret;
473*4882a593Smuzhiyun ret = devm_request_any_context_irq(&pdev->dev, *irq, handler, 0,
474*4882a593Smuzhiyun devname, info);
475*4882a593Smuzhiyun if (ret < 0) {
476*4882a593Smuzhiyun dev_err(&pdev->dev, "could not request %s interrupt: %d\n",
477*4882a593Smuzhiyun name, ret);
478*4882a593Smuzhiyun return ret;
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun disable_irq(*irq);
482*4882a593Smuzhiyun atomic_set(atomic, 0);
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun return 0;
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun static const struct of_device_id sun4i_gpadc_of_id[] = {
488*4882a593Smuzhiyun {
489*4882a593Smuzhiyun .compatible = "allwinner,sun8i-a33-ths",
490*4882a593Smuzhiyun .data = &sun8i_a33_gpadc_data,
491*4882a593Smuzhiyun },
492*4882a593Smuzhiyun { /* sentinel */ }
493*4882a593Smuzhiyun };
494*4882a593Smuzhiyun
sun4i_gpadc_probe_dt(struct platform_device * pdev,struct iio_dev * indio_dev)495*4882a593Smuzhiyun static int sun4i_gpadc_probe_dt(struct platform_device *pdev,
496*4882a593Smuzhiyun struct iio_dev *indio_dev)
497*4882a593Smuzhiyun {
498*4882a593Smuzhiyun struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
499*4882a593Smuzhiyun void __iomem *base;
500*4882a593Smuzhiyun int ret;
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun info->data = of_device_get_match_data(&pdev->dev);
503*4882a593Smuzhiyun if (!info->data)
504*4882a593Smuzhiyun return -ENODEV;
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun info->no_irq = true;
507*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(sun8i_a33_gpadc_channels);
508*4882a593Smuzhiyun indio_dev->channels = sun8i_a33_gpadc_channels;
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun base = devm_platform_ioremap_resource(pdev, 0);
511*4882a593Smuzhiyun if (IS_ERR(base))
512*4882a593Smuzhiyun return PTR_ERR(base);
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun info->regmap = devm_regmap_init_mmio(&pdev->dev, base,
515*4882a593Smuzhiyun &sun4i_gpadc_regmap_config);
516*4882a593Smuzhiyun if (IS_ERR(info->regmap)) {
517*4882a593Smuzhiyun ret = PTR_ERR(info->regmap);
518*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to init regmap: %d\n", ret);
519*4882a593Smuzhiyun return ret;
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_THERMAL_OF))
523*4882a593Smuzhiyun info->sensor_device = &pdev->dev;
524*4882a593Smuzhiyun
525*4882a593Smuzhiyun return 0;
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun
sun4i_gpadc_probe_mfd(struct platform_device * pdev,struct iio_dev * indio_dev)528*4882a593Smuzhiyun static int sun4i_gpadc_probe_mfd(struct platform_device *pdev,
529*4882a593Smuzhiyun struct iio_dev *indio_dev)
530*4882a593Smuzhiyun {
531*4882a593Smuzhiyun struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
532*4882a593Smuzhiyun struct sun4i_gpadc_dev *sun4i_gpadc_dev =
533*4882a593Smuzhiyun dev_get_drvdata(pdev->dev.parent);
534*4882a593Smuzhiyun int ret;
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun info->no_irq = false;
537*4882a593Smuzhiyun info->regmap = sun4i_gpadc_dev->regmap;
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(sun4i_gpadc_channels);
540*4882a593Smuzhiyun indio_dev->channels = sun4i_gpadc_channels;
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun info->data = (struct gpadc_data *)platform_get_device_id(pdev)->driver_data;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun /*
545*4882a593Smuzhiyun * Since the controller needs to be in touchscreen mode for its thermal
546*4882a593Smuzhiyun * sensor to operate properly, and that switching between the two modes
547*4882a593Smuzhiyun * needs a delay, always registering in the thermal framework will
548*4882a593Smuzhiyun * significantly slow down the conversion rate of the ADCs.
549*4882a593Smuzhiyun *
550*4882a593Smuzhiyun * Therefore, instead of depending on THERMAL_OF in Kconfig, we only
551*4882a593Smuzhiyun * register the sensor if that option is enabled, eventually leaving
552*4882a593Smuzhiyun * that choice to the user.
553*4882a593Smuzhiyun */
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_THERMAL_OF)) {
556*4882a593Smuzhiyun /*
557*4882a593Smuzhiyun * This driver is a child of an MFD which has a node in the DT
558*4882a593Smuzhiyun * but not its children, because of DT backward compatibility
559*4882a593Smuzhiyun * for A10, A13 and A31 SoCs. Therefore, the resulting devices
560*4882a593Smuzhiyun * of this driver do not have an of_node variable.
561*4882a593Smuzhiyun * However, its parent (the MFD driver) has an of_node variable
562*4882a593Smuzhiyun * and since devm_thermal_zone_of_sensor_register uses its first
563*4882a593Smuzhiyun * argument to match the phandle defined in the node of the
564*4882a593Smuzhiyun * thermal driver with the of_node of the device passed as first
565*4882a593Smuzhiyun * argument and the third argument to call ops from
566*4882a593Smuzhiyun * thermal_zone_of_device_ops, the solution is to use the parent
567*4882a593Smuzhiyun * device as first argument to match the phandle with its
568*4882a593Smuzhiyun * of_node, and the device from this driver as third argument to
569*4882a593Smuzhiyun * return the temperature.
570*4882a593Smuzhiyun */
571*4882a593Smuzhiyun info->sensor_device = pdev->dev.parent;
572*4882a593Smuzhiyun } else {
573*4882a593Smuzhiyun indio_dev->num_channels =
574*4882a593Smuzhiyun ARRAY_SIZE(sun4i_gpadc_channels_no_temp);
575*4882a593Smuzhiyun indio_dev->channels = sun4i_gpadc_channels_no_temp;
576*4882a593Smuzhiyun }
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_THERMAL_OF)) {
579*4882a593Smuzhiyun ret = sun4i_irq_init(pdev, "TEMP_DATA_PENDING",
580*4882a593Smuzhiyun sun4i_gpadc_temp_data_irq_handler,
581*4882a593Smuzhiyun "temp_data", &info->temp_data_irq,
582*4882a593Smuzhiyun &info->ignore_temp_data_irq);
583*4882a593Smuzhiyun if (ret < 0)
584*4882a593Smuzhiyun return ret;
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun ret = sun4i_irq_init(pdev, "FIFO_DATA_PENDING",
588*4882a593Smuzhiyun sun4i_gpadc_fifo_data_irq_handler, "fifo_data",
589*4882a593Smuzhiyun &info->fifo_data_irq, &info->ignore_fifo_data_irq);
590*4882a593Smuzhiyun if (ret < 0)
591*4882a593Smuzhiyun return ret;
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_THERMAL_OF)) {
594*4882a593Smuzhiyun ret = iio_map_array_register(indio_dev, sun4i_gpadc_hwmon_maps);
595*4882a593Smuzhiyun if (ret < 0) {
596*4882a593Smuzhiyun dev_err(&pdev->dev,
597*4882a593Smuzhiyun "failed to register iio map array\n");
598*4882a593Smuzhiyun return ret;
599*4882a593Smuzhiyun }
600*4882a593Smuzhiyun }
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun return 0;
603*4882a593Smuzhiyun }
604*4882a593Smuzhiyun
sun4i_gpadc_probe(struct platform_device * pdev)605*4882a593Smuzhiyun static int sun4i_gpadc_probe(struct platform_device *pdev)
606*4882a593Smuzhiyun {
607*4882a593Smuzhiyun struct sun4i_gpadc_iio *info;
608*4882a593Smuzhiyun struct iio_dev *indio_dev;
609*4882a593Smuzhiyun int ret;
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
612*4882a593Smuzhiyun if (!indio_dev)
613*4882a593Smuzhiyun return -ENOMEM;
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun info = iio_priv(indio_dev);
616*4882a593Smuzhiyun platform_set_drvdata(pdev, indio_dev);
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun mutex_init(&info->mutex);
619*4882a593Smuzhiyun info->indio_dev = indio_dev;
620*4882a593Smuzhiyun init_completion(&info->completion);
621*4882a593Smuzhiyun indio_dev->name = dev_name(&pdev->dev);
622*4882a593Smuzhiyun indio_dev->info = &sun4i_gpadc_iio_info;
623*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
624*4882a593Smuzhiyun
625*4882a593Smuzhiyun if (pdev->dev.of_node)
626*4882a593Smuzhiyun ret = sun4i_gpadc_probe_dt(pdev, indio_dev);
627*4882a593Smuzhiyun else
628*4882a593Smuzhiyun ret = sun4i_gpadc_probe_mfd(pdev, indio_dev);
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun if (ret)
631*4882a593Smuzhiyun return ret;
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun pm_runtime_set_autosuspend_delay(&pdev->dev,
634*4882a593Smuzhiyun SUN4I_GPADC_AUTOSUSPEND_DELAY);
635*4882a593Smuzhiyun pm_runtime_use_autosuspend(&pdev->dev);
636*4882a593Smuzhiyun pm_runtime_set_suspended(&pdev->dev);
637*4882a593Smuzhiyun pm_runtime_enable(&pdev->dev);
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_THERMAL_OF)) {
640*4882a593Smuzhiyun info->tzd = thermal_zone_of_sensor_register(info->sensor_device,
641*4882a593Smuzhiyun 0, info,
642*4882a593Smuzhiyun &sun4i_ts_tz_ops);
643*4882a593Smuzhiyun /*
644*4882a593Smuzhiyun * Do not fail driver probing when failing to register in
645*4882a593Smuzhiyun * thermal because no thermal DT node is found.
646*4882a593Smuzhiyun */
647*4882a593Smuzhiyun if (IS_ERR(info->tzd) && PTR_ERR(info->tzd) != -ENODEV) {
648*4882a593Smuzhiyun dev_err(&pdev->dev,
649*4882a593Smuzhiyun "could not register thermal sensor: %ld\n",
650*4882a593Smuzhiyun PTR_ERR(info->tzd));
651*4882a593Smuzhiyun return PTR_ERR(info->tzd);
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun }
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun ret = devm_iio_device_register(&pdev->dev, indio_dev);
656*4882a593Smuzhiyun if (ret < 0) {
657*4882a593Smuzhiyun dev_err(&pdev->dev, "could not register the device\n");
658*4882a593Smuzhiyun goto err_map;
659*4882a593Smuzhiyun }
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun return 0;
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun err_map:
664*4882a593Smuzhiyun if (!info->no_irq && IS_ENABLED(CONFIG_THERMAL_OF))
665*4882a593Smuzhiyun iio_map_array_unregister(indio_dev);
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun pm_runtime_put(&pdev->dev);
668*4882a593Smuzhiyun pm_runtime_disable(&pdev->dev);
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun return ret;
671*4882a593Smuzhiyun }
672*4882a593Smuzhiyun
sun4i_gpadc_remove(struct platform_device * pdev)673*4882a593Smuzhiyun static int sun4i_gpadc_remove(struct platform_device *pdev)
674*4882a593Smuzhiyun {
675*4882a593Smuzhiyun struct iio_dev *indio_dev = platform_get_drvdata(pdev);
676*4882a593Smuzhiyun struct sun4i_gpadc_iio *info = iio_priv(indio_dev);
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun pm_runtime_put(&pdev->dev);
679*4882a593Smuzhiyun pm_runtime_disable(&pdev->dev);
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun if (!IS_ENABLED(CONFIG_THERMAL_OF))
682*4882a593Smuzhiyun return 0;
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun thermal_zone_of_sensor_unregister(info->sensor_device, info->tzd);
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun if (!info->no_irq)
687*4882a593Smuzhiyun iio_map_array_unregister(indio_dev);
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun return 0;
690*4882a593Smuzhiyun }
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun static const struct platform_device_id sun4i_gpadc_id[] = {
693*4882a593Smuzhiyun { "sun4i-a10-gpadc-iio", (kernel_ulong_t)&sun4i_gpadc_data },
694*4882a593Smuzhiyun { "sun5i-a13-gpadc-iio", (kernel_ulong_t)&sun5i_gpadc_data },
695*4882a593Smuzhiyun { "sun6i-a31-gpadc-iio", (kernel_ulong_t)&sun6i_gpadc_data },
696*4882a593Smuzhiyun { /* sentinel */ },
697*4882a593Smuzhiyun };
698*4882a593Smuzhiyun MODULE_DEVICE_TABLE(platform, sun4i_gpadc_id);
699*4882a593Smuzhiyun
700*4882a593Smuzhiyun static struct platform_driver sun4i_gpadc_driver = {
701*4882a593Smuzhiyun .driver = {
702*4882a593Smuzhiyun .name = "sun4i-gpadc-iio",
703*4882a593Smuzhiyun .of_match_table = sun4i_gpadc_of_id,
704*4882a593Smuzhiyun .pm = &sun4i_gpadc_pm_ops,
705*4882a593Smuzhiyun },
706*4882a593Smuzhiyun .id_table = sun4i_gpadc_id,
707*4882a593Smuzhiyun .probe = sun4i_gpadc_probe,
708*4882a593Smuzhiyun .remove = sun4i_gpadc_remove,
709*4882a593Smuzhiyun };
710*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, sun4i_gpadc_of_id);
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun module_platform_driver(sun4i_gpadc_driver);
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun MODULE_DESCRIPTION("ADC driver for sunxi platforms");
715*4882a593Smuzhiyun MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
716*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
717