1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Rockchip Successive Approximation Register (SAR) A/D Converter
4 * Copyright (C) 2014 ROCKCHIP, Inc.
5 */
6
7 #include <linux/module.h>
8 #include <linux/platform_device.h>
9 #include <linux/interrupt.h>
10 #include <linux/io.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/clk.h>
14 #include <linux/completion.h>
15 #include <linux/delay.h>
16 #include <linux/reset.h>
17 #include <linux/regulator/consumer.h>
18 #include <linux/iio/buffer.h>
19 #include <linux/iio/iio.h>
20 #include <linux/iio/trigger_consumer.h>
21 #include <linux/iio/triggered_buffer.h>
22
23 #define SARADC_DATA 0x00
24
25 #define SARADC_STAS 0x04
26 #define SARADC_STAS_BUSY BIT(0)
27
28 #define SARADC_CTRL 0x08
29 #define SARADC_CTRL_IRQ_STATUS BIT(6)
30 #define SARADC_CTRL_IRQ_ENABLE BIT(5)
31 #define SARADC_CTRL_POWER_CTRL BIT(3)
32 #define SARADC_CTRL_CHN_MASK 0x7
33
34 #define SARADC_DLY_PU_SOC 0x0c
35 #define SARADC_DLY_PU_SOC_MASK 0x3f
36
37 #define SARADC_TIMEOUT msecs_to_jiffies(100)
38 #define SARADC_MAX_CHANNELS 8
39
40 /* v2 registers */
41 #define SARADC2_CONV_CON 0x0
42 #define SARADC_T_PD_SOC 0x4
43 #define SARADC_T_DAS_SOC 0xc
44 #define SARADC2_END_INT_EN 0x104
45 #define SARADC2_ST_CON 0x108
46 #define SARADC2_STATUS 0x10c
47 #define SARADC2_END_INT_ST 0x110
48 #define SARADC2_DATA_BASE 0x120
49
50 #define SARADC2_EN_END_INT BIT(0)
51 #define SARADC2_START BIT(4)
52 #define SARADC2_SINGLE_MODE BIT(5)
53
54 struct rockchip_saradc;
55
56 struct rockchip_saradc_data {
57 const struct iio_chan_spec *channels;
58 int num_channels;
59 unsigned long clk_rate;
60 void (*start)(struct rockchip_saradc *info, int chn);
61 int (*read)(struct rockchip_saradc *info);
62 void (*power_down)(struct rockchip_saradc *info);
63 };
64
65 struct rockchip_saradc {
66 void __iomem *regs;
67 struct clk *pclk;
68 struct clk *clk;
69 struct completion completion;
70 struct regulator *vref;
71 int uv_vref;
72 struct reset_control *reset;
73 const struct rockchip_saradc_data *data;
74 u16 last_val;
75 const struct iio_chan_spec *last_chan;
76 struct notifier_block nb;
77 bool suspended;
78 #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
79 bool test;
80 u32 chn;
81 spinlock_t lock;
82 struct workqueue_struct *wq;
83 struct delayed_work work;
84 #endif
85 };
86
87 static void rockchip_saradc_reset_controller(struct reset_control *reset);
88
rockchip_saradc_start_v1(struct rockchip_saradc * info,int chn)89 static void rockchip_saradc_start_v1(struct rockchip_saradc *info,
90 int chn)
91 {
92 /* 8 clock periods as delay between power up and start cmd */
93 writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
94 /* Select the channel to be used and trigger conversion */
95 writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) |
96 SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL);
97 }
98
rockchip_saradc_start_v2(struct rockchip_saradc * info,int chn)99 static void rockchip_saradc_start_v2(struct rockchip_saradc *info,
100 int chn)
101 {
102 int val;
103
104 /* If read other chn at anytime, then chn1 will error, assert
105 * controller as a workaround.
106 */
107 if (info->reset)
108 rockchip_saradc_reset_controller(info->reset);
109
110 writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
111 writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
112 val = SARADC2_EN_END_INT << 16 | SARADC2_EN_END_INT;
113 writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
114 val = SARADC2_START | SARADC2_SINGLE_MODE | chn;
115 writel(val << 16 | val, info->regs + SARADC2_CONV_CON);
116 }
117
rockchip_saradc_start(struct rockchip_saradc * info,int chn)118 static void rockchip_saradc_start(struct rockchip_saradc *info,
119 int chn)
120 {
121 info->data->start(info, chn);
122 }
123
rockchip_saradc_read_v1(struct rockchip_saradc * info)124 static int rockchip_saradc_read_v1(struct rockchip_saradc *info)
125 {
126 return readl_relaxed(info->regs + SARADC_DATA);
127 }
128
rockchip_saradc_read_v2(struct rockchip_saradc * info)129 static int rockchip_saradc_read_v2(struct rockchip_saradc *info)
130 {
131 int offset;
132 int channel;
133
134 /* Clear irq */
135 writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST);
136
137 #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
138 channel = info->chn;
139 #else
140 channel = info->last_chan->channel;
141 #endif
142
143 offset = SARADC2_DATA_BASE + channel * 0x4;
144
145 return readl_relaxed(info->regs + offset);
146 }
147
rockchip_saradc_read(struct rockchip_saradc * info)148 static int rockchip_saradc_read(struct rockchip_saradc *info)
149 {
150 return info->data->read(info);
151 }
152
rockchip_saradc_power_down_v1(struct rockchip_saradc * info)153 static void rockchip_saradc_power_down_v1(struct rockchip_saradc *info)
154 {
155 writel_relaxed(0, info->regs + SARADC_CTRL);
156 }
157
rockchip_saradc_power_down(struct rockchip_saradc * info)158 static void rockchip_saradc_power_down(struct rockchip_saradc *info)
159 {
160 if (info->data->power_down)
161 info->data->power_down(info);
162 }
163
rockchip_saradc_conversion(struct rockchip_saradc * info,struct iio_chan_spec const * chan)164 static int rockchip_saradc_conversion(struct rockchip_saradc *info,
165 struct iio_chan_spec const *chan)
166 {
167 reinit_completion(&info->completion);
168
169 /* prevent isr get NULL last_chan */
170 info->last_chan = chan;
171 rockchip_saradc_start(info, chan->channel);
172
173 if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
174 return -ETIMEDOUT;
175
176 return 0;
177 }
178
rockchip_saradc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)179 static int rockchip_saradc_read_raw(struct iio_dev *indio_dev,
180 struct iio_chan_spec const *chan,
181 int *val, int *val2, long mask)
182 {
183 struct rockchip_saradc *info = iio_priv(indio_dev);
184 int ret;
185
186 #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
187 if (info->test)
188 return 0;
189 #endif
190 switch (mask) {
191 case IIO_CHAN_INFO_RAW:
192 mutex_lock(&indio_dev->mlock);
193
194 if (info->suspended) {
195 mutex_unlock(&indio_dev->mlock);
196 return -EBUSY;
197 }
198
199 ret = rockchip_saradc_conversion(info, chan);
200 if (ret) {
201 rockchip_saradc_power_down(info);
202 mutex_unlock(&indio_dev->mlock);
203 return ret;
204 }
205
206 *val = info->last_val;
207 mutex_unlock(&indio_dev->mlock);
208 return IIO_VAL_INT;
209 case IIO_CHAN_INFO_SCALE:
210 /* It is a dummy regulator */
211 if (info->uv_vref < 0)
212 return info->uv_vref;
213
214 *val = info->uv_vref / 1000;
215 *val2 = chan->scan_type.realbits;
216 return IIO_VAL_FRACTIONAL_LOG2;
217 default:
218 return -EINVAL;
219 }
220 }
221
rockchip_saradc_isr(int irq,void * dev_id)222 static irqreturn_t rockchip_saradc_isr(int irq, void *dev_id)
223 {
224 struct rockchip_saradc *info = dev_id;
225 #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
226 unsigned long flags;
227 #endif
228
229 /* Read value */
230 info->last_val = rockchip_saradc_read(info);
231 #ifndef CONFIG_ROCKCHIP_SARADC_TEST_CHN
232 info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
233 #endif
234
235 rockchip_saradc_power_down(info);
236
237 complete(&info->completion);
238 #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
239 spin_lock_irqsave(&info->lock, flags);
240 if (info->test) {
241 pr_info("chn[%d] val = %d\n", info->chn, info->last_val);
242 mod_delayed_work(info->wq, &info->work, msecs_to_jiffies(100));
243 }
244 spin_unlock_irqrestore(&info->lock, flags);
245 #endif
246 return IRQ_HANDLED;
247 }
248
249 static const struct iio_info rockchip_saradc_iio_info = {
250 .read_raw = rockchip_saradc_read_raw,
251 };
252
253 #define SARADC_CHANNEL(_index, _id, _res) { \
254 .type = IIO_VOLTAGE, \
255 .indexed = 1, \
256 .channel = _index, \
257 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
258 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
259 .datasheet_name = _id, \
260 .scan_index = _index, \
261 .scan_type = { \
262 .sign = 'u', \
263 .realbits = _res, \
264 .storagebits = 16, \
265 .endianness = IIO_CPU, \
266 }, \
267 }
268
269 static const struct iio_chan_spec rockchip_saradc_iio_channels[] = {
270 SARADC_CHANNEL(0, "adc0", 10),
271 SARADC_CHANNEL(1, "adc1", 10),
272 SARADC_CHANNEL(2, "adc2", 10),
273 };
274
275 static const struct rockchip_saradc_data saradc_data = {
276 .channels = rockchip_saradc_iio_channels,
277 .num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
278 .clk_rate = 1000000,
279 .start = rockchip_saradc_start_v1,
280 .read = rockchip_saradc_read_v1,
281 .power_down = rockchip_saradc_power_down_v1,
282 };
283
284 static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
285 SARADC_CHANNEL(0, "adc0", 12),
286 SARADC_CHANNEL(1, "adc1", 12),
287 };
288
289 static const struct rockchip_saradc_data rk3066_tsadc_data = {
290 .channels = rockchip_rk3066_tsadc_iio_channels,
291 .num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
292 .clk_rate = 50000,
293 .start = rockchip_saradc_start_v1,
294 .read = rockchip_saradc_read_v1,
295 .power_down = rockchip_saradc_power_down_v1,
296 };
297
298 static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
299 SARADC_CHANNEL(0, "adc0", 10),
300 SARADC_CHANNEL(1, "adc1", 10),
301 SARADC_CHANNEL(2, "adc2", 10),
302 SARADC_CHANNEL(3, "adc3", 10),
303 SARADC_CHANNEL(4, "adc4", 10),
304 SARADC_CHANNEL(5, "adc5", 10),
305 };
306
307 static const struct rockchip_saradc_data rk3399_saradc_data = {
308 .channels = rockchip_rk3399_saradc_iio_channels,
309 .num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
310 .clk_rate = 1000000,
311 .start = rockchip_saradc_start_v1,
312 .read = rockchip_saradc_read_v1,
313 .power_down = rockchip_saradc_power_down_v1,
314 };
315
316 static const struct iio_chan_spec rockchip_rk3528_saradc_iio_channels[] = {
317 SARADC_CHANNEL(0, "adc0", 10),
318 SARADC_CHANNEL(1, "adc1", 10),
319 SARADC_CHANNEL(2, "adc2", 10),
320 SARADC_CHANNEL(3, "adc3", 10),
321 };
322
323 static const struct rockchip_saradc_data rk3528_saradc_data = {
324 .channels = rockchip_rk3528_saradc_iio_channels,
325 .num_channels = ARRAY_SIZE(rockchip_rk3528_saradc_iio_channels),
326 .clk_rate = 1000000,
327 .start = rockchip_saradc_start_v2,
328 .read = rockchip_saradc_read_v2,
329 };
330
331 static const struct iio_chan_spec rockchip_rk3562_saradc_iio_channels[] = {
332 SARADC_CHANNEL(0, "adc0", 10),
333 SARADC_CHANNEL(1, "adc1", 10),
334 SARADC_CHANNEL(2, "adc2", 10),
335 SARADC_CHANNEL(3, "adc3", 10),
336 SARADC_CHANNEL(4, "adc4", 10),
337 SARADC_CHANNEL(5, "adc5", 10),
338 SARADC_CHANNEL(6, "adc6", 10),
339 SARADC_CHANNEL(7, "adc7", 10),
340 };
341
342 static const struct rockchip_saradc_data rk3562_saradc_data = {
343 .channels = rockchip_rk3562_saradc_iio_channels,
344 .num_channels = ARRAY_SIZE(rockchip_rk3562_saradc_iio_channels),
345 .clk_rate = 1000000,
346 .start = rockchip_saradc_start_v2,
347 .read = rockchip_saradc_read_v2,
348 };
349
350 static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = {
351 SARADC_CHANNEL(0, "adc0", 10),
352 SARADC_CHANNEL(1, "adc1", 10),
353 SARADC_CHANNEL(2, "adc2", 10),
354 SARADC_CHANNEL(3, "adc3", 10),
355 SARADC_CHANNEL(4, "adc4", 10),
356 SARADC_CHANNEL(5, "adc5", 10),
357 SARADC_CHANNEL(6, "adc6", 10),
358 SARADC_CHANNEL(7, "adc7", 10),
359 };
360
361 static const struct rockchip_saradc_data rk3568_saradc_data = {
362 .channels = rockchip_rk3568_saradc_iio_channels,
363 .num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels),
364 .clk_rate = 1000000,
365 .start = rockchip_saradc_start_v1,
366 .read = rockchip_saradc_read_v1,
367 .power_down = rockchip_saradc_power_down_v1,
368 };
369
370 static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = {
371 SARADC_CHANNEL(0, "adc0", 12),
372 SARADC_CHANNEL(1, "adc1", 12),
373 SARADC_CHANNEL(2, "adc2", 12),
374 SARADC_CHANNEL(3, "adc3", 12),
375 SARADC_CHANNEL(4, "adc4", 12),
376 SARADC_CHANNEL(5, "adc5", 12),
377 SARADC_CHANNEL(6, "adc6", 12),
378 SARADC_CHANNEL(7, "adc7", 12),
379 };
380
381 static const struct rockchip_saradc_data rk3588_saradc_data = {
382 .channels = rockchip_rk3588_saradc_iio_channels,
383 .num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels),
384 .clk_rate = 1000000,
385 .start = rockchip_saradc_start_v2,
386 .read = rockchip_saradc_read_v2,
387 };
388
389 static const struct iio_chan_spec rockchip_rv1106_saradc_iio_channels[] = {
390 SARADC_CHANNEL(0, "adc0", 10),
391 SARADC_CHANNEL(1, "adc1", 10),
392 };
393
394 static const struct rockchip_saradc_data rv1106_saradc_data = {
395 .channels = rockchip_rv1106_saradc_iio_channels,
396 .num_channels = ARRAY_SIZE(rockchip_rv1106_saradc_iio_channels),
397 .clk_rate = 1000000,
398 .start = rockchip_saradc_start_v2,
399 .read = rockchip_saradc_read_v2,
400 };
401
402 static const struct of_device_id rockchip_saradc_match[] = {
403 {
404 .compatible = "rockchip,saradc",
405 .data = &saradc_data,
406 }, {
407 .compatible = "rockchip,rk3066-tsadc",
408 .data = &rk3066_tsadc_data,
409 }, {
410 .compatible = "rockchip,rk3399-saradc",
411 .data = &rk3399_saradc_data,
412 }, {
413 .compatible = "rockchip,rk3528-saradc",
414 .data = &rk3528_saradc_data,
415 }, {
416 .compatible = "rockchip,rk3562-saradc",
417 .data = &rk3562_saradc_data,
418 }, {
419 .compatible = "rockchip,rk3568-saradc",
420 .data = &rk3568_saradc_data,
421 }, {
422 .compatible = "rockchip,rk3588-saradc",
423 .data = &rk3588_saradc_data,
424 }, {
425 .compatible = "rockchip,rv1106-saradc",
426 .data = &rv1106_saradc_data,
427 },
428 {},
429 };
430 MODULE_DEVICE_TABLE(of, rockchip_saradc_match);
431
432 /*
433 * Reset SARADC Controller.
434 */
rockchip_saradc_reset_controller(struct reset_control * reset)435 static void rockchip_saradc_reset_controller(struct reset_control *reset)
436 {
437 reset_control_assert(reset);
438 usleep_range(10, 20);
439 reset_control_deassert(reset);
440 }
441
rockchip_saradc_clk_disable(void * data)442 static void rockchip_saradc_clk_disable(void *data)
443 {
444 struct rockchip_saradc *info = data;
445
446 clk_disable_unprepare(info->clk);
447 }
448
rockchip_saradc_pclk_disable(void * data)449 static void rockchip_saradc_pclk_disable(void *data)
450 {
451 struct rockchip_saradc *info = data;
452
453 clk_disable_unprepare(info->pclk);
454 }
455
rockchip_saradc_regulator_disable(void * data)456 static void rockchip_saradc_regulator_disable(void *data)
457 {
458 struct rockchip_saradc *info = data;
459
460 regulator_disable(info->vref);
461 }
462
rockchip_saradc_trigger_handler(int irq,void * p)463 static irqreturn_t rockchip_saradc_trigger_handler(int irq, void *p)
464 {
465 struct iio_poll_func *pf = p;
466 struct iio_dev *i_dev = pf->indio_dev;
467 struct rockchip_saradc *info = iio_priv(i_dev);
468 /*
469 * @values: each channel takes an u16 value
470 * @timestamp: will be 8-byte aligned automatically
471 */
472 struct {
473 u16 values[SARADC_MAX_CHANNELS];
474 int64_t timestamp;
475 } data;
476 int ret;
477 int i, j = 0;
478
479 mutex_lock(&i_dev->mlock);
480
481 for_each_set_bit(i, i_dev->active_scan_mask, i_dev->masklength) {
482 const struct iio_chan_spec *chan = &i_dev->channels[i];
483
484 ret = rockchip_saradc_conversion(info, chan);
485 if (ret) {
486 rockchip_saradc_power_down(info);
487 goto out;
488 }
489
490 data.values[j] = info->last_val;
491 j++;
492 }
493
494 iio_push_to_buffers_with_timestamp(i_dev, &data, iio_get_time_ns(i_dev));
495 out:
496 mutex_unlock(&i_dev->mlock);
497
498 iio_trigger_notify_done(i_dev->trig);
499
500 return IRQ_HANDLED;
501 }
502
rockchip_saradc_volt_notify(struct notifier_block * nb,unsigned long event,void * data)503 static int rockchip_saradc_volt_notify(struct notifier_block *nb,
504 unsigned long event,
505 void *data)
506 {
507 struct rockchip_saradc *info =
508 container_of(nb, struct rockchip_saradc, nb);
509
510 if (event & REGULATOR_EVENT_VOLTAGE_CHANGE)
511 info->uv_vref = (unsigned long)data;
512
513 return NOTIFY_OK;
514 }
515
rockchip_saradc_regulator_unreg_notifier(void * data)516 static void rockchip_saradc_regulator_unreg_notifier(void *data)
517 {
518 struct rockchip_saradc *info = data;
519
520 regulator_unregister_notifier(info->vref, &info->nb);
521 }
522
523 #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
saradc_test_chn_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t size)524 static ssize_t saradc_test_chn_store(struct device *dev,
525 struct device_attribute *attr,
526 const char *buf, size_t size)
527 {
528 u32 val = 0;
529 int err;
530 struct iio_dev *indio_dev = dev_get_drvdata(dev);
531 struct rockchip_saradc *info = iio_priv(indio_dev);
532 unsigned long flags;
533
534 err = kstrtou32(buf, 10, &val);
535 if (err)
536 return err;
537
538 spin_lock_irqsave(&info->lock, flags);
539
540 if (val > SARADC_CTRL_CHN_MASK && info->test) {
541 info->test = false;
542 spin_unlock_irqrestore(&info->lock, flags);
543 cancel_delayed_work_sync(&info->work);
544 return size;
545 }
546
547 if (!info->test && val <= SARADC_CTRL_CHN_MASK) {
548 info->test = true;
549 info->chn = val;
550 mod_delayed_work(info->wq, &info->work, msecs_to_jiffies(100));
551 }
552
553 spin_unlock_irqrestore(&info->lock, flags);
554
555 return size;
556 }
557
558 static DEVICE_ATTR_WO(saradc_test_chn);
559
560 static struct attribute *saradc_attrs[] = {
561 &dev_attr_saradc_test_chn.attr,
562 NULL
563 };
564
565 static const struct attribute_group rockchip_saradc_attr_group = {
566 .attrs = saradc_attrs,
567 };
568
rockchip_saradc_remove_sysgroup(void * data)569 static void rockchip_saradc_remove_sysgroup(void *data)
570 {
571 struct platform_device *pdev = data;
572
573 sysfs_remove_group(&pdev->dev.kobj, &rockchip_saradc_attr_group);
574 }
575
rockchip_saradc_destroy_wq(void * data)576 static void rockchip_saradc_destroy_wq(void *data)
577 {
578 struct rockchip_saradc *info = data;
579
580 destroy_workqueue(info->wq);
581 }
582
rockchip_saradc_test_work(struct work_struct * work)583 static void rockchip_saradc_test_work(struct work_struct *work)
584 {
585 struct rockchip_saradc *info = container_of(work,
586 struct rockchip_saradc, work.work);
587
588 rockchip_saradc_start(info, info->chn);
589 }
590 #endif
591
rockchip_saradc_probe(struct platform_device * pdev)592 static int rockchip_saradc_probe(struct platform_device *pdev)
593 {
594 struct rockchip_saradc *info = NULL;
595 struct device_node *np = pdev->dev.of_node;
596 struct iio_dev *indio_dev = NULL;
597 struct resource *mem;
598 const struct of_device_id *match;
599 int ret;
600 int irq;
601
602 if (!np)
603 return -ENODEV;
604
605 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
606 if (!indio_dev) {
607 dev_err(&pdev->dev, "failed allocating iio device\n");
608 return -ENOMEM;
609 }
610 info = iio_priv(indio_dev);
611
612 match = of_match_device(rockchip_saradc_match, &pdev->dev);
613 if (!match) {
614 dev_err(&pdev->dev, "failed to match device\n");
615 return -ENODEV;
616 }
617
618 info->data = match->data;
619
620 /* Sanity check for possible later IP variants with more channels */
621 if (info->data->num_channels > SARADC_MAX_CHANNELS) {
622 dev_err(&pdev->dev, "max channels exceeded");
623 return -EINVAL;
624 }
625
626 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
627 info->regs = devm_ioremap_resource(&pdev->dev, mem);
628 if (IS_ERR(info->regs))
629 return PTR_ERR(info->regs);
630
631 /*
632 * The reset should be an optional property, as it should work
633 * with old devicetrees as well
634 */
635 info->reset = devm_reset_control_get_exclusive(&pdev->dev,
636 "saradc-apb");
637 if (IS_ERR(info->reset)) {
638 ret = PTR_ERR(info->reset);
639 if (ret != -ENOENT)
640 return ret;
641
642 dev_dbg(&pdev->dev, "no reset control found\n");
643 info->reset = NULL;
644 }
645
646 init_completion(&info->completion);
647
648 irq = platform_get_irq(pdev, 0);
649 if (irq < 0)
650 return irq;
651
652 ret = devm_request_irq(&pdev->dev, irq, rockchip_saradc_isr,
653 0, dev_name(&pdev->dev), info);
654 if (ret < 0) {
655 dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
656 return ret;
657 }
658
659 info->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
660 if (IS_ERR(info->pclk)) {
661 dev_err(&pdev->dev, "failed to get pclk\n");
662 return PTR_ERR(info->pclk);
663 }
664
665 info->clk = devm_clk_get(&pdev->dev, "saradc");
666 if (IS_ERR(info->clk)) {
667 dev_err(&pdev->dev, "failed to get adc clock\n");
668 return PTR_ERR(info->clk);
669 }
670
671 info->vref = devm_regulator_get(&pdev->dev, "vref");
672 if (IS_ERR(info->vref)) {
673 dev_err(&pdev->dev, "failed to get regulator, %ld\n",
674 PTR_ERR(info->vref));
675 return PTR_ERR(info->vref);
676 }
677
678 if (info->reset)
679 rockchip_saradc_reset_controller(info->reset);
680
681 /*
682 * Use a default value for the converter clock.
683 * This may become user-configurable in the future.
684 */
685 ret = clk_set_rate(info->clk, info->data->clk_rate);
686 if (ret < 0) {
687 dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret);
688 return ret;
689 }
690
691 ret = regulator_enable(info->vref);
692 if (ret < 0) {
693 dev_err(&pdev->dev, "failed to enable vref regulator\n");
694 return ret;
695 }
696 ret = devm_add_action_or_reset(&pdev->dev,
697 rockchip_saradc_regulator_disable, info);
698 if (ret) {
699 dev_err(&pdev->dev, "failed to register devm action, %d\n",
700 ret);
701 return ret;
702 }
703
704 ret = regulator_get_voltage(info->vref);
705 if (ret < 0) {
706 dev_err(&pdev->dev, "failed to get voltage\n");
707 return ret;
708 }
709
710 info->uv_vref = ret;
711
712 ret = clk_prepare_enable(info->pclk);
713 if (ret < 0) {
714 dev_err(&pdev->dev, "failed to enable pclk\n");
715 return ret;
716 }
717 ret = devm_add_action_or_reset(&pdev->dev,
718 rockchip_saradc_pclk_disable, info);
719 if (ret) {
720 dev_err(&pdev->dev, "failed to register devm action, %d\n",
721 ret);
722 return ret;
723 }
724
725 ret = clk_prepare_enable(info->clk);
726 if (ret < 0) {
727 dev_err(&pdev->dev, "failed to enable converter clock\n");
728 return ret;
729 }
730 ret = devm_add_action_or_reset(&pdev->dev,
731 rockchip_saradc_clk_disable, info);
732 if (ret) {
733 dev_err(&pdev->dev, "failed to register devm action, %d\n",
734 ret);
735 return ret;
736 }
737
738 platform_set_drvdata(pdev, indio_dev);
739
740 indio_dev->name = dev_name(&pdev->dev);
741 indio_dev->info = &rockchip_saradc_iio_info;
742 indio_dev->modes = INDIO_DIRECT_MODE;
743
744 indio_dev->channels = info->data->channels;
745 indio_dev->num_channels = info->data->num_channels;
746 ret = devm_iio_triggered_buffer_setup(&indio_dev->dev, indio_dev, NULL,
747 rockchip_saradc_trigger_handler,
748 NULL);
749 if (ret)
750 return ret;
751
752 info->nb.notifier_call = rockchip_saradc_volt_notify;
753 ret = regulator_register_notifier(info->vref, &info->nb);
754 if (ret)
755 return ret;
756
757 ret = devm_add_action_or_reset(&pdev->dev,
758 rockchip_saradc_regulator_unreg_notifier,
759 info);
760 if (ret)
761 return ret;
762
763 #ifdef CONFIG_ROCKCHIP_SARADC_TEST_CHN
764 info->wq = create_singlethread_workqueue("adc_wq");
765 INIT_DELAYED_WORK(&info->work, rockchip_saradc_test_work);
766 spin_lock_init(&info->lock);
767 ret = sysfs_create_group(&pdev->dev.kobj, &rockchip_saradc_attr_group);
768 if (ret)
769 return ret;
770
771 ret = devm_add_action_or_reset(&pdev->dev,
772 rockchip_saradc_remove_sysgroup, pdev);
773 if (ret) {
774 dev_err(&pdev->dev, "failed to register devm action, %d\n",
775 ret);
776 return ret;
777 }
778
779 ret = devm_add_action_or_reset(&pdev->dev,
780 rockchip_saradc_destroy_wq, info);
781 if (ret) {
782 dev_err(&pdev->dev, "failed to register destroy_wq, %d\n",
783 ret);
784 return ret;
785 }
786 #endif
787 return devm_iio_device_register(&pdev->dev, indio_dev);
788 }
789
790 #ifdef CONFIG_PM_SLEEP
rockchip_saradc_suspend(struct device * dev)791 static int rockchip_saradc_suspend(struct device *dev)
792 {
793 struct iio_dev *indio_dev = dev_get_drvdata(dev);
794 struct rockchip_saradc *info = iio_priv(indio_dev);
795
796 /* Avoid reading saradc when suspending */
797 mutex_lock(&indio_dev->mlock);
798
799 clk_disable_unprepare(info->clk);
800 clk_disable_unprepare(info->pclk);
801 regulator_disable(info->vref);
802
803 info->suspended = true;
804 mutex_unlock(&indio_dev->mlock);
805
806 return 0;
807 }
808
rockchip_saradc_resume(struct device * dev)809 static int rockchip_saradc_resume(struct device *dev)
810 {
811 struct iio_dev *indio_dev = dev_get_drvdata(dev);
812 struct rockchip_saradc *info = iio_priv(indio_dev);
813 int ret;
814
815 ret = regulator_enable(info->vref);
816 if (ret)
817 return ret;
818
819 ret = clk_prepare_enable(info->pclk);
820 if (ret)
821 return ret;
822
823 ret = clk_prepare_enable(info->clk);
824 if (ret)
825 clk_disable_unprepare(info->pclk);
826
827 info->suspended = false;
828
829 return ret;
830 }
831 #endif
832
833 static SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops,
834 rockchip_saradc_suspend, rockchip_saradc_resume);
835
836 static struct platform_driver rockchip_saradc_driver = {
837 .probe = rockchip_saradc_probe,
838 .driver = {
839 .name = "rockchip-saradc",
840 .of_match_table = rockchip_saradc_match,
841 .pm = &rockchip_saradc_pm_ops,
842 },
843 };
844
845 module_platform_driver(rockchip_saradc_driver);
846
847 MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
848 MODULE_DESCRIPTION("Rockchip SARADC driver");
849 MODULE_LICENSE("GPL v2");
850