1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ADC driver for the RICOH RN5T618 power management chip family
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2019 Andreas Kemnade
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/errno.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/mfd/rn5t618.h>
15*4882a593Smuzhiyun #include <linux/platform_device.h>
16*4882a593Smuzhiyun #include <linux/completion.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun #include <linux/iio/iio.h>
19*4882a593Smuzhiyun #include <linux/slab.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define RN5T618_ADC_CONVERSION_TIMEOUT (msecs_to_jiffies(500))
22*4882a593Smuzhiyun #define RN5T618_REFERENCE_VOLT 2500
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* mask for selecting channels for single conversion */
25*4882a593Smuzhiyun #define RN5T618_ADCCNT3_CHANNEL_MASK 0x7
26*4882a593Smuzhiyun /* average 4-time conversion mode */
27*4882a593Smuzhiyun #define RN5T618_ADCCNT3_AVG BIT(3)
28*4882a593Smuzhiyun /* set for starting a single conversion, gets cleared by hw when done */
29*4882a593Smuzhiyun #define RN5T618_ADCCNT3_GODONE BIT(4)
30*4882a593Smuzhiyun /* automatic conversion, period is in ADCCNT2, selected channels are
31*4882a593Smuzhiyun * in ADCCNT1
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun #define RN5T618_ADCCNT3_AUTO BIT(5)
34*4882a593Smuzhiyun #define RN5T618_ADCEND_IRQ BIT(0)
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun struct rn5t618_adc_data {
37*4882a593Smuzhiyun struct device *dev;
38*4882a593Smuzhiyun struct rn5t618 *rn5t618;
39*4882a593Smuzhiyun struct completion conv_completion;
40*4882a593Smuzhiyun int irq;
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun struct rn5t618_channel_ratios {
44*4882a593Smuzhiyun u16 numerator;
45*4882a593Smuzhiyun u16 denominator;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun enum rn5t618_channels {
49*4882a593Smuzhiyun LIMMON = 0,
50*4882a593Smuzhiyun VBAT,
51*4882a593Smuzhiyun VADP,
52*4882a593Smuzhiyun VUSB,
53*4882a593Smuzhiyun VSYS,
54*4882a593Smuzhiyun VTHM,
55*4882a593Smuzhiyun AIN1,
56*4882a593Smuzhiyun AIN0
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static const struct rn5t618_channel_ratios rn5t618_ratios[8] = {
60*4882a593Smuzhiyun [LIMMON] = {50, 32}, /* measured across 20mOhm, amplified by 32 */
61*4882a593Smuzhiyun [VBAT] = {2, 1},
62*4882a593Smuzhiyun [VADP] = {3, 1},
63*4882a593Smuzhiyun [VUSB] = {3, 1},
64*4882a593Smuzhiyun [VSYS] = {3, 1},
65*4882a593Smuzhiyun [VTHM] = {1, 1},
66*4882a593Smuzhiyun [AIN1] = {1, 1},
67*4882a593Smuzhiyun [AIN0] = {1, 1},
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
rn5t618_read_adc_reg(struct rn5t618 * rn5t618,int reg,u16 * val)70*4882a593Smuzhiyun static int rn5t618_read_adc_reg(struct rn5t618 *rn5t618, int reg, u16 *val)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun u8 data[2];
73*4882a593Smuzhiyun int ret;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun ret = regmap_bulk_read(rn5t618->regmap, reg, data, sizeof(data));
76*4882a593Smuzhiyun if (ret < 0)
77*4882a593Smuzhiyun return ret;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun *val = (data[0] << 4) | (data[1] & 0xF);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun return 0;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
rn5t618_adc_irq(int irq,void * data)84*4882a593Smuzhiyun static irqreturn_t rn5t618_adc_irq(int irq, void *data)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun struct rn5t618_adc_data *adc = data;
87*4882a593Smuzhiyun unsigned int r = 0;
88*4882a593Smuzhiyun int ret;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* clear low & high threshold irqs */
91*4882a593Smuzhiyun regmap_write(adc->rn5t618->regmap, RN5T618_IR_ADC1, 0);
92*4882a593Smuzhiyun regmap_write(adc->rn5t618->regmap, RN5T618_IR_ADC2, 0);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun ret = regmap_read(adc->rn5t618->regmap, RN5T618_IR_ADC3, &r);
95*4882a593Smuzhiyun if (ret < 0)
96*4882a593Smuzhiyun dev_err(adc->dev, "failed to read IRQ status: %d\n", ret);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun regmap_write(adc->rn5t618->regmap, RN5T618_IR_ADC3, 0);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun if (r & RN5T618_ADCEND_IRQ)
101*4882a593Smuzhiyun complete(&adc->conv_completion);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun return IRQ_HANDLED;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
rn5t618_adc_read(struct iio_dev * iio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long mask)106*4882a593Smuzhiyun static int rn5t618_adc_read(struct iio_dev *iio_dev,
107*4882a593Smuzhiyun const struct iio_chan_spec *chan,
108*4882a593Smuzhiyun int *val, int *val2, long mask)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun struct rn5t618_adc_data *adc = iio_priv(iio_dev);
111*4882a593Smuzhiyun u16 raw;
112*4882a593Smuzhiyun int ret;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun if (mask == IIO_CHAN_INFO_SCALE) {
115*4882a593Smuzhiyun *val = RN5T618_REFERENCE_VOLT *
116*4882a593Smuzhiyun rn5t618_ratios[chan->channel].numerator;
117*4882a593Smuzhiyun *val2 = rn5t618_ratios[chan->channel].denominator * 4095;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /* select channel */
123*4882a593Smuzhiyun ret = regmap_update_bits(adc->rn5t618->regmap, RN5T618_ADCCNT3,
124*4882a593Smuzhiyun RN5T618_ADCCNT3_CHANNEL_MASK,
125*4882a593Smuzhiyun chan->channel);
126*4882a593Smuzhiyun if (ret < 0)
127*4882a593Smuzhiyun return ret;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun ret = regmap_write(adc->rn5t618->regmap, RN5T618_EN_ADCIR3,
130*4882a593Smuzhiyun RN5T618_ADCEND_IRQ);
131*4882a593Smuzhiyun if (ret < 0)
132*4882a593Smuzhiyun return ret;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun ret = regmap_update_bits(adc->rn5t618->regmap, RN5T618_ADCCNT3,
135*4882a593Smuzhiyun RN5T618_ADCCNT3_AVG,
136*4882a593Smuzhiyun mask == IIO_CHAN_INFO_AVERAGE_RAW ?
137*4882a593Smuzhiyun RN5T618_ADCCNT3_AVG : 0);
138*4882a593Smuzhiyun if (ret < 0)
139*4882a593Smuzhiyun return ret;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun init_completion(&adc->conv_completion);
142*4882a593Smuzhiyun /* single conversion */
143*4882a593Smuzhiyun ret = regmap_update_bits(adc->rn5t618->regmap, RN5T618_ADCCNT3,
144*4882a593Smuzhiyun RN5T618_ADCCNT3_GODONE,
145*4882a593Smuzhiyun RN5T618_ADCCNT3_GODONE);
146*4882a593Smuzhiyun if (ret < 0)
147*4882a593Smuzhiyun return ret;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun ret = wait_for_completion_timeout(&adc->conv_completion,
150*4882a593Smuzhiyun RN5T618_ADC_CONVERSION_TIMEOUT);
151*4882a593Smuzhiyun if (ret == 0) {
152*4882a593Smuzhiyun dev_warn(adc->dev, "timeout waiting for adc result\n");
153*4882a593Smuzhiyun return -ETIMEDOUT;
154*4882a593Smuzhiyun }
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun ret = rn5t618_read_adc_reg(adc->rn5t618,
157*4882a593Smuzhiyun RN5T618_ILIMDATAH + 2 * chan->channel,
158*4882a593Smuzhiyun &raw);
159*4882a593Smuzhiyun if (ret < 0)
160*4882a593Smuzhiyun return ret;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun *val = raw;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun return IIO_VAL_INT;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun static const struct iio_info rn5t618_adc_iio_info = {
168*4882a593Smuzhiyun .read_raw = &rn5t618_adc_read,
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun #define RN5T618_ADC_CHANNEL(_channel, _type, _name) { \
172*4882a593Smuzhiyun .type = _type, \
173*4882a593Smuzhiyun .channel = _channel, \
174*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
175*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_AVERAGE_RAW) | \
176*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE), \
177*4882a593Smuzhiyun .datasheet_name = _name, \
178*4882a593Smuzhiyun .indexed = 1. \
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun static const struct iio_chan_spec rn5t618_adc_iio_channels[] = {
182*4882a593Smuzhiyun RN5T618_ADC_CHANNEL(LIMMON, IIO_CURRENT, "LIMMON"),
183*4882a593Smuzhiyun RN5T618_ADC_CHANNEL(VBAT, IIO_VOLTAGE, "VBAT"),
184*4882a593Smuzhiyun RN5T618_ADC_CHANNEL(VADP, IIO_VOLTAGE, "VADP"),
185*4882a593Smuzhiyun RN5T618_ADC_CHANNEL(VUSB, IIO_VOLTAGE, "VUSB"),
186*4882a593Smuzhiyun RN5T618_ADC_CHANNEL(VSYS, IIO_VOLTAGE, "VSYS"),
187*4882a593Smuzhiyun RN5T618_ADC_CHANNEL(VTHM, IIO_VOLTAGE, "VTHM"),
188*4882a593Smuzhiyun RN5T618_ADC_CHANNEL(AIN1, IIO_VOLTAGE, "AIN1"),
189*4882a593Smuzhiyun RN5T618_ADC_CHANNEL(AIN0, IIO_VOLTAGE, "AIN0")
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun
rn5t618_adc_probe(struct platform_device * pdev)192*4882a593Smuzhiyun static int rn5t618_adc_probe(struct platform_device *pdev)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun int ret;
195*4882a593Smuzhiyun struct iio_dev *iio_dev;
196*4882a593Smuzhiyun struct rn5t618_adc_data *adc;
197*4882a593Smuzhiyun struct rn5t618 *rn5t618 = dev_get_drvdata(pdev->dev.parent);
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun iio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
200*4882a593Smuzhiyun if (!iio_dev) {
201*4882a593Smuzhiyun dev_err(&pdev->dev, "failed allocating iio device\n");
202*4882a593Smuzhiyun return -ENOMEM;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun adc = iio_priv(iio_dev);
206*4882a593Smuzhiyun adc->dev = &pdev->dev;
207*4882a593Smuzhiyun adc->rn5t618 = rn5t618;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun if (rn5t618->irq_data)
210*4882a593Smuzhiyun adc->irq = regmap_irq_get_virq(rn5t618->irq_data,
211*4882a593Smuzhiyun RN5T618_IRQ_ADC);
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun if (adc->irq <= 0) {
214*4882a593Smuzhiyun dev_err(&pdev->dev, "get virq failed\n");
215*4882a593Smuzhiyun return -EINVAL;
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun init_completion(&adc->conv_completion);
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun iio_dev->name = dev_name(&pdev->dev);
221*4882a593Smuzhiyun iio_dev->info = &rn5t618_adc_iio_info;
222*4882a593Smuzhiyun iio_dev->modes = INDIO_DIRECT_MODE;
223*4882a593Smuzhiyun iio_dev->channels = rn5t618_adc_iio_channels;
224*4882a593Smuzhiyun iio_dev->num_channels = ARRAY_SIZE(rn5t618_adc_iio_channels);
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun /* stop any auto-conversion */
227*4882a593Smuzhiyun ret = regmap_write(rn5t618->regmap, RN5T618_ADCCNT3, 0);
228*4882a593Smuzhiyun if (ret < 0)
229*4882a593Smuzhiyun return ret;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun platform_set_drvdata(pdev, iio_dev);
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun ret = devm_request_threaded_irq(adc->dev, adc->irq, NULL,
234*4882a593Smuzhiyun rn5t618_adc_irq,
235*4882a593Smuzhiyun IRQF_ONESHOT, dev_name(adc->dev),
236*4882a593Smuzhiyun adc);
237*4882a593Smuzhiyun if (ret < 0) {
238*4882a593Smuzhiyun dev_err(adc->dev, "request irq %d failed: %d\n", adc->irq, ret);
239*4882a593Smuzhiyun return ret;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun return devm_iio_device_register(adc->dev, iio_dev);
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun static struct platform_driver rn5t618_adc_driver = {
246*4882a593Smuzhiyun .driver = {
247*4882a593Smuzhiyun .name = "rn5t618-adc",
248*4882a593Smuzhiyun },
249*4882a593Smuzhiyun .probe = rn5t618_adc_probe,
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun module_platform_driver(rn5t618_adc_driver);
253*4882a593Smuzhiyun MODULE_ALIAS("platform:rn5t618-adc");
254*4882a593Smuzhiyun MODULE_DESCRIPTION("RICOH RN5T618 ADC driver");
255*4882a593Smuzhiyun MODULE_LICENSE("GPL");
256