1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/bitops.h>
7*4882a593Smuzhiyun #include <linux/completion.h>
8*4882a593Smuzhiyun #include <linux/delay.h>
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun #include <linux/iio/iio.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/math64.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/of.h>
16*4882a593Smuzhiyun #include <linux/platform_device.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun #include <linux/log2.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <dt-bindings/iio/qcom,spmi-vadc.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include "qcom-vadc-common.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* VADC register and bit definitions */
26*4882a593Smuzhiyun #define VADC_REVISION2 0x1
27*4882a593Smuzhiyun #define VADC_REVISION2_SUPPORTED_VADC 1
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define VADC_PERPH_TYPE 0x4
30*4882a593Smuzhiyun #define VADC_PERPH_TYPE_ADC 8
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define VADC_PERPH_SUBTYPE 0x5
33*4882a593Smuzhiyun #define VADC_PERPH_SUBTYPE_VADC 1
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define VADC_STATUS1 0x8
36*4882a593Smuzhiyun #define VADC_STATUS1_OP_MODE 4
37*4882a593Smuzhiyun #define VADC_STATUS1_REQ_STS BIT(1)
38*4882a593Smuzhiyun #define VADC_STATUS1_EOC BIT(0)
39*4882a593Smuzhiyun #define VADC_STATUS1_REQ_STS_EOC_MASK 0x3
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define VADC_MODE_CTL 0x40
42*4882a593Smuzhiyun #define VADC_OP_MODE_SHIFT 3
43*4882a593Smuzhiyun #define VADC_OP_MODE_NORMAL 0
44*4882a593Smuzhiyun #define VADC_AMUX_TRIM_EN BIT(1)
45*4882a593Smuzhiyun #define VADC_ADC_TRIM_EN BIT(0)
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define VADC_EN_CTL1 0x46
48*4882a593Smuzhiyun #define VADC_EN_CTL1_SET BIT(7)
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define VADC_ADC_CH_SEL_CTL 0x48
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define VADC_ADC_DIG_PARAM 0x50
53*4882a593Smuzhiyun #define VADC_ADC_DIG_DEC_RATIO_SEL_SHIFT 2
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define VADC_HW_SETTLE_DELAY 0x51
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define VADC_CONV_REQ 0x52
58*4882a593Smuzhiyun #define VADC_CONV_REQ_SET BIT(7)
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define VADC_FAST_AVG_CTL 0x5a
61*4882a593Smuzhiyun #define VADC_FAST_AVG_EN 0x5b
62*4882a593Smuzhiyun #define VADC_FAST_AVG_EN_SET BIT(7)
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #define VADC_ACCESS 0xd0
65*4882a593Smuzhiyun #define VADC_ACCESS_DATA 0xa5
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #define VADC_PERH_RESET_CTL3 0xda
68*4882a593Smuzhiyun #define VADC_FOLLOW_WARM_RB BIT(2)
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #define VADC_DATA 0x60 /* 16 bits */
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #define VADC_CHAN_MIN VADC_USBIN
73*4882a593Smuzhiyun #define VADC_CHAN_MAX VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /**
76*4882a593Smuzhiyun * struct vadc_channel_prop - VADC channel property.
77*4882a593Smuzhiyun * @channel: channel number, refer to the channel list.
78*4882a593Smuzhiyun * @calibration: calibration type.
79*4882a593Smuzhiyun * @decimation: sampling rate supported for the channel.
80*4882a593Smuzhiyun * @prescale: channel scaling performed on the input signal.
81*4882a593Smuzhiyun * @hw_settle_time: the time between AMUX being configured and the
82*4882a593Smuzhiyun * start of conversion.
83*4882a593Smuzhiyun * @avg_samples: ability to provide single result from the ADC
84*4882a593Smuzhiyun * that is an average of multiple measurements.
85*4882a593Smuzhiyun * @scale_fn_type: Represents the scaling function to convert voltage
86*4882a593Smuzhiyun * physical units desired by the client for the channel.
87*4882a593Smuzhiyun */
88*4882a593Smuzhiyun struct vadc_channel_prop {
89*4882a593Smuzhiyun unsigned int channel;
90*4882a593Smuzhiyun enum vadc_calibration calibration;
91*4882a593Smuzhiyun unsigned int decimation;
92*4882a593Smuzhiyun unsigned int prescale;
93*4882a593Smuzhiyun unsigned int hw_settle_time;
94*4882a593Smuzhiyun unsigned int avg_samples;
95*4882a593Smuzhiyun enum vadc_scale_fn_type scale_fn_type;
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /**
99*4882a593Smuzhiyun * struct vadc_priv - VADC private structure.
100*4882a593Smuzhiyun * @regmap: pointer to struct regmap.
101*4882a593Smuzhiyun * @dev: pointer to struct device.
102*4882a593Smuzhiyun * @base: base address for the ADC peripheral.
103*4882a593Smuzhiyun * @nchannels: number of VADC channels.
104*4882a593Smuzhiyun * @chan_props: array of VADC channel properties.
105*4882a593Smuzhiyun * @iio_chans: array of IIO channels specification.
106*4882a593Smuzhiyun * @are_ref_measured: are reference points measured.
107*4882a593Smuzhiyun * @poll_eoc: use polling instead of interrupt.
108*4882a593Smuzhiyun * @complete: VADC result notification after interrupt is received.
109*4882a593Smuzhiyun * @graph: store parameters for calibration.
110*4882a593Smuzhiyun * @lock: ADC lock for access to the peripheral.
111*4882a593Smuzhiyun */
112*4882a593Smuzhiyun struct vadc_priv {
113*4882a593Smuzhiyun struct regmap *regmap;
114*4882a593Smuzhiyun struct device *dev;
115*4882a593Smuzhiyun u16 base;
116*4882a593Smuzhiyun unsigned int nchannels;
117*4882a593Smuzhiyun struct vadc_channel_prop *chan_props;
118*4882a593Smuzhiyun struct iio_chan_spec *iio_chans;
119*4882a593Smuzhiyun bool are_ref_measured;
120*4882a593Smuzhiyun bool poll_eoc;
121*4882a593Smuzhiyun struct completion complete;
122*4882a593Smuzhiyun struct vadc_linear_graph graph[2];
123*4882a593Smuzhiyun struct mutex lock;
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun static const struct vadc_prescale_ratio vadc_prescale_ratios[] = {
127*4882a593Smuzhiyun {.num = 1, .den = 1},
128*4882a593Smuzhiyun {.num = 1, .den = 3},
129*4882a593Smuzhiyun {.num = 1, .den = 4},
130*4882a593Smuzhiyun {.num = 1, .den = 6},
131*4882a593Smuzhiyun {.num = 1, .den = 20},
132*4882a593Smuzhiyun {.num = 1, .den = 8},
133*4882a593Smuzhiyun {.num = 10, .den = 81},
134*4882a593Smuzhiyun {.num = 1, .den = 10}
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
vadc_read(struct vadc_priv * vadc,u16 offset,u8 * data)137*4882a593Smuzhiyun static int vadc_read(struct vadc_priv *vadc, u16 offset, u8 *data)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun return regmap_bulk_read(vadc->regmap, vadc->base + offset, data, 1);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
vadc_write(struct vadc_priv * vadc,u16 offset,u8 data)142*4882a593Smuzhiyun static int vadc_write(struct vadc_priv *vadc, u16 offset, u8 data)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun return regmap_write(vadc->regmap, vadc->base + offset, data);
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
vadc_reset(struct vadc_priv * vadc)147*4882a593Smuzhiyun static int vadc_reset(struct vadc_priv *vadc)
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun u8 data;
150*4882a593Smuzhiyun int ret;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun ret = vadc_write(vadc, VADC_ACCESS, VADC_ACCESS_DATA);
153*4882a593Smuzhiyun if (ret)
154*4882a593Smuzhiyun return ret;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun ret = vadc_read(vadc, VADC_PERH_RESET_CTL3, &data);
157*4882a593Smuzhiyun if (ret)
158*4882a593Smuzhiyun return ret;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun ret = vadc_write(vadc, VADC_ACCESS, VADC_ACCESS_DATA);
161*4882a593Smuzhiyun if (ret)
162*4882a593Smuzhiyun return ret;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun data |= VADC_FOLLOW_WARM_RB;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun return vadc_write(vadc, VADC_PERH_RESET_CTL3, data);
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
vadc_set_state(struct vadc_priv * vadc,bool state)169*4882a593Smuzhiyun static int vadc_set_state(struct vadc_priv *vadc, bool state)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun return vadc_write(vadc, VADC_EN_CTL1, state ? VADC_EN_CTL1_SET : 0);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
vadc_show_status(struct vadc_priv * vadc)174*4882a593Smuzhiyun static void vadc_show_status(struct vadc_priv *vadc)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun u8 mode, sta1, chan, dig, en, req;
177*4882a593Smuzhiyun int ret;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun ret = vadc_read(vadc, VADC_MODE_CTL, &mode);
180*4882a593Smuzhiyun if (ret)
181*4882a593Smuzhiyun return;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun ret = vadc_read(vadc, VADC_ADC_DIG_PARAM, &dig);
184*4882a593Smuzhiyun if (ret)
185*4882a593Smuzhiyun return;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun ret = vadc_read(vadc, VADC_ADC_CH_SEL_CTL, &chan);
188*4882a593Smuzhiyun if (ret)
189*4882a593Smuzhiyun return;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun ret = vadc_read(vadc, VADC_CONV_REQ, &req);
192*4882a593Smuzhiyun if (ret)
193*4882a593Smuzhiyun return;
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun ret = vadc_read(vadc, VADC_STATUS1, &sta1);
196*4882a593Smuzhiyun if (ret)
197*4882a593Smuzhiyun return;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun ret = vadc_read(vadc, VADC_EN_CTL1, &en);
200*4882a593Smuzhiyun if (ret)
201*4882a593Smuzhiyun return;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun dev_err(vadc->dev,
204*4882a593Smuzhiyun "mode:%02x en:%02x chan:%02x dig:%02x req:%02x sta1:%02x\n",
205*4882a593Smuzhiyun mode, en, chan, dig, req, sta1);
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
vadc_configure(struct vadc_priv * vadc,struct vadc_channel_prop * prop)208*4882a593Smuzhiyun static int vadc_configure(struct vadc_priv *vadc,
209*4882a593Smuzhiyun struct vadc_channel_prop *prop)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun u8 decimation, mode_ctrl;
212*4882a593Smuzhiyun int ret;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun /* Mode selection */
215*4882a593Smuzhiyun mode_ctrl = (VADC_OP_MODE_NORMAL << VADC_OP_MODE_SHIFT) |
216*4882a593Smuzhiyun VADC_ADC_TRIM_EN | VADC_AMUX_TRIM_EN;
217*4882a593Smuzhiyun ret = vadc_write(vadc, VADC_MODE_CTL, mode_ctrl);
218*4882a593Smuzhiyun if (ret)
219*4882a593Smuzhiyun return ret;
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun /* Channel selection */
222*4882a593Smuzhiyun ret = vadc_write(vadc, VADC_ADC_CH_SEL_CTL, prop->channel);
223*4882a593Smuzhiyun if (ret)
224*4882a593Smuzhiyun return ret;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun /* Digital parameter setup */
227*4882a593Smuzhiyun decimation = prop->decimation << VADC_ADC_DIG_DEC_RATIO_SEL_SHIFT;
228*4882a593Smuzhiyun ret = vadc_write(vadc, VADC_ADC_DIG_PARAM, decimation);
229*4882a593Smuzhiyun if (ret)
230*4882a593Smuzhiyun return ret;
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun /* HW settle time delay */
233*4882a593Smuzhiyun ret = vadc_write(vadc, VADC_HW_SETTLE_DELAY, prop->hw_settle_time);
234*4882a593Smuzhiyun if (ret)
235*4882a593Smuzhiyun return ret;
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun ret = vadc_write(vadc, VADC_FAST_AVG_CTL, prop->avg_samples);
238*4882a593Smuzhiyun if (ret)
239*4882a593Smuzhiyun return ret;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun if (prop->avg_samples)
242*4882a593Smuzhiyun ret = vadc_write(vadc, VADC_FAST_AVG_EN, VADC_FAST_AVG_EN_SET);
243*4882a593Smuzhiyun else
244*4882a593Smuzhiyun ret = vadc_write(vadc, VADC_FAST_AVG_EN, 0);
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun return ret;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
vadc_poll_wait_eoc(struct vadc_priv * vadc,unsigned int interval_us)249*4882a593Smuzhiyun static int vadc_poll_wait_eoc(struct vadc_priv *vadc, unsigned int interval_us)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun unsigned int count, retry;
252*4882a593Smuzhiyun u8 sta1;
253*4882a593Smuzhiyun int ret;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun retry = interval_us / VADC_CONV_TIME_MIN_US;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun for (count = 0; count < retry; count++) {
258*4882a593Smuzhiyun ret = vadc_read(vadc, VADC_STATUS1, &sta1);
259*4882a593Smuzhiyun if (ret)
260*4882a593Smuzhiyun return ret;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun sta1 &= VADC_STATUS1_REQ_STS_EOC_MASK;
263*4882a593Smuzhiyun if (sta1 == VADC_STATUS1_EOC)
264*4882a593Smuzhiyun return 0;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun usleep_range(VADC_CONV_TIME_MIN_US, VADC_CONV_TIME_MAX_US);
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun vadc_show_status(vadc);
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun return -ETIMEDOUT;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
vadc_read_result(struct vadc_priv * vadc,u16 * data)274*4882a593Smuzhiyun static int vadc_read_result(struct vadc_priv *vadc, u16 *data)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun int ret;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun ret = regmap_bulk_read(vadc->regmap, vadc->base + VADC_DATA, data, 2);
279*4882a593Smuzhiyun if (ret)
280*4882a593Smuzhiyun return ret;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun *data = clamp_t(u16, *data, VADC_MIN_ADC_CODE, VADC_MAX_ADC_CODE);
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun return 0;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun
vadc_get_channel(struct vadc_priv * vadc,unsigned int num)287*4882a593Smuzhiyun static struct vadc_channel_prop *vadc_get_channel(struct vadc_priv *vadc,
288*4882a593Smuzhiyun unsigned int num)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun unsigned int i;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun for (i = 0; i < vadc->nchannels; i++)
293*4882a593Smuzhiyun if (vadc->chan_props[i].channel == num)
294*4882a593Smuzhiyun return &vadc->chan_props[i];
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun dev_dbg(vadc->dev, "no such channel %02x\n", num);
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun return NULL;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
vadc_do_conversion(struct vadc_priv * vadc,struct vadc_channel_prop * prop,u16 * data)301*4882a593Smuzhiyun static int vadc_do_conversion(struct vadc_priv *vadc,
302*4882a593Smuzhiyun struct vadc_channel_prop *prop, u16 *data)
303*4882a593Smuzhiyun {
304*4882a593Smuzhiyun unsigned int timeout;
305*4882a593Smuzhiyun int ret;
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun mutex_lock(&vadc->lock);
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun ret = vadc_configure(vadc, prop);
310*4882a593Smuzhiyun if (ret)
311*4882a593Smuzhiyun goto unlock;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun if (!vadc->poll_eoc)
314*4882a593Smuzhiyun reinit_completion(&vadc->complete);
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun ret = vadc_set_state(vadc, true);
317*4882a593Smuzhiyun if (ret)
318*4882a593Smuzhiyun goto unlock;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun ret = vadc_write(vadc, VADC_CONV_REQ, VADC_CONV_REQ_SET);
321*4882a593Smuzhiyun if (ret)
322*4882a593Smuzhiyun goto err_disable;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun timeout = BIT(prop->avg_samples) * VADC_CONV_TIME_MIN_US * 2;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun if (vadc->poll_eoc) {
327*4882a593Smuzhiyun ret = vadc_poll_wait_eoc(vadc, timeout);
328*4882a593Smuzhiyun } else {
329*4882a593Smuzhiyun ret = wait_for_completion_timeout(&vadc->complete, timeout);
330*4882a593Smuzhiyun if (!ret) {
331*4882a593Smuzhiyun ret = -ETIMEDOUT;
332*4882a593Smuzhiyun goto err_disable;
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun /* Double check conversion status */
336*4882a593Smuzhiyun ret = vadc_poll_wait_eoc(vadc, VADC_CONV_TIME_MIN_US);
337*4882a593Smuzhiyun if (ret)
338*4882a593Smuzhiyun goto err_disable;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun ret = vadc_read_result(vadc, data);
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun err_disable:
344*4882a593Smuzhiyun vadc_set_state(vadc, false);
345*4882a593Smuzhiyun if (ret)
346*4882a593Smuzhiyun dev_err(vadc->dev, "conversion failed\n");
347*4882a593Smuzhiyun unlock:
348*4882a593Smuzhiyun mutex_unlock(&vadc->lock);
349*4882a593Smuzhiyun return ret;
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun
vadc_measure_ref_points(struct vadc_priv * vadc)352*4882a593Smuzhiyun static int vadc_measure_ref_points(struct vadc_priv *vadc)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun struct vadc_channel_prop *prop;
355*4882a593Smuzhiyun u16 read_1, read_2;
356*4882a593Smuzhiyun int ret;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun vadc->graph[VADC_CALIB_RATIOMETRIC].dx = VADC_RATIOMETRIC_RANGE;
359*4882a593Smuzhiyun vadc->graph[VADC_CALIB_ABSOLUTE].dx = VADC_ABSOLUTE_RANGE_UV;
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun prop = vadc_get_channel(vadc, VADC_REF_1250MV);
362*4882a593Smuzhiyun ret = vadc_do_conversion(vadc, prop, &read_1);
363*4882a593Smuzhiyun if (ret)
364*4882a593Smuzhiyun goto err;
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun /* Try with buffered 625mV channel first */
367*4882a593Smuzhiyun prop = vadc_get_channel(vadc, VADC_SPARE1);
368*4882a593Smuzhiyun if (!prop)
369*4882a593Smuzhiyun prop = vadc_get_channel(vadc, VADC_REF_625MV);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun ret = vadc_do_conversion(vadc, prop, &read_2);
372*4882a593Smuzhiyun if (ret)
373*4882a593Smuzhiyun goto err;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun if (read_1 == read_2) {
376*4882a593Smuzhiyun ret = -EINVAL;
377*4882a593Smuzhiyun goto err;
378*4882a593Smuzhiyun }
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun vadc->graph[VADC_CALIB_ABSOLUTE].dy = read_1 - read_2;
381*4882a593Smuzhiyun vadc->graph[VADC_CALIB_ABSOLUTE].gnd = read_2;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun /* Ratiometric calibration */
384*4882a593Smuzhiyun prop = vadc_get_channel(vadc, VADC_VDD_VADC);
385*4882a593Smuzhiyun ret = vadc_do_conversion(vadc, prop, &read_1);
386*4882a593Smuzhiyun if (ret)
387*4882a593Smuzhiyun goto err;
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun prop = vadc_get_channel(vadc, VADC_GND_REF);
390*4882a593Smuzhiyun ret = vadc_do_conversion(vadc, prop, &read_2);
391*4882a593Smuzhiyun if (ret)
392*4882a593Smuzhiyun goto err;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun if (read_1 == read_2) {
395*4882a593Smuzhiyun ret = -EINVAL;
396*4882a593Smuzhiyun goto err;
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun vadc->graph[VADC_CALIB_RATIOMETRIC].dy = read_1 - read_2;
400*4882a593Smuzhiyun vadc->graph[VADC_CALIB_RATIOMETRIC].gnd = read_2;
401*4882a593Smuzhiyun err:
402*4882a593Smuzhiyun if (ret)
403*4882a593Smuzhiyun dev_err(vadc->dev, "measure reference points failed\n");
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun return ret;
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun
vadc_prescaling_from_dt(u32 num,u32 den)408*4882a593Smuzhiyun static int vadc_prescaling_from_dt(u32 num, u32 den)
409*4882a593Smuzhiyun {
410*4882a593Smuzhiyun unsigned int pre;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun for (pre = 0; pre < ARRAY_SIZE(vadc_prescale_ratios); pre++)
413*4882a593Smuzhiyun if (vadc_prescale_ratios[pre].num == num &&
414*4882a593Smuzhiyun vadc_prescale_ratios[pre].den == den)
415*4882a593Smuzhiyun break;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun if (pre == ARRAY_SIZE(vadc_prescale_ratios))
418*4882a593Smuzhiyun return -EINVAL;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun return pre;
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun
vadc_hw_settle_time_from_dt(u32 value)423*4882a593Smuzhiyun static int vadc_hw_settle_time_from_dt(u32 value)
424*4882a593Smuzhiyun {
425*4882a593Smuzhiyun if ((value <= 1000 && value % 100) || (value > 1000 && value % 2000))
426*4882a593Smuzhiyun return -EINVAL;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun if (value <= 1000)
429*4882a593Smuzhiyun value /= 100;
430*4882a593Smuzhiyun else
431*4882a593Smuzhiyun value = value / 2000 + 10;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun return value;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
vadc_avg_samples_from_dt(u32 value)436*4882a593Smuzhiyun static int vadc_avg_samples_from_dt(u32 value)
437*4882a593Smuzhiyun {
438*4882a593Smuzhiyun if (!is_power_of_2(value) || value > VADC_AVG_SAMPLES_MAX)
439*4882a593Smuzhiyun return -EINVAL;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun return __ffs64(value);
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun
vadc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)444*4882a593Smuzhiyun static int vadc_read_raw(struct iio_dev *indio_dev,
445*4882a593Smuzhiyun struct iio_chan_spec const *chan, int *val, int *val2,
446*4882a593Smuzhiyun long mask)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun struct vadc_priv *vadc = iio_priv(indio_dev);
449*4882a593Smuzhiyun struct vadc_channel_prop *prop;
450*4882a593Smuzhiyun u16 adc_code;
451*4882a593Smuzhiyun int ret;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun switch (mask) {
454*4882a593Smuzhiyun case IIO_CHAN_INFO_PROCESSED:
455*4882a593Smuzhiyun prop = &vadc->chan_props[chan->address];
456*4882a593Smuzhiyun ret = vadc_do_conversion(vadc, prop, &adc_code);
457*4882a593Smuzhiyun if (ret)
458*4882a593Smuzhiyun break;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun ret = qcom_vadc_scale(prop->scale_fn_type,
461*4882a593Smuzhiyun &vadc->graph[prop->calibration],
462*4882a593Smuzhiyun &vadc_prescale_ratios[prop->prescale],
463*4882a593Smuzhiyun (prop->calibration == VADC_CALIB_ABSOLUTE),
464*4882a593Smuzhiyun adc_code, val);
465*4882a593Smuzhiyun if (ret)
466*4882a593Smuzhiyun break;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun return IIO_VAL_INT;
469*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
470*4882a593Smuzhiyun prop = &vadc->chan_props[chan->address];
471*4882a593Smuzhiyun ret = vadc_do_conversion(vadc, prop, &adc_code);
472*4882a593Smuzhiyun if (ret)
473*4882a593Smuzhiyun break;
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun *val = (int)adc_code;
476*4882a593Smuzhiyun return IIO_VAL_INT;
477*4882a593Smuzhiyun default:
478*4882a593Smuzhiyun ret = -EINVAL;
479*4882a593Smuzhiyun break;
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun return ret;
483*4882a593Smuzhiyun }
484*4882a593Smuzhiyun
vadc_of_xlate(struct iio_dev * indio_dev,const struct of_phandle_args * iiospec)485*4882a593Smuzhiyun static int vadc_of_xlate(struct iio_dev *indio_dev,
486*4882a593Smuzhiyun const struct of_phandle_args *iiospec)
487*4882a593Smuzhiyun {
488*4882a593Smuzhiyun struct vadc_priv *vadc = iio_priv(indio_dev);
489*4882a593Smuzhiyun unsigned int i;
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun for (i = 0; i < vadc->nchannels; i++)
492*4882a593Smuzhiyun if (vadc->iio_chans[i].channel == iiospec->args[0])
493*4882a593Smuzhiyun return i;
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun return -EINVAL;
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun static const struct iio_info vadc_info = {
499*4882a593Smuzhiyun .read_raw = vadc_read_raw,
500*4882a593Smuzhiyun .of_xlate = vadc_of_xlate,
501*4882a593Smuzhiyun };
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun struct vadc_channels {
504*4882a593Smuzhiyun const char *datasheet_name;
505*4882a593Smuzhiyun unsigned int prescale_index;
506*4882a593Smuzhiyun enum iio_chan_type type;
507*4882a593Smuzhiyun long info_mask;
508*4882a593Smuzhiyun enum vadc_scale_fn_type scale_fn_type;
509*4882a593Smuzhiyun };
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun #define VADC_CHAN(_dname, _type, _mask, _pre, _scale) \
512*4882a593Smuzhiyun [VADC_##_dname] = { \
513*4882a593Smuzhiyun .datasheet_name = __stringify(_dname), \
514*4882a593Smuzhiyun .prescale_index = _pre, \
515*4882a593Smuzhiyun .type = _type, \
516*4882a593Smuzhiyun .info_mask = _mask, \
517*4882a593Smuzhiyun .scale_fn_type = _scale \
518*4882a593Smuzhiyun }, \
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun #define VADC_NO_CHAN(_dname, _type, _mask, _pre) \
521*4882a593Smuzhiyun [VADC_##_dname] = { \
522*4882a593Smuzhiyun .datasheet_name = __stringify(_dname), \
523*4882a593Smuzhiyun .prescale_index = _pre, \
524*4882a593Smuzhiyun .type = _type, \
525*4882a593Smuzhiyun .info_mask = _mask \
526*4882a593Smuzhiyun },
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun #define VADC_CHAN_TEMP(_dname, _pre, _scale) \
529*4882a593Smuzhiyun VADC_CHAN(_dname, IIO_TEMP, \
530*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_PROCESSED), \
531*4882a593Smuzhiyun _pre, _scale) \
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun #define VADC_CHAN_VOLT(_dname, _pre, _scale) \
534*4882a593Smuzhiyun VADC_CHAN(_dname, IIO_VOLTAGE, \
535*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_PROCESSED),\
536*4882a593Smuzhiyun _pre, _scale) \
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun #define VADC_CHAN_NO_SCALE(_dname, _pre) \
539*4882a593Smuzhiyun VADC_NO_CHAN(_dname, IIO_VOLTAGE, \
540*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_RAW), \
541*4882a593Smuzhiyun _pre) \
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun /*
544*4882a593Smuzhiyun * The array represents all possible ADC channels found in the supported PMICs.
545*4882a593Smuzhiyun * Every index in the array is equal to the channel number per datasheet. The
546*4882a593Smuzhiyun * gaps in the array should be treated as reserved channels.
547*4882a593Smuzhiyun */
548*4882a593Smuzhiyun static const struct vadc_channels vadc_chans[] = {
549*4882a593Smuzhiyun VADC_CHAN_VOLT(USBIN, 4, SCALE_DEFAULT)
550*4882a593Smuzhiyun VADC_CHAN_VOLT(DCIN, 4, SCALE_DEFAULT)
551*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(VCHG_SNS, 3)
552*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(SPARE1_03, 1)
553*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(USB_ID_MV, 1)
554*4882a593Smuzhiyun VADC_CHAN_VOLT(VCOIN, 1, SCALE_DEFAULT)
555*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(VBAT_SNS, 1)
556*4882a593Smuzhiyun VADC_CHAN_VOLT(VSYS, 1, SCALE_DEFAULT)
557*4882a593Smuzhiyun VADC_CHAN_TEMP(DIE_TEMP, 0, SCALE_PMIC_THERM)
558*4882a593Smuzhiyun VADC_CHAN_VOLT(REF_625MV, 0, SCALE_DEFAULT)
559*4882a593Smuzhiyun VADC_CHAN_VOLT(REF_1250MV, 0, SCALE_DEFAULT)
560*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(CHG_TEMP, 0)
561*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(SPARE1, 0)
562*4882a593Smuzhiyun VADC_CHAN_TEMP(SPARE2, 0, SCALE_PMI_CHG_TEMP)
563*4882a593Smuzhiyun VADC_CHAN_VOLT(GND_REF, 0, SCALE_DEFAULT)
564*4882a593Smuzhiyun VADC_CHAN_VOLT(VDD_VADC, 0, SCALE_DEFAULT)
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX1_1_1, 0)
567*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX2_1_1, 0)
568*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX3_1_1, 0)
569*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX4_1_1, 0)
570*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX5_1_1, 0)
571*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX6_1_1, 0)
572*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX7_1_1, 0)
573*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX8_1_1, 0)
574*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX9_1_1, 0)
575*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX10_1_1, 0)
576*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX11_1_1, 0)
577*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX12_1_1, 0)
578*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX13_1_1, 0)
579*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX14_1_1, 0)
580*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX15_1_1, 0)
581*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX16_1_1, 0)
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX1_1_3, 1)
584*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX2_1_3, 1)
585*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX3_1_3, 1)
586*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX4_1_3, 1)
587*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX5_1_3, 1)
588*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX6_1_3, 1)
589*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX7_1_3, 1)
590*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX8_1_3, 1)
591*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX9_1_3, 1)
592*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX10_1_3, 1)
593*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX11_1_3, 1)
594*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX12_1_3, 1)
595*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX13_1_3, 1)
596*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX14_1_3, 1)
597*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX15_1_3, 1)
598*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(P_MUX16_1_3, 1)
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX1_BAT_THERM, 0)
601*4882a593Smuzhiyun VADC_CHAN_VOLT(LR_MUX2_BAT_ID, 0, SCALE_DEFAULT)
602*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX3_XO_THERM, 0)
603*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX4_AMUX_THM1, 0)
604*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX5_AMUX_THM2, 0)
605*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX6_AMUX_THM3, 0)
606*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX7_HW_ID, 0)
607*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX8_AMUX_THM4, 0)
608*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX9_AMUX_THM5, 0)
609*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX10_USB_ID, 0)
610*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(AMUX_PU1, 0)
611*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(AMUX_PU2, 0)
612*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX3_BUF_XO_THERM, 0)
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX1_PU1_BAT_THERM, 0)
615*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX2_PU1_BAT_ID, 0)
616*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX3_PU1_XO_THERM, 0)
617*4882a593Smuzhiyun VADC_CHAN_TEMP(LR_MUX4_PU1_AMUX_THM1, 0, SCALE_THERM_100K_PULLUP)
618*4882a593Smuzhiyun VADC_CHAN_TEMP(LR_MUX5_PU1_AMUX_THM2, 0, SCALE_THERM_100K_PULLUP)
619*4882a593Smuzhiyun VADC_CHAN_TEMP(LR_MUX6_PU1_AMUX_THM3, 0, SCALE_THERM_100K_PULLUP)
620*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX7_PU1_AMUX_HW_ID, 0)
621*4882a593Smuzhiyun VADC_CHAN_TEMP(LR_MUX8_PU1_AMUX_THM4, 0, SCALE_THERM_100K_PULLUP)
622*4882a593Smuzhiyun VADC_CHAN_TEMP(LR_MUX9_PU1_AMUX_THM5, 0, SCALE_THERM_100K_PULLUP)
623*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX10_PU1_AMUX_USB_ID, 0)
624*4882a593Smuzhiyun VADC_CHAN_TEMP(LR_MUX3_BUF_PU1_XO_THERM, 0, SCALE_XOTHERM)
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX1_PU2_BAT_THERM, 0)
627*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX2_PU2_BAT_ID, 0)
628*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX3_PU2_XO_THERM, 0)
629*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX4_PU2_AMUX_THM1, 0)
630*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX5_PU2_AMUX_THM2, 0)
631*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX6_PU2_AMUX_THM3, 0)
632*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX7_PU2_AMUX_HW_ID, 0)
633*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX8_PU2_AMUX_THM4, 0)
634*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX9_PU2_AMUX_THM5, 0)
635*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX10_PU2_AMUX_USB_ID, 0)
636*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX3_BUF_PU2_XO_THERM, 0)
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX1_PU1_PU2_BAT_THERM, 0)
639*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX2_PU1_PU2_BAT_ID, 0)
640*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX3_PU1_PU2_XO_THERM, 0)
641*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX4_PU1_PU2_AMUX_THM1, 0)
642*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX5_PU1_PU2_AMUX_THM2, 0)
643*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX6_PU1_PU2_AMUX_THM3, 0)
644*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX7_PU1_PU2_AMUX_HW_ID, 0)
645*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX8_PU1_PU2_AMUX_THM4, 0)
646*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX9_PU1_PU2_AMUX_THM5, 0)
647*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX10_PU1_PU2_AMUX_USB_ID, 0)
648*4882a593Smuzhiyun VADC_CHAN_NO_SCALE(LR_MUX3_BUF_PU1_PU2_XO_THERM, 0)
649*4882a593Smuzhiyun };
650*4882a593Smuzhiyun
vadc_get_dt_channel_data(struct device * dev,struct vadc_channel_prop * prop,struct device_node * node)651*4882a593Smuzhiyun static int vadc_get_dt_channel_data(struct device *dev,
652*4882a593Smuzhiyun struct vadc_channel_prop *prop,
653*4882a593Smuzhiyun struct device_node *node)
654*4882a593Smuzhiyun {
655*4882a593Smuzhiyun const char *name = node->name;
656*4882a593Smuzhiyun u32 chan, value, varr[2];
657*4882a593Smuzhiyun int ret;
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun ret = of_property_read_u32(node, "reg", &chan);
660*4882a593Smuzhiyun if (ret) {
661*4882a593Smuzhiyun dev_err(dev, "invalid channel number %s\n", name);
662*4882a593Smuzhiyun return ret;
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun if (chan > VADC_CHAN_MAX || chan < VADC_CHAN_MIN) {
666*4882a593Smuzhiyun dev_err(dev, "%s invalid channel number %d\n", name, chan);
667*4882a593Smuzhiyun return -EINVAL;
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun /* the channel has DT description */
671*4882a593Smuzhiyun prop->channel = chan;
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun ret = of_property_read_u32(node, "qcom,decimation", &value);
674*4882a593Smuzhiyun if (!ret) {
675*4882a593Smuzhiyun ret = qcom_vadc_decimation_from_dt(value);
676*4882a593Smuzhiyun if (ret < 0) {
677*4882a593Smuzhiyun dev_err(dev, "%02x invalid decimation %d\n",
678*4882a593Smuzhiyun chan, value);
679*4882a593Smuzhiyun return ret;
680*4882a593Smuzhiyun }
681*4882a593Smuzhiyun prop->decimation = ret;
682*4882a593Smuzhiyun } else {
683*4882a593Smuzhiyun prop->decimation = VADC_DEF_DECIMATION;
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun
686*4882a593Smuzhiyun ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2);
687*4882a593Smuzhiyun if (!ret) {
688*4882a593Smuzhiyun ret = vadc_prescaling_from_dt(varr[0], varr[1]);
689*4882a593Smuzhiyun if (ret < 0) {
690*4882a593Smuzhiyun dev_err(dev, "%02x invalid pre-scaling <%d %d>\n",
691*4882a593Smuzhiyun chan, varr[0], varr[1]);
692*4882a593Smuzhiyun return ret;
693*4882a593Smuzhiyun }
694*4882a593Smuzhiyun prop->prescale = ret;
695*4882a593Smuzhiyun } else {
696*4882a593Smuzhiyun prop->prescale = vadc_chans[prop->channel].prescale_index;
697*4882a593Smuzhiyun }
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun ret = of_property_read_u32(node, "qcom,hw-settle-time", &value);
700*4882a593Smuzhiyun if (!ret) {
701*4882a593Smuzhiyun ret = vadc_hw_settle_time_from_dt(value);
702*4882a593Smuzhiyun if (ret < 0) {
703*4882a593Smuzhiyun dev_err(dev, "%02x invalid hw-settle-time %d us\n",
704*4882a593Smuzhiyun chan, value);
705*4882a593Smuzhiyun return ret;
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun prop->hw_settle_time = ret;
708*4882a593Smuzhiyun } else {
709*4882a593Smuzhiyun prop->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
710*4882a593Smuzhiyun }
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun ret = of_property_read_u32(node, "qcom,avg-samples", &value);
713*4882a593Smuzhiyun if (!ret) {
714*4882a593Smuzhiyun ret = vadc_avg_samples_from_dt(value);
715*4882a593Smuzhiyun if (ret < 0) {
716*4882a593Smuzhiyun dev_err(dev, "%02x invalid avg-samples %d\n",
717*4882a593Smuzhiyun chan, value);
718*4882a593Smuzhiyun return ret;
719*4882a593Smuzhiyun }
720*4882a593Smuzhiyun prop->avg_samples = ret;
721*4882a593Smuzhiyun } else {
722*4882a593Smuzhiyun prop->avg_samples = VADC_DEF_AVG_SAMPLES;
723*4882a593Smuzhiyun }
724*4882a593Smuzhiyun
725*4882a593Smuzhiyun if (of_property_read_bool(node, "qcom,ratiometric"))
726*4882a593Smuzhiyun prop->calibration = VADC_CALIB_RATIOMETRIC;
727*4882a593Smuzhiyun else
728*4882a593Smuzhiyun prop->calibration = VADC_CALIB_ABSOLUTE;
729*4882a593Smuzhiyun
730*4882a593Smuzhiyun dev_dbg(dev, "%02x name %s\n", chan, name);
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun return 0;
733*4882a593Smuzhiyun }
734*4882a593Smuzhiyun
vadc_get_dt_data(struct vadc_priv * vadc,struct device_node * node)735*4882a593Smuzhiyun static int vadc_get_dt_data(struct vadc_priv *vadc, struct device_node *node)
736*4882a593Smuzhiyun {
737*4882a593Smuzhiyun const struct vadc_channels *vadc_chan;
738*4882a593Smuzhiyun struct iio_chan_spec *iio_chan;
739*4882a593Smuzhiyun struct vadc_channel_prop prop;
740*4882a593Smuzhiyun struct device_node *child;
741*4882a593Smuzhiyun unsigned int index = 0;
742*4882a593Smuzhiyun int ret;
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun vadc->nchannels = of_get_available_child_count(node);
745*4882a593Smuzhiyun if (!vadc->nchannels)
746*4882a593Smuzhiyun return -EINVAL;
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun vadc->iio_chans = devm_kcalloc(vadc->dev, vadc->nchannels,
749*4882a593Smuzhiyun sizeof(*vadc->iio_chans), GFP_KERNEL);
750*4882a593Smuzhiyun if (!vadc->iio_chans)
751*4882a593Smuzhiyun return -ENOMEM;
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun vadc->chan_props = devm_kcalloc(vadc->dev, vadc->nchannels,
754*4882a593Smuzhiyun sizeof(*vadc->chan_props), GFP_KERNEL);
755*4882a593Smuzhiyun if (!vadc->chan_props)
756*4882a593Smuzhiyun return -ENOMEM;
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun iio_chan = vadc->iio_chans;
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun for_each_available_child_of_node(node, child) {
761*4882a593Smuzhiyun ret = vadc_get_dt_channel_data(vadc->dev, &prop, child);
762*4882a593Smuzhiyun if (ret) {
763*4882a593Smuzhiyun of_node_put(child);
764*4882a593Smuzhiyun return ret;
765*4882a593Smuzhiyun }
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun prop.scale_fn_type = vadc_chans[prop.channel].scale_fn_type;
768*4882a593Smuzhiyun vadc->chan_props[index] = prop;
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun vadc_chan = &vadc_chans[prop.channel];
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun iio_chan->channel = prop.channel;
773*4882a593Smuzhiyun iio_chan->datasheet_name = vadc_chan->datasheet_name;
774*4882a593Smuzhiyun iio_chan->info_mask_separate = vadc_chan->info_mask;
775*4882a593Smuzhiyun iio_chan->type = vadc_chan->type;
776*4882a593Smuzhiyun iio_chan->indexed = 1;
777*4882a593Smuzhiyun iio_chan->address = index++;
778*4882a593Smuzhiyun
779*4882a593Smuzhiyun iio_chan++;
780*4882a593Smuzhiyun }
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun /* These channels are mandatory, they are used as reference points */
783*4882a593Smuzhiyun if (!vadc_get_channel(vadc, VADC_REF_1250MV)) {
784*4882a593Smuzhiyun dev_err(vadc->dev, "Please define 1.25V channel\n");
785*4882a593Smuzhiyun return -ENODEV;
786*4882a593Smuzhiyun }
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun if (!vadc_get_channel(vadc, VADC_REF_625MV)) {
789*4882a593Smuzhiyun dev_err(vadc->dev, "Please define 0.625V channel\n");
790*4882a593Smuzhiyun return -ENODEV;
791*4882a593Smuzhiyun }
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun if (!vadc_get_channel(vadc, VADC_VDD_VADC)) {
794*4882a593Smuzhiyun dev_err(vadc->dev, "Please define VDD channel\n");
795*4882a593Smuzhiyun return -ENODEV;
796*4882a593Smuzhiyun }
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun if (!vadc_get_channel(vadc, VADC_GND_REF)) {
799*4882a593Smuzhiyun dev_err(vadc->dev, "Please define GND channel\n");
800*4882a593Smuzhiyun return -ENODEV;
801*4882a593Smuzhiyun }
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun return 0;
804*4882a593Smuzhiyun }
805*4882a593Smuzhiyun
vadc_isr(int irq,void * dev_id)806*4882a593Smuzhiyun static irqreturn_t vadc_isr(int irq, void *dev_id)
807*4882a593Smuzhiyun {
808*4882a593Smuzhiyun struct vadc_priv *vadc = dev_id;
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun complete(&vadc->complete);
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun return IRQ_HANDLED;
813*4882a593Smuzhiyun }
814*4882a593Smuzhiyun
vadc_check_revision(struct vadc_priv * vadc)815*4882a593Smuzhiyun static int vadc_check_revision(struct vadc_priv *vadc)
816*4882a593Smuzhiyun {
817*4882a593Smuzhiyun u8 val;
818*4882a593Smuzhiyun int ret;
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun ret = vadc_read(vadc, VADC_PERPH_TYPE, &val);
821*4882a593Smuzhiyun if (ret)
822*4882a593Smuzhiyun return ret;
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun if (val < VADC_PERPH_TYPE_ADC) {
825*4882a593Smuzhiyun dev_err(vadc->dev, "%d is not ADC\n", val);
826*4882a593Smuzhiyun return -ENODEV;
827*4882a593Smuzhiyun }
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun ret = vadc_read(vadc, VADC_PERPH_SUBTYPE, &val);
830*4882a593Smuzhiyun if (ret)
831*4882a593Smuzhiyun return ret;
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun if (val < VADC_PERPH_SUBTYPE_VADC) {
834*4882a593Smuzhiyun dev_err(vadc->dev, "%d is not VADC\n", val);
835*4882a593Smuzhiyun return -ENODEV;
836*4882a593Smuzhiyun }
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun ret = vadc_read(vadc, VADC_REVISION2, &val);
839*4882a593Smuzhiyun if (ret)
840*4882a593Smuzhiyun return ret;
841*4882a593Smuzhiyun
842*4882a593Smuzhiyun if (val < VADC_REVISION2_SUPPORTED_VADC) {
843*4882a593Smuzhiyun dev_err(vadc->dev, "revision %d not supported\n", val);
844*4882a593Smuzhiyun return -ENODEV;
845*4882a593Smuzhiyun }
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun return 0;
848*4882a593Smuzhiyun }
849*4882a593Smuzhiyun
vadc_probe(struct platform_device * pdev)850*4882a593Smuzhiyun static int vadc_probe(struct platform_device *pdev)
851*4882a593Smuzhiyun {
852*4882a593Smuzhiyun struct device_node *node = pdev->dev.of_node;
853*4882a593Smuzhiyun struct device *dev = &pdev->dev;
854*4882a593Smuzhiyun struct iio_dev *indio_dev;
855*4882a593Smuzhiyun struct vadc_priv *vadc;
856*4882a593Smuzhiyun struct regmap *regmap;
857*4882a593Smuzhiyun int ret, irq_eoc;
858*4882a593Smuzhiyun u32 reg;
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun regmap = dev_get_regmap(dev->parent, NULL);
861*4882a593Smuzhiyun if (!regmap)
862*4882a593Smuzhiyun return -ENODEV;
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun ret = of_property_read_u32(node, "reg", ®);
865*4882a593Smuzhiyun if (ret < 0)
866*4882a593Smuzhiyun return ret;
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(dev, sizeof(*vadc));
869*4882a593Smuzhiyun if (!indio_dev)
870*4882a593Smuzhiyun return -ENOMEM;
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun vadc = iio_priv(indio_dev);
873*4882a593Smuzhiyun vadc->regmap = regmap;
874*4882a593Smuzhiyun vadc->dev = dev;
875*4882a593Smuzhiyun vadc->base = reg;
876*4882a593Smuzhiyun vadc->are_ref_measured = false;
877*4882a593Smuzhiyun init_completion(&vadc->complete);
878*4882a593Smuzhiyun mutex_init(&vadc->lock);
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun ret = vadc_check_revision(vadc);
881*4882a593Smuzhiyun if (ret)
882*4882a593Smuzhiyun return ret;
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun ret = vadc_get_dt_data(vadc, node);
885*4882a593Smuzhiyun if (ret)
886*4882a593Smuzhiyun return ret;
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun irq_eoc = platform_get_irq(pdev, 0);
889*4882a593Smuzhiyun if (irq_eoc < 0) {
890*4882a593Smuzhiyun if (irq_eoc == -EPROBE_DEFER || irq_eoc == -EINVAL)
891*4882a593Smuzhiyun return irq_eoc;
892*4882a593Smuzhiyun vadc->poll_eoc = true;
893*4882a593Smuzhiyun } else {
894*4882a593Smuzhiyun ret = devm_request_irq(dev, irq_eoc, vadc_isr, 0,
895*4882a593Smuzhiyun "spmi-vadc", vadc);
896*4882a593Smuzhiyun if (ret)
897*4882a593Smuzhiyun return ret;
898*4882a593Smuzhiyun }
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun ret = vadc_reset(vadc);
901*4882a593Smuzhiyun if (ret) {
902*4882a593Smuzhiyun dev_err(dev, "reset failed\n");
903*4882a593Smuzhiyun return ret;
904*4882a593Smuzhiyun }
905*4882a593Smuzhiyun
906*4882a593Smuzhiyun ret = vadc_measure_ref_points(vadc);
907*4882a593Smuzhiyun if (ret)
908*4882a593Smuzhiyun return ret;
909*4882a593Smuzhiyun
910*4882a593Smuzhiyun indio_dev->name = pdev->name;
911*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
912*4882a593Smuzhiyun indio_dev->info = &vadc_info;
913*4882a593Smuzhiyun indio_dev->channels = vadc->iio_chans;
914*4882a593Smuzhiyun indio_dev->num_channels = vadc->nchannels;
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun return devm_iio_device_register(dev, indio_dev);
917*4882a593Smuzhiyun }
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun static const struct of_device_id vadc_match_table[] = {
920*4882a593Smuzhiyun { .compatible = "qcom,spmi-vadc" },
921*4882a593Smuzhiyun { }
922*4882a593Smuzhiyun };
923*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, vadc_match_table);
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun static struct platform_driver vadc_driver = {
926*4882a593Smuzhiyun .driver = {
927*4882a593Smuzhiyun .name = "qcom-spmi-vadc",
928*4882a593Smuzhiyun .of_match_table = vadc_match_table,
929*4882a593Smuzhiyun },
930*4882a593Smuzhiyun .probe = vadc_probe,
931*4882a593Smuzhiyun };
932*4882a593Smuzhiyun module_platform_driver(vadc_driver);
933*4882a593Smuzhiyun
934*4882a593Smuzhiyun MODULE_ALIAS("platform:qcom-spmi-vadc");
935*4882a593Smuzhiyun MODULE_DESCRIPTION("Qualcomm SPMI PMIC voltage ADC driver");
936*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
937*4882a593Smuzhiyun MODULE_AUTHOR("Stanimir Varbanov <svarbanov@mm-sol.com>");
938*4882a593Smuzhiyun MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
939