xref: /OK3568_Linux_fs/kernel/drivers/iio/adc/hx711.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * HX711: analog to digital converter for weight sensor module
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2016 Andreas Klinger <ak@it-klinger.de>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun #include <linux/err.h>
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/property.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun #include <linux/sched.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/iio/iio.h>
17*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
18*4882a593Smuzhiyun #include <linux/iio/buffer.h>
19*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
20*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
21*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
22*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun /* gain to pulse and scale conversion */
25*4882a593Smuzhiyun #define HX711_GAIN_MAX		3
26*4882a593Smuzhiyun #define HX711_RESET_GAIN	128
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun struct hx711_gain_to_scale {
29*4882a593Smuzhiyun 	int			gain;
30*4882a593Smuzhiyun 	int			gain_pulse;
31*4882a593Smuzhiyun 	int			scale;
32*4882a593Smuzhiyun 	int			channel;
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun  * .scale depends on AVDD which in turn is known as soon as the regulator
37*4882a593Smuzhiyun  * is available
38*4882a593Smuzhiyun  * therefore we set .scale in hx711_probe()
39*4882a593Smuzhiyun  *
40*4882a593Smuzhiyun  * channel A in documentation is channel 0 in source code
41*4882a593Smuzhiyun  * channel B in documentation is channel 1 in source code
42*4882a593Smuzhiyun  */
43*4882a593Smuzhiyun static struct hx711_gain_to_scale hx711_gain_to_scale[HX711_GAIN_MAX] = {
44*4882a593Smuzhiyun 	{ 128, 1, 0, 0 },
45*4882a593Smuzhiyun 	{  32, 2, 0, 1 },
46*4882a593Smuzhiyun 	{  64, 3, 0, 0 }
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun 
hx711_get_gain_to_pulse(int gain)49*4882a593Smuzhiyun static int hx711_get_gain_to_pulse(int gain)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun 	int i;
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	for (i = 0; i < HX711_GAIN_MAX; i++)
54*4882a593Smuzhiyun 		if (hx711_gain_to_scale[i].gain == gain)
55*4882a593Smuzhiyun 			return hx711_gain_to_scale[i].gain_pulse;
56*4882a593Smuzhiyun 	return 1;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun 
hx711_get_gain_to_scale(int gain)59*4882a593Smuzhiyun static int hx711_get_gain_to_scale(int gain)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun 	int i;
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	for (i = 0; i < HX711_GAIN_MAX; i++)
64*4882a593Smuzhiyun 		if (hx711_gain_to_scale[i].gain == gain)
65*4882a593Smuzhiyun 			return hx711_gain_to_scale[i].scale;
66*4882a593Smuzhiyun 	return 0;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun 
hx711_get_scale_to_gain(int scale)69*4882a593Smuzhiyun static int hx711_get_scale_to_gain(int scale)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun 	int i;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	for (i = 0; i < HX711_GAIN_MAX; i++)
74*4882a593Smuzhiyun 		if (hx711_gain_to_scale[i].scale == scale)
75*4882a593Smuzhiyun 			return hx711_gain_to_scale[i].gain;
76*4882a593Smuzhiyun 	return -EINVAL;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun struct hx711_data {
80*4882a593Smuzhiyun 	struct device		*dev;
81*4882a593Smuzhiyun 	struct gpio_desc	*gpiod_pd_sck;
82*4882a593Smuzhiyun 	struct gpio_desc	*gpiod_dout;
83*4882a593Smuzhiyun 	struct regulator	*reg_avdd;
84*4882a593Smuzhiyun 	int			gain_set;	/* gain set on device */
85*4882a593Smuzhiyun 	int			gain_chan_a;	/* gain for channel A */
86*4882a593Smuzhiyun 	struct mutex		lock;
87*4882a593Smuzhiyun 	/*
88*4882a593Smuzhiyun 	 * triggered buffer
89*4882a593Smuzhiyun 	 * 2x32-bit channel + 64-bit naturally aligned timestamp
90*4882a593Smuzhiyun 	 */
91*4882a593Smuzhiyun 	u32			buffer[4] __aligned(8);
92*4882a593Smuzhiyun 	/*
93*4882a593Smuzhiyun 	 * delay after a rising edge on SCK until the data is ready DOUT
94*4882a593Smuzhiyun 	 * this is dependent on the hx711 where the datasheet tells a
95*4882a593Smuzhiyun 	 * maximum value of 100 ns
96*4882a593Smuzhiyun 	 * but also on potential parasitic capacities on the wiring
97*4882a593Smuzhiyun 	 */
98*4882a593Smuzhiyun 	u32			data_ready_delay_ns;
99*4882a593Smuzhiyun 	u32			clock_frequency;
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun 
hx711_cycle(struct hx711_data * hx711_data)102*4882a593Smuzhiyun static int hx711_cycle(struct hx711_data *hx711_data)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	unsigned long flags;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	/*
107*4882a593Smuzhiyun 	 * if preempted for more then 60us while PD_SCK is high:
108*4882a593Smuzhiyun 	 * hx711 is going in reset
109*4882a593Smuzhiyun 	 * ==> measuring is false
110*4882a593Smuzhiyun 	 */
111*4882a593Smuzhiyun 	local_irq_save(flags);
112*4882a593Smuzhiyun 	gpiod_set_value(hx711_data->gpiod_pd_sck, 1);
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	/*
115*4882a593Smuzhiyun 	 * wait until DOUT is ready
116*4882a593Smuzhiyun 	 * it turned out that parasitic capacities are extending the time
117*4882a593Smuzhiyun 	 * until DOUT has reached it's value
118*4882a593Smuzhiyun 	 */
119*4882a593Smuzhiyun 	ndelay(hx711_data->data_ready_delay_ns);
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	/*
122*4882a593Smuzhiyun 	 * here we are not waiting for 0.2 us as suggested by the datasheet,
123*4882a593Smuzhiyun 	 * because the oscilloscope showed in a test scenario
124*4882a593Smuzhiyun 	 * at least 1.15 us for PD_SCK high (T3 in datasheet)
125*4882a593Smuzhiyun 	 * and 0.56 us for PD_SCK low on TI Sitara with 800 MHz
126*4882a593Smuzhiyun 	 */
127*4882a593Smuzhiyun 	gpiod_set_value(hx711_data->gpiod_pd_sck, 0);
128*4882a593Smuzhiyun 	local_irq_restore(flags);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	/*
131*4882a593Smuzhiyun 	 * make it a square wave for addressing cases with capacitance on
132*4882a593Smuzhiyun 	 * PC_SCK
133*4882a593Smuzhiyun 	 */
134*4882a593Smuzhiyun 	ndelay(hx711_data->data_ready_delay_ns);
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	/* sample as late as possible */
137*4882a593Smuzhiyun 	return gpiod_get_value(hx711_data->gpiod_dout);
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
hx711_read(struct hx711_data * hx711_data)140*4882a593Smuzhiyun static int hx711_read(struct hx711_data *hx711_data)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	int i, ret;
143*4882a593Smuzhiyun 	int value = 0;
144*4882a593Smuzhiyun 	int val = gpiod_get_value(hx711_data->gpiod_dout);
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	/* we double check if it's really down */
147*4882a593Smuzhiyun 	if (val)
148*4882a593Smuzhiyun 		return -EIO;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	for (i = 0; i < 24; i++) {
151*4882a593Smuzhiyun 		value <<= 1;
152*4882a593Smuzhiyun 		ret = hx711_cycle(hx711_data);
153*4882a593Smuzhiyun 		if (ret)
154*4882a593Smuzhiyun 			value++;
155*4882a593Smuzhiyun 	}
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	value ^= 0x800000;
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	for (i = 0; i < hx711_get_gain_to_pulse(hx711_data->gain_set); i++)
160*4882a593Smuzhiyun 		hx711_cycle(hx711_data);
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun 	return value;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun 
hx711_wait_for_ready(struct hx711_data * hx711_data)165*4882a593Smuzhiyun static int hx711_wait_for_ready(struct hx711_data *hx711_data)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun 	int i, val;
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun 	/*
170*4882a593Smuzhiyun 	 * in some rare cases the reset takes quite a long time
171*4882a593Smuzhiyun 	 * especially when the channel is changed.
172*4882a593Smuzhiyun 	 * Allow up to one second for it
173*4882a593Smuzhiyun 	 */
174*4882a593Smuzhiyun 	for (i = 0; i < 100; i++) {
175*4882a593Smuzhiyun 		val = gpiod_get_value(hx711_data->gpiod_dout);
176*4882a593Smuzhiyun 		if (!val)
177*4882a593Smuzhiyun 			break;
178*4882a593Smuzhiyun 		/* sleep at least 10 ms */
179*4882a593Smuzhiyun 		msleep(10);
180*4882a593Smuzhiyun 	}
181*4882a593Smuzhiyun 	if (val)
182*4882a593Smuzhiyun 		return -EIO;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	return 0;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun 
hx711_reset(struct hx711_data * hx711_data)187*4882a593Smuzhiyun static int hx711_reset(struct hx711_data *hx711_data)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun 	int val = hx711_wait_for_ready(hx711_data);
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	if (val) {
192*4882a593Smuzhiyun 		/*
193*4882a593Smuzhiyun 		 * an examination with the oszilloscope indicated
194*4882a593Smuzhiyun 		 * that the first value read after the reset is not stable
195*4882a593Smuzhiyun 		 * if we reset too short;
196*4882a593Smuzhiyun 		 * the shorter the reset cycle
197*4882a593Smuzhiyun 		 * the less reliable the first value after reset is;
198*4882a593Smuzhiyun 		 * there were no problems encountered with a value
199*4882a593Smuzhiyun 		 * of 10 ms or higher
200*4882a593Smuzhiyun 		 */
201*4882a593Smuzhiyun 		gpiod_set_value(hx711_data->gpiod_pd_sck, 1);
202*4882a593Smuzhiyun 		msleep(10);
203*4882a593Smuzhiyun 		gpiod_set_value(hx711_data->gpiod_pd_sck, 0);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 		val = hx711_wait_for_ready(hx711_data);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 		/* after a reset the gain is 128 */
208*4882a593Smuzhiyun 		hx711_data->gain_set = HX711_RESET_GAIN;
209*4882a593Smuzhiyun 	}
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 	return val;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun 
hx711_set_gain_for_channel(struct hx711_data * hx711_data,int chan)214*4882a593Smuzhiyun static int hx711_set_gain_for_channel(struct hx711_data *hx711_data, int chan)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun 	int ret;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	if (chan == 0) {
219*4882a593Smuzhiyun 		if (hx711_data->gain_set == 32) {
220*4882a593Smuzhiyun 			hx711_data->gain_set = hx711_data->gain_chan_a;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 			ret = hx711_read(hx711_data);
223*4882a593Smuzhiyun 			if (ret < 0)
224*4882a593Smuzhiyun 				return ret;
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 			ret = hx711_wait_for_ready(hx711_data);
227*4882a593Smuzhiyun 			if (ret)
228*4882a593Smuzhiyun 				return ret;
229*4882a593Smuzhiyun 		}
230*4882a593Smuzhiyun 	} else {
231*4882a593Smuzhiyun 		if (hx711_data->gain_set != 32) {
232*4882a593Smuzhiyun 			hx711_data->gain_set = 32;
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 			ret = hx711_read(hx711_data);
235*4882a593Smuzhiyun 			if (ret < 0)
236*4882a593Smuzhiyun 				return ret;
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 			ret = hx711_wait_for_ready(hx711_data);
239*4882a593Smuzhiyun 			if (ret)
240*4882a593Smuzhiyun 				return ret;
241*4882a593Smuzhiyun 		}
242*4882a593Smuzhiyun 	}
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	return 0;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun 
hx711_reset_read(struct hx711_data * hx711_data,int chan)247*4882a593Smuzhiyun static int hx711_reset_read(struct hx711_data *hx711_data, int chan)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun 	int ret;
250*4882a593Smuzhiyun 	int val;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	/*
253*4882a593Smuzhiyun 	 * hx711_reset() must be called from here
254*4882a593Smuzhiyun 	 * because it could be calling hx711_read() by itself
255*4882a593Smuzhiyun 	 */
256*4882a593Smuzhiyun 	if (hx711_reset(hx711_data)) {
257*4882a593Smuzhiyun 		dev_err(hx711_data->dev, "reset failed!");
258*4882a593Smuzhiyun 		return -EIO;
259*4882a593Smuzhiyun 	}
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	ret = hx711_set_gain_for_channel(hx711_data, chan);
262*4882a593Smuzhiyun 	if (ret < 0)
263*4882a593Smuzhiyun 		return ret;
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	val = hx711_read(hx711_data);
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	return val;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun 
hx711_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long mask)270*4882a593Smuzhiyun static int hx711_read_raw(struct iio_dev *indio_dev,
271*4882a593Smuzhiyun 				const struct iio_chan_spec *chan,
272*4882a593Smuzhiyun 				int *val, int *val2, long mask)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun 	struct hx711_data *hx711_data = iio_priv(indio_dev);
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	switch (mask) {
277*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
278*4882a593Smuzhiyun 		mutex_lock(&hx711_data->lock);
279*4882a593Smuzhiyun 
280*4882a593Smuzhiyun 		*val = hx711_reset_read(hx711_data, chan->channel);
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 		mutex_unlock(&hx711_data->lock);
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 		if (*val < 0)
285*4882a593Smuzhiyun 			return *val;
286*4882a593Smuzhiyun 		return IIO_VAL_INT;
287*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
288*4882a593Smuzhiyun 		*val = 0;
289*4882a593Smuzhiyun 		mutex_lock(&hx711_data->lock);
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 		*val2 = hx711_get_gain_to_scale(hx711_data->gain_set);
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 		mutex_unlock(&hx711_data->lock);
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 		return IIO_VAL_INT_PLUS_NANO;
296*4882a593Smuzhiyun 	default:
297*4882a593Smuzhiyun 		return -EINVAL;
298*4882a593Smuzhiyun 	}
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun 
hx711_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)301*4882a593Smuzhiyun static int hx711_write_raw(struct iio_dev *indio_dev,
302*4882a593Smuzhiyun 				struct iio_chan_spec const *chan,
303*4882a593Smuzhiyun 				int val,
304*4882a593Smuzhiyun 				int val2,
305*4882a593Smuzhiyun 				long mask)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun 	struct hx711_data *hx711_data = iio_priv(indio_dev);
308*4882a593Smuzhiyun 	int ret;
309*4882a593Smuzhiyun 	int gain;
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	switch (mask) {
312*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
313*4882a593Smuzhiyun 		/*
314*4882a593Smuzhiyun 		 * a scale greater than 1 mV per LSB is not possible
315*4882a593Smuzhiyun 		 * with the HX711, therefore val must be 0
316*4882a593Smuzhiyun 		 */
317*4882a593Smuzhiyun 		if (val != 0)
318*4882a593Smuzhiyun 			return -EINVAL;
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 		mutex_lock(&hx711_data->lock);
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 		gain = hx711_get_scale_to_gain(val2);
323*4882a593Smuzhiyun 		if (gain < 0) {
324*4882a593Smuzhiyun 			mutex_unlock(&hx711_data->lock);
325*4882a593Smuzhiyun 			return gain;
326*4882a593Smuzhiyun 		}
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 		if (gain != hx711_data->gain_set) {
329*4882a593Smuzhiyun 			hx711_data->gain_set = gain;
330*4882a593Smuzhiyun 			if (gain != 32)
331*4882a593Smuzhiyun 				hx711_data->gain_chan_a = gain;
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 			ret = hx711_read(hx711_data);
334*4882a593Smuzhiyun 			if (ret < 0) {
335*4882a593Smuzhiyun 				mutex_unlock(&hx711_data->lock);
336*4882a593Smuzhiyun 				return ret;
337*4882a593Smuzhiyun 			}
338*4882a593Smuzhiyun 		}
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 		mutex_unlock(&hx711_data->lock);
341*4882a593Smuzhiyun 		return 0;
342*4882a593Smuzhiyun 	default:
343*4882a593Smuzhiyun 		return -EINVAL;
344*4882a593Smuzhiyun 	}
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	return 0;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun 
hx711_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)349*4882a593Smuzhiyun static int hx711_write_raw_get_fmt(struct iio_dev *indio_dev,
350*4882a593Smuzhiyun 		struct iio_chan_spec const *chan,
351*4882a593Smuzhiyun 		long mask)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun 	return IIO_VAL_INT_PLUS_NANO;
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun 
hx711_trigger(int irq,void * p)356*4882a593Smuzhiyun static irqreturn_t hx711_trigger(int irq, void *p)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun 	struct iio_poll_func *pf = p;
359*4882a593Smuzhiyun 	struct iio_dev *indio_dev = pf->indio_dev;
360*4882a593Smuzhiyun 	struct hx711_data *hx711_data = iio_priv(indio_dev);
361*4882a593Smuzhiyun 	int i, j = 0;
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	mutex_lock(&hx711_data->lock);
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	memset(hx711_data->buffer, 0, sizeof(hx711_data->buffer));
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	for (i = 0; i < indio_dev->masklength; i++) {
368*4882a593Smuzhiyun 		if (!test_bit(i, indio_dev->active_scan_mask))
369*4882a593Smuzhiyun 			continue;
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 		hx711_data->buffer[j] = hx711_reset_read(hx711_data,
372*4882a593Smuzhiyun 					indio_dev->channels[i].channel);
373*4882a593Smuzhiyun 		j++;
374*4882a593Smuzhiyun 	}
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 	iio_push_to_buffers_with_timestamp(indio_dev, hx711_data->buffer,
377*4882a593Smuzhiyun 							pf->timestamp);
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	mutex_unlock(&hx711_data->lock);
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	iio_trigger_notify_done(indio_dev->trig);
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun 	return IRQ_HANDLED;
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun 
hx711_scale_available_show(struct device * dev,struct device_attribute * attr,char * buf)386*4882a593Smuzhiyun static ssize_t hx711_scale_available_show(struct device *dev,
387*4882a593Smuzhiyun 				struct device_attribute *attr,
388*4882a593Smuzhiyun 				char *buf)
389*4882a593Smuzhiyun {
390*4882a593Smuzhiyun 	struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
391*4882a593Smuzhiyun 	int channel = iio_attr->address;
392*4882a593Smuzhiyun 	int i, len = 0;
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	for (i = 0; i < HX711_GAIN_MAX; i++)
395*4882a593Smuzhiyun 		if (hx711_gain_to_scale[i].channel == channel)
396*4882a593Smuzhiyun 			len += sprintf(buf + len, "0.%09d ",
397*4882a593Smuzhiyun 					hx711_gain_to_scale[i].scale);
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun 	len += sprintf(buf + len, "\n");
400*4882a593Smuzhiyun 
401*4882a593Smuzhiyun 	return len;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun static IIO_DEVICE_ATTR(in_voltage0_scale_available, S_IRUGO,
405*4882a593Smuzhiyun 	hx711_scale_available_show, NULL, 0);
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun static IIO_DEVICE_ATTR(in_voltage1_scale_available, S_IRUGO,
408*4882a593Smuzhiyun 	hx711_scale_available_show, NULL, 1);
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun static struct attribute *hx711_attributes[] = {
411*4882a593Smuzhiyun 	&iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
412*4882a593Smuzhiyun 	&iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
413*4882a593Smuzhiyun 	NULL,
414*4882a593Smuzhiyun };
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun static const struct attribute_group hx711_attribute_group = {
417*4882a593Smuzhiyun 	.attrs = hx711_attributes,
418*4882a593Smuzhiyun };
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun static const struct iio_info hx711_iio_info = {
421*4882a593Smuzhiyun 	.read_raw		= hx711_read_raw,
422*4882a593Smuzhiyun 	.write_raw		= hx711_write_raw,
423*4882a593Smuzhiyun 	.write_raw_get_fmt	= hx711_write_raw_get_fmt,
424*4882a593Smuzhiyun 	.attrs			= &hx711_attribute_group,
425*4882a593Smuzhiyun };
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun static const struct iio_chan_spec hx711_chan_spec[] = {
428*4882a593Smuzhiyun 	{
429*4882a593Smuzhiyun 		.type = IIO_VOLTAGE,
430*4882a593Smuzhiyun 		.channel = 0,
431*4882a593Smuzhiyun 		.indexed = 1,
432*4882a593Smuzhiyun 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
433*4882a593Smuzhiyun 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
434*4882a593Smuzhiyun 		.scan_index = 0,
435*4882a593Smuzhiyun 		.scan_type = {
436*4882a593Smuzhiyun 			.sign = 'u',
437*4882a593Smuzhiyun 			.realbits = 24,
438*4882a593Smuzhiyun 			.storagebits = 32,
439*4882a593Smuzhiyun 			.endianness = IIO_CPU,
440*4882a593Smuzhiyun 		},
441*4882a593Smuzhiyun 	},
442*4882a593Smuzhiyun 	{
443*4882a593Smuzhiyun 		.type = IIO_VOLTAGE,
444*4882a593Smuzhiyun 		.channel = 1,
445*4882a593Smuzhiyun 		.indexed = 1,
446*4882a593Smuzhiyun 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
447*4882a593Smuzhiyun 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
448*4882a593Smuzhiyun 		.scan_index = 1,
449*4882a593Smuzhiyun 		.scan_type = {
450*4882a593Smuzhiyun 			.sign = 'u',
451*4882a593Smuzhiyun 			.realbits = 24,
452*4882a593Smuzhiyun 			.storagebits = 32,
453*4882a593Smuzhiyun 			.endianness = IIO_CPU,
454*4882a593Smuzhiyun 		},
455*4882a593Smuzhiyun 	},
456*4882a593Smuzhiyun 	IIO_CHAN_SOFT_TIMESTAMP(2),
457*4882a593Smuzhiyun };
458*4882a593Smuzhiyun 
hx711_probe(struct platform_device * pdev)459*4882a593Smuzhiyun static int hx711_probe(struct platform_device *pdev)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
462*4882a593Smuzhiyun 	struct device_node *np = dev->of_node;
463*4882a593Smuzhiyun 	struct hx711_data *hx711_data;
464*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
465*4882a593Smuzhiyun 	int ret;
466*4882a593Smuzhiyun 	int i;
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(dev, sizeof(struct hx711_data));
469*4882a593Smuzhiyun 	if (!indio_dev) {
470*4882a593Smuzhiyun 		dev_err(dev, "failed to allocate IIO device\n");
471*4882a593Smuzhiyun 		return -ENOMEM;
472*4882a593Smuzhiyun 	}
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 	hx711_data = iio_priv(indio_dev);
475*4882a593Smuzhiyun 	hx711_data->dev = dev;
476*4882a593Smuzhiyun 
477*4882a593Smuzhiyun 	mutex_init(&hx711_data->lock);
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun 	/*
480*4882a593Smuzhiyun 	 * PD_SCK stands for power down and serial clock input of HX711
481*4882a593Smuzhiyun 	 * in the driver it is an output
482*4882a593Smuzhiyun 	 */
483*4882a593Smuzhiyun 	hx711_data->gpiod_pd_sck = devm_gpiod_get(dev, "sck", GPIOD_OUT_LOW);
484*4882a593Smuzhiyun 	if (IS_ERR(hx711_data->gpiod_pd_sck)) {
485*4882a593Smuzhiyun 		dev_err(dev, "failed to get sck-gpiod: err=%ld\n",
486*4882a593Smuzhiyun 					PTR_ERR(hx711_data->gpiod_pd_sck));
487*4882a593Smuzhiyun 		return PTR_ERR(hx711_data->gpiod_pd_sck);
488*4882a593Smuzhiyun 	}
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	/*
491*4882a593Smuzhiyun 	 * DOUT stands for serial data output of HX711
492*4882a593Smuzhiyun 	 * for the driver it is an input
493*4882a593Smuzhiyun 	 */
494*4882a593Smuzhiyun 	hx711_data->gpiod_dout = devm_gpiod_get(dev, "dout", GPIOD_IN);
495*4882a593Smuzhiyun 	if (IS_ERR(hx711_data->gpiod_dout)) {
496*4882a593Smuzhiyun 		dev_err(dev, "failed to get dout-gpiod: err=%ld\n",
497*4882a593Smuzhiyun 					PTR_ERR(hx711_data->gpiod_dout));
498*4882a593Smuzhiyun 		return PTR_ERR(hx711_data->gpiod_dout);
499*4882a593Smuzhiyun 	}
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun 	hx711_data->reg_avdd = devm_regulator_get(dev, "avdd");
502*4882a593Smuzhiyun 	if (IS_ERR(hx711_data->reg_avdd))
503*4882a593Smuzhiyun 		return PTR_ERR(hx711_data->reg_avdd);
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun 	ret = regulator_enable(hx711_data->reg_avdd);
506*4882a593Smuzhiyun 	if (ret < 0)
507*4882a593Smuzhiyun 		return ret;
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	/*
510*4882a593Smuzhiyun 	 * with
511*4882a593Smuzhiyun 	 * full scale differential input range: AVDD / GAIN
512*4882a593Smuzhiyun 	 * full scale output data: 2^24
513*4882a593Smuzhiyun 	 * we can say:
514*4882a593Smuzhiyun 	 *     AVDD / GAIN = 2^24
515*4882a593Smuzhiyun 	 * therefore:
516*4882a593Smuzhiyun 	 *     1 LSB = AVDD / GAIN / 2^24
517*4882a593Smuzhiyun 	 * AVDD is in uV, but we need 10^-9 mV
518*4882a593Smuzhiyun 	 * approximately to fit into a 32 bit number:
519*4882a593Smuzhiyun 	 * 1 LSB = (AVDD * 100) / GAIN / 1678 [10^-9 mV]
520*4882a593Smuzhiyun 	 */
521*4882a593Smuzhiyun 	ret = regulator_get_voltage(hx711_data->reg_avdd);
522*4882a593Smuzhiyun 	if (ret < 0)
523*4882a593Smuzhiyun 		goto error_regulator;
524*4882a593Smuzhiyun 
525*4882a593Smuzhiyun 	/* we need 10^-9 mV */
526*4882a593Smuzhiyun 	ret *= 100;
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun 	for (i = 0; i < HX711_GAIN_MAX; i++)
529*4882a593Smuzhiyun 		hx711_gain_to_scale[i].scale =
530*4882a593Smuzhiyun 			ret / hx711_gain_to_scale[i].gain / 1678;
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 	hx711_data->gain_set = 128;
533*4882a593Smuzhiyun 	hx711_data->gain_chan_a = 128;
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	hx711_data->clock_frequency = 400000;
536*4882a593Smuzhiyun 	ret = of_property_read_u32(np, "clock-frequency",
537*4882a593Smuzhiyun 					&hx711_data->clock_frequency);
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun 	/*
540*4882a593Smuzhiyun 	 * datasheet says the high level of PD_SCK has a maximum duration
541*4882a593Smuzhiyun 	 * of 50 microseconds
542*4882a593Smuzhiyun 	 */
543*4882a593Smuzhiyun 	if (hx711_data->clock_frequency < 20000) {
544*4882a593Smuzhiyun 		dev_warn(dev, "clock-frequency too low - assuming 400 kHz\n");
545*4882a593Smuzhiyun 		hx711_data->clock_frequency = 400000;
546*4882a593Smuzhiyun 	}
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun 	hx711_data->data_ready_delay_ns =
549*4882a593Smuzhiyun 				1000000000 / hx711_data->clock_frequency;
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 	platform_set_drvdata(pdev, indio_dev);
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun 	indio_dev->name = "hx711";
554*4882a593Smuzhiyun 	indio_dev->info = &hx711_iio_info;
555*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
556*4882a593Smuzhiyun 	indio_dev->channels = hx711_chan_spec;
557*4882a593Smuzhiyun 	indio_dev->num_channels = ARRAY_SIZE(hx711_chan_spec);
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 	ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time,
560*4882a593Smuzhiyun 							hx711_trigger, NULL);
561*4882a593Smuzhiyun 	if (ret < 0) {
562*4882a593Smuzhiyun 		dev_err(dev, "setup of iio triggered buffer failed\n");
563*4882a593Smuzhiyun 		goto error_regulator;
564*4882a593Smuzhiyun 	}
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun 	ret = iio_device_register(indio_dev);
567*4882a593Smuzhiyun 	if (ret < 0) {
568*4882a593Smuzhiyun 		dev_err(dev, "Couldn't register the device\n");
569*4882a593Smuzhiyun 		goto error_buffer;
570*4882a593Smuzhiyun 	}
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 	return 0;
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun error_buffer:
575*4882a593Smuzhiyun 	iio_triggered_buffer_cleanup(indio_dev);
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun error_regulator:
578*4882a593Smuzhiyun 	regulator_disable(hx711_data->reg_avdd);
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 	return ret;
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun 
hx711_remove(struct platform_device * pdev)583*4882a593Smuzhiyun static int hx711_remove(struct platform_device *pdev)
584*4882a593Smuzhiyun {
585*4882a593Smuzhiyun 	struct hx711_data *hx711_data;
586*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun 	indio_dev = platform_get_drvdata(pdev);
589*4882a593Smuzhiyun 	hx711_data = iio_priv(indio_dev);
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	iio_device_unregister(indio_dev);
592*4882a593Smuzhiyun 
593*4882a593Smuzhiyun 	iio_triggered_buffer_cleanup(indio_dev);
594*4882a593Smuzhiyun 
595*4882a593Smuzhiyun 	regulator_disable(hx711_data->reg_avdd);
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun 	return 0;
598*4882a593Smuzhiyun }
599*4882a593Smuzhiyun 
600*4882a593Smuzhiyun static const struct of_device_id of_hx711_match[] = {
601*4882a593Smuzhiyun 	{ .compatible = "avia,hx711", },
602*4882a593Smuzhiyun 	{},
603*4882a593Smuzhiyun };
604*4882a593Smuzhiyun 
605*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, of_hx711_match);
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun static struct platform_driver hx711_driver = {
608*4882a593Smuzhiyun 	.probe		= hx711_probe,
609*4882a593Smuzhiyun 	.remove		= hx711_remove,
610*4882a593Smuzhiyun 	.driver		= {
611*4882a593Smuzhiyun 		.name		= "hx711-gpio",
612*4882a593Smuzhiyun 		.of_match_table	= of_hx711_match,
613*4882a593Smuzhiyun 	},
614*4882a593Smuzhiyun };
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun module_platform_driver(hx711_driver);
617*4882a593Smuzhiyun 
618*4882a593Smuzhiyun MODULE_AUTHOR("Andreas Klinger <ak@it-klinger.de>");
619*4882a593Smuzhiyun MODULE_DESCRIPTION("HX711 bitbanging driver - ADC for weight cells");
620*4882a593Smuzhiyun MODULE_LICENSE("GPL");
621*4882a593Smuzhiyun MODULE_ALIAS("platform:hx711-gpio");
622*4882a593Smuzhiyun 
623