1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * iio/adc/ad799x.c
4*4882a593Smuzhiyun * Copyright (C) 2010-2011 Michael Hennerich, Analog Devices Inc.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * based on iio/adc/max1363
7*4882a593Smuzhiyun * Copyright (C) 2008-2010 Jonathan Cameron
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * based on linux/drivers/i2c/chips/max123x
10*4882a593Smuzhiyun * Copyright (C) 2002-2004 Stefan Eletzhofer
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * based on linux/drivers/acron/char/pcf8583.c
13*4882a593Smuzhiyun * Copyright (C) 2000 Russell King
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * ad799x.c
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * Support for ad7991, ad7995, ad7999, ad7992, ad7993, ad7994, ad7997,
18*4882a593Smuzhiyun * ad7998 and similar chips.
19*4882a593Smuzhiyun */
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <linux/interrupt.h>
22*4882a593Smuzhiyun #include <linux/device.h>
23*4882a593Smuzhiyun #include <linux/kernel.h>
24*4882a593Smuzhiyun #include <linux/sysfs.h>
25*4882a593Smuzhiyun #include <linux/i2c.h>
26*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
27*4882a593Smuzhiyun #include <linux/slab.h>
28*4882a593Smuzhiyun #include <linux/types.h>
29*4882a593Smuzhiyun #include <linux/err.h>
30*4882a593Smuzhiyun #include <linux/module.h>
31*4882a593Smuzhiyun #include <linux/bitops.h>
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #include <linux/iio/iio.h>
34*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
35*4882a593Smuzhiyun #include <linux/iio/events.h>
36*4882a593Smuzhiyun #include <linux/iio/buffer.h>
37*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
38*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define AD799X_CHANNEL_SHIFT 4
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /*
43*4882a593Smuzhiyun * AD7991, AD7995 and AD7999 defines
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #define AD7991_REF_SEL 0x08
47*4882a593Smuzhiyun #define AD7991_FLTR 0x04
48*4882a593Smuzhiyun #define AD7991_BIT_TRIAL_DELAY 0x02
49*4882a593Smuzhiyun #define AD7991_SAMPLE_DELAY 0x01
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /*
52*4882a593Smuzhiyun * AD7992, AD7993, AD7994, AD7997 and AD7998 defines
53*4882a593Smuzhiyun */
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define AD7998_FLTR BIT(3)
56*4882a593Smuzhiyun #define AD7998_ALERT_EN BIT(2)
57*4882a593Smuzhiyun #define AD7998_BUSY_ALERT BIT(1)
58*4882a593Smuzhiyun #define AD7998_BUSY_ALERT_POL BIT(0)
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #define AD7998_CONV_RES_REG 0x0
61*4882a593Smuzhiyun #define AD7998_ALERT_STAT_REG 0x1
62*4882a593Smuzhiyun #define AD7998_CONF_REG 0x2
63*4882a593Smuzhiyun #define AD7998_CYCLE_TMR_REG 0x3
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #define AD7998_DATALOW_REG(x) ((x) * 3 + 0x4)
66*4882a593Smuzhiyun #define AD7998_DATAHIGH_REG(x) ((x) * 3 + 0x5)
67*4882a593Smuzhiyun #define AD7998_HYST_REG(x) ((x) * 3 + 0x6)
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #define AD7998_CYC_MASK GENMASK(2, 0)
70*4882a593Smuzhiyun #define AD7998_CYC_DIS 0x0
71*4882a593Smuzhiyun #define AD7998_CYC_TCONF_32 0x1
72*4882a593Smuzhiyun #define AD7998_CYC_TCONF_64 0x2
73*4882a593Smuzhiyun #define AD7998_CYC_TCONF_128 0x3
74*4882a593Smuzhiyun #define AD7998_CYC_TCONF_256 0x4
75*4882a593Smuzhiyun #define AD7998_CYC_TCONF_512 0x5
76*4882a593Smuzhiyun #define AD7998_CYC_TCONF_1024 0x6
77*4882a593Smuzhiyun #define AD7998_CYC_TCONF_2048 0x7
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #define AD7998_ALERT_STAT_CLEAR 0xFF
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /*
82*4882a593Smuzhiyun * AD7997 and AD7997 defines
83*4882a593Smuzhiyun */
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #define AD7997_8_READ_SINGLE BIT(7)
86*4882a593Smuzhiyun #define AD7997_8_READ_SEQUENCE (BIT(6) | BIT(5) | BIT(4))
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun enum {
89*4882a593Smuzhiyun ad7991,
90*4882a593Smuzhiyun ad7995,
91*4882a593Smuzhiyun ad7999,
92*4882a593Smuzhiyun ad7992,
93*4882a593Smuzhiyun ad7993,
94*4882a593Smuzhiyun ad7994,
95*4882a593Smuzhiyun ad7997,
96*4882a593Smuzhiyun ad7998
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /**
100*4882a593Smuzhiyun * struct ad799x_chip_config - chip specific information
101*4882a593Smuzhiyun * @channel: channel specification
102*4882a593Smuzhiyun * @default_config: device default configuration
103*4882a593Smuzhiyun * @info: pointer to iio_info struct
104*4882a593Smuzhiyun */
105*4882a593Smuzhiyun struct ad799x_chip_config {
106*4882a593Smuzhiyun const struct iio_chan_spec channel[9];
107*4882a593Smuzhiyun u16 default_config;
108*4882a593Smuzhiyun const struct iio_info *info;
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /**
112*4882a593Smuzhiyun * struct ad799x_chip_info - chip specific information
113*4882a593Smuzhiyun * @num_channels: number of channels
114*4882a593Smuzhiyun * @noirq_config: device configuration w/o IRQ
115*4882a593Smuzhiyun * @irq_config: device configuration w/IRQ
116*4882a593Smuzhiyun */
117*4882a593Smuzhiyun struct ad799x_chip_info {
118*4882a593Smuzhiyun int num_channels;
119*4882a593Smuzhiyun const struct ad799x_chip_config noirq_config;
120*4882a593Smuzhiyun const struct ad799x_chip_config irq_config;
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun struct ad799x_state {
124*4882a593Smuzhiyun struct i2c_client *client;
125*4882a593Smuzhiyun const struct ad799x_chip_config *chip_config;
126*4882a593Smuzhiyun struct regulator *reg;
127*4882a593Smuzhiyun struct regulator *vref;
128*4882a593Smuzhiyun unsigned id;
129*4882a593Smuzhiyun u16 config;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun u8 *rx_buf;
132*4882a593Smuzhiyun unsigned int transfer_size;
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun
ad799x_write_config(struct ad799x_state * st,u16 val)135*4882a593Smuzhiyun static int ad799x_write_config(struct ad799x_state *st, u16 val)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun switch (st->id) {
138*4882a593Smuzhiyun case ad7997:
139*4882a593Smuzhiyun case ad7998:
140*4882a593Smuzhiyun return i2c_smbus_write_word_swapped(st->client, AD7998_CONF_REG,
141*4882a593Smuzhiyun val);
142*4882a593Smuzhiyun case ad7992:
143*4882a593Smuzhiyun case ad7993:
144*4882a593Smuzhiyun case ad7994:
145*4882a593Smuzhiyun return i2c_smbus_write_byte_data(st->client, AD7998_CONF_REG,
146*4882a593Smuzhiyun val);
147*4882a593Smuzhiyun default:
148*4882a593Smuzhiyun /* Will be written when doing a conversion */
149*4882a593Smuzhiyun st->config = val;
150*4882a593Smuzhiyun return 0;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
ad799x_read_config(struct ad799x_state * st)154*4882a593Smuzhiyun static int ad799x_read_config(struct ad799x_state *st)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun switch (st->id) {
157*4882a593Smuzhiyun case ad7997:
158*4882a593Smuzhiyun case ad7998:
159*4882a593Smuzhiyun return i2c_smbus_read_word_swapped(st->client, AD7998_CONF_REG);
160*4882a593Smuzhiyun case ad7992:
161*4882a593Smuzhiyun case ad7993:
162*4882a593Smuzhiyun case ad7994:
163*4882a593Smuzhiyun return i2c_smbus_read_byte_data(st->client, AD7998_CONF_REG);
164*4882a593Smuzhiyun default:
165*4882a593Smuzhiyun /* No readback support */
166*4882a593Smuzhiyun return st->config;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
ad799x_update_config(struct ad799x_state * st,u16 config)170*4882a593Smuzhiyun static int ad799x_update_config(struct ad799x_state *st, u16 config)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun int ret;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun ret = ad799x_write_config(st, config);
175*4882a593Smuzhiyun if (ret < 0)
176*4882a593Smuzhiyun return ret;
177*4882a593Smuzhiyun ret = ad799x_read_config(st);
178*4882a593Smuzhiyun if (ret < 0)
179*4882a593Smuzhiyun return ret;
180*4882a593Smuzhiyun st->config = ret;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun return 0;
183*4882a593Smuzhiyun }
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun /*
186*4882a593Smuzhiyun * ad799x_trigger_handler() bh of trigger launched polling to ring buffer
187*4882a593Smuzhiyun *
188*4882a593Smuzhiyun * Currently there is no option in this driver to disable the saving of
189*4882a593Smuzhiyun * timestamps within the ring.
190*4882a593Smuzhiyun **/
ad799x_trigger_handler(int irq,void * p)191*4882a593Smuzhiyun static irqreturn_t ad799x_trigger_handler(int irq, void *p)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun struct iio_poll_func *pf = p;
194*4882a593Smuzhiyun struct iio_dev *indio_dev = pf->indio_dev;
195*4882a593Smuzhiyun struct ad799x_state *st = iio_priv(indio_dev);
196*4882a593Smuzhiyun int b_sent;
197*4882a593Smuzhiyun u8 cmd;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun switch (st->id) {
200*4882a593Smuzhiyun case ad7991:
201*4882a593Smuzhiyun case ad7995:
202*4882a593Smuzhiyun case ad7999:
203*4882a593Smuzhiyun cmd = st->config |
204*4882a593Smuzhiyun (*indio_dev->active_scan_mask << AD799X_CHANNEL_SHIFT);
205*4882a593Smuzhiyun break;
206*4882a593Smuzhiyun case ad7992:
207*4882a593Smuzhiyun case ad7993:
208*4882a593Smuzhiyun case ad7994:
209*4882a593Smuzhiyun cmd = (*indio_dev->active_scan_mask << AD799X_CHANNEL_SHIFT) |
210*4882a593Smuzhiyun AD7998_CONV_RES_REG;
211*4882a593Smuzhiyun break;
212*4882a593Smuzhiyun case ad7997:
213*4882a593Smuzhiyun case ad7998:
214*4882a593Smuzhiyun cmd = AD7997_8_READ_SEQUENCE | AD7998_CONV_RES_REG;
215*4882a593Smuzhiyun break;
216*4882a593Smuzhiyun default:
217*4882a593Smuzhiyun cmd = 0;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun b_sent = i2c_smbus_read_i2c_block_data(st->client,
221*4882a593Smuzhiyun cmd, st->transfer_size, st->rx_buf);
222*4882a593Smuzhiyun if (b_sent < 0)
223*4882a593Smuzhiyun goto out;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
226*4882a593Smuzhiyun iio_get_time_ns(indio_dev));
227*4882a593Smuzhiyun out:
228*4882a593Smuzhiyun iio_trigger_notify_done(indio_dev->trig);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun return IRQ_HANDLED;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
ad799x_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)233*4882a593Smuzhiyun static int ad799x_update_scan_mode(struct iio_dev *indio_dev,
234*4882a593Smuzhiyun const unsigned long *scan_mask)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun struct ad799x_state *st = iio_priv(indio_dev);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun kfree(st->rx_buf);
239*4882a593Smuzhiyun st->rx_buf = kmalloc(indio_dev->scan_bytes, GFP_KERNEL);
240*4882a593Smuzhiyun if (!st->rx_buf)
241*4882a593Smuzhiyun return -ENOMEM;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun st->transfer_size = bitmap_weight(scan_mask, indio_dev->masklength) * 2;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun switch (st->id) {
246*4882a593Smuzhiyun case ad7992:
247*4882a593Smuzhiyun case ad7993:
248*4882a593Smuzhiyun case ad7994:
249*4882a593Smuzhiyun case ad7997:
250*4882a593Smuzhiyun case ad7998:
251*4882a593Smuzhiyun st->config &= ~(GENMASK(7, 0) << AD799X_CHANNEL_SHIFT);
252*4882a593Smuzhiyun st->config |= (*scan_mask << AD799X_CHANNEL_SHIFT);
253*4882a593Smuzhiyun return ad799x_write_config(st, st->config);
254*4882a593Smuzhiyun default:
255*4882a593Smuzhiyun return 0;
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
ad799x_scan_direct(struct ad799x_state * st,unsigned ch)259*4882a593Smuzhiyun static int ad799x_scan_direct(struct ad799x_state *st, unsigned ch)
260*4882a593Smuzhiyun {
261*4882a593Smuzhiyun u8 cmd;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun switch (st->id) {
264*4882a593Smuzhiyun case ad7991:
265*4882a593Smuzhiyun case ad7995:
266*4882a593Smuzhiyun case ad7999:
267*4882a593Smuzhiyun cmd = st->config | (BIT(ch) << AD799X_CHANNEL_SHIFT);
268*4882a593Smuzhiyun break;
269*4882a593Smuzhiyun case ad7992:
270*4882a593Smuzhiyun case ad7993:
271*4882a593Smuzhiyun case ad7994:
272*4882a593Smuzhiyun cmd = BIT(ch) << AD799X_CHANNEL_SHIFT;
273*4882a593Smuzhiyun break;
274*4882a593Smuzhiyun case ad7997:
275*4882a593Smuzhiyun case ad7998:
276*4882a593Smuzhiyun cmd = (ch << AD799X_CHANNEL_SHIFT) | AD7997_8_READ_SINGLE;
277*4882a593Smuzhiyun break;
278*4882a593Smuzhiyun default:
279*4882a593Smuzhiyun return -EINVAL;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun return i2c_smbus_read_word_swapped(st->client, cmd);
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
ad799x_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)285*4882a593Smuzhiyun static int ad799x_read_raw(struct iio_dev *indio_dev,
286*4882a593Smuzhiyun struct iio_chan_spec const *chan,
287*4882a593Smuzhiyun int *val,
288*4882a593Smuzhiyun int *val2,
289*4882a593Smuzhiyun long m)
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun int ret;
292*4882a593Smuzhiyun struct ad799x_state *st = iio_priv(indio_dev);
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun switch (m) {
295*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
296*4882a593Smuzhiyun ret = iio_device_claim_direct_mode(indio_dev);
297*4882a593Smuzhiyun if (ret)
298*4882a593Smuzhiyun return ret;
299*4882a593Smuzhiyun ret = ad799x_scan_direct(st, chan->scan_index);
300*4882a593Smuzhiyun iio_device_release_direct_mode(indio_dev);
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun if (ret < 0)
303*4882a593Smuzhiyun return ret;
304*4882a593Smuzhiyun *val = (ret >> chan->scan_type.shift) &
305*4882a593Smuzhiyun GENMASK(chan->scan_type.realbits - 1, 0);
306*4882a593Smuzhiyun return IIO_VAL_INT;
307*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
308*4882a593Smuzhiyun ret = regulator_get_voltage(st->vref);
309*4882a593Smuzhiyun if (ret < 0)
310*4882a593Smuzhiyun return ret;
311*4882a593Smuzhiyun *val = ret / 1000;
312*4882a593Smuzhiyun *val2 = chan->scan_type.realbits;
313*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL_LOG2;
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun return -EINVAL;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun static const unsigned int ad7998_frequencies[] = {
318*4882a593Smuzhiyun [AD7998_CYC_DIS] = 0,
319*4882a593Smuzhiyun [AD7998_CYC_TCONF_32] = 15625,
320*4882a593Smuzhiyun [AD7998_CYC_TCONF_64] = 7812,
321*4882a593Smuzhiyun [AD7998_CYC_TCONF_128] = 3906,
322*4882a593Smuzhiyun [AD7998_CYC_TCONF_512] = 976,
323*4882a593Smuzhiyun [AD7998_CYC_TCONF_1024] = 488,
324*4882a593Smuzhiyun [AD7998_CYC_TCONF_2048] = 244,
325*4882a593Smuzhiyun };
326*4882a593Smuzhiyun
ad799x_read_frequency(struct device * dev,struct device_attribute * attr,char * buf)327*4882a593Smuzhiyun static ssize_t ad799x_read_frequency(struct device *dev,
328*4882a593Smuzhiyun struct device_attribute *attr,
329*4882a593Smuzhiyun char *buf)
330*4882a593Smuzhiyun {
331*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_to_iio_dev(dev);
332*4882a593Smuzhiyun struct ad799x_state *st = iio_priv(indio_dev);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun int ret = i2c_smbus_read_byte_data(st->client, AD7998_CYCLE_TMR_REG);
335*4882a593Smuzhiyun if (ret < 0)
336*4882a593Smuzhiyun return ret;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun return sprintf(buf, "%u\n", ad7998_frequencies[ret & AD7998_CYC_MASK]);
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
ad799x_write_frequency(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)341*4882a593Smuzhiyun static ssize_t ad799x_write_frequency(struct device *dev,
342*4882a593Smuzhiyun struct device_attribute *attr,
343*4882a593Smuzhiyun const char *buf,
344*4882a593Smuzhiyun size_t len)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_to_iio_dev(dev);
347*4882a593Smuzhiyun struct ad799x_state *st = iio_priv(indio_dev);
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun long val;
350*4882a593Smuzhiyun int ret, i;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun ret = kstrtol(buf, 10, &val);
353*4882a593Smuzhiyun if (ret)
354*4882a593Smuzhiyun return ret;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun mutex_lock(&indio_dev->mlock);
357*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(st->client, AD7998_CYCLE_TMR_REG);
358*4882a593Smuzhiyun if (ret < 0)
359*4882a593Smuzhiyun goto error_ret_mutex;
360*4882a593Smuzhiyun /* Wipe the bits clean */
361*4882a593Smuzhiyun ret &= ~AD7998_CYC_MASK;
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(ad7998_frequencies); i++)
364*4882a593Smuzhiyun if (val == ad7998_frequencies[i])
365*4882a593Smuzhiyun break;
366*4882a593Smuzhiyun if (i == ARRAY_SIZE(ad7998_frequencies)) {
367*4882a593Smuzhiyun ret = -EINVAL;
368*4882a593Smuzhiyun goto error_ret_mutex;
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(st->client, AD7998_CYCLE_TMR_REG,
372*4882a593Smuzhiyun ret | i);
373*4882a593Smuzhiyun if (ret < 0)
374*4882a593Smuzhiyun goto error_ret_mutex;
375*4882a593Smuzhiyun ret = len;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun error_ret_mutex:
378*4882a593Smuzhiyun mutex_unlock(&indio_dev->mlock);
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun return ret;
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun
ad799x_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)383*4882a593Smuzhiyun static int ad799x_read_event_config(struct iio_dev *indio_dev,
384*4882a593Smuzhiyun const struct iio_chan_spec *chan,
385*4882a593Smuzhiyun enum iio_event_type type,
386*4882a593Smuzhiyun enum iio_event_direction dir)
387*4882a593Smuzhiyun {
388*4882a593Smuzhiyun struct ad799x_state *st = iio_priv(indio_dev);
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun if (!(st->config & AD7998_ALERT_EN))
391*4882a593Smuzhiyun return 0;
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun if ((st->config >> AD799X_CHANNEL_SHIFT) & BIT(chan->scan_index))
394*4882a593Smuzhiyun return 1;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun return 0;
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun
ad799x_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)399*4882a593Smuzhiyun static int ad799x_write_event_config(struct iio_dev *indio_dev,
400*4882a593Smuzhiyun const struct iio_chan_spec *chan,
401*4882a593Smuzhiyun enum iio_event_type type,
402*4882a593Smuzhiyun enum iio_event_direction dir,
403*4882a593Smuzhiyun int state)
404*4882a593Smuzhiyun {
405*4882a593Smuzhiyun struct ad799x_state *st = iio_priv(indio_dev);
406*4882a593Smuzhiyun int ret;
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun ret = iio_device_claim_direct_mode(indio_dev);
409*4882a593Smuzhiyun if (ret)
410*4882a593Smuzhiyun return ret;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun if (state)
413*4882a593Smuzhiyun st->config |= BIT(chan->scan_index) << AD799X_CHANNEL_SHIFT;
414*4882a593Smuzhiyun else
415*4882a593Smuzhiyun st->config &= ~(BIT(chan->scan_index) << AD799X_CHANNEL_SHIFT);
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun if (st->config >> AD799X_CHANNEL_SHIFT)
418*4882a593Smuzhiyun st->config |= AD7998_ALERT_EN;
419*4882a593Smuzhiyun else
420*4882a593Smuzhiyun st->config &= ~AD7998_ALERT_EN;
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun ret = ad799x_write_config(st, st->config);
423*4882a593Smuzhiyun iio_device_release_direct_mode(indio_dev);
424*4882a593Smuzhiyun return ret;
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun
ad799x_threshold_reg(const struct iio_chan_spec * chan,enum iio_event_direction dir,enum iio_event_info info)427*4882a593Smuzhiyun static unsigned int ad799x_threshold_reg(const struct iio_chan_spec *chan,
428*4882a593Smuzhiyun enum iio_event_direction dir,
429*4882a593Smuzhiyun enum iio_event_info info)
430*4882a593Smuzhiyun {
431*4882a593Smuzhiyun switch (info) {
432*4882a593Smuzhiyun case IIO_EV_INFO_VALUE:
433*4882a593Smuzhiyun if (dir == IIO_EV_DIR_FALLING)
434*4882a593Smuzhiyun return AD7998_DATALOW_REG(chan->channel);
435*4882a593Smuzhiyun else
436*4882a593Smuzhiyun return AD7998_DATAHIGH_REG(chan->channel);
437*4882a593Smuzhiyun case IIO_EV_INFO_HYSTERESIS:
438*4882a593Smuzhiyun return AD7998_HYST_REG(chan->channel);
439*4882a593Smuzhiyun default:
440*4882a593Smuzhiyun return -EINVAL;
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun return 0;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun
ad799x_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)446*4882a593Smuzhiyun static int ad799x_write_event_value(struct iio_dev *indio_dev,
447*4882a593Smuzhiyun const struct iio_chan_spec *chan,
448*4882a593Smuzhiyun enum iio_event_type type,
449*4882a593Smuzhiyun enum iio_event_direction dir,
450*4882a593Smuzhiyun enum iio_event_info info,
451*4882a593Smuzhiyun int val, int val2)
452*4882a593Smuzhiyun {
453*4882a593Smuzhiyun int ret;
454*4882a593Smuzhiyun struct ad799x_state *st = iio_priv(indio_dev);
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun if (val < 0 || val > GENMASK(chan->scan_type.realbits - 1, 0))
457*4882a593Smuzhiyun return -EINVAL;
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun mutex_lock(&indio_dev->mlock);
460*4882a593Smuzhiyun ret = i2c_smbus_write_word_swapped(st->client,
461*4882a593Smuzhiyun ad799x_threshold_reg(chan, dir, info),
462*4882a593Smuzhiyun val << chan->scan_type.shift);
463*4882a593Smuzhiyun mutex_unlock(&indio_dev->mlock);
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun return ret;
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun
ad799x_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)468*4882a593Smuzhiyun static int ad799x_read_event_value(struct iio_dev *indio_dev,
469*4882a593Smuzhiyun const struct iio_chan_spec *chan,
470*4882a593Smuzhiyun enum iio_event_type type,
471*4882a593Smuzhiyun enum iio_event_direction dir,
472*4882a593Smuzhiyun enum iio_event_info info,
473*4882a593Smuzhiyun int *val, int *val2)
474*4882a593Smuzhiyun {
475*4882a593Smuzhiyun int ret;
476*4882a593Smuzhiyun struct ad799x_state *st = iio_priv(indio_dev);
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun mutex_lock(&indio_dev->mlock);
479*4882a593Smuzhiyun ret = i2c_smbus_read_word_swapped(st->client,
480*4882a593Smuzhiyun ad799x_threshold_reg(chan, dir, info));
481*4882a593Smuzhiyun mutex_unlock(&indio_dev->mlock);
482*4882a593Smuzhiyun if (ret < 0)
483*4882a593Smuzhiyun return ret;
484*4882a593Smuzhiyun *val = (ret >> chan->scan_type.shift) &
485*4882a593Smuzhiyun GENMASK(chan->scan_type.realbits - 1, 0);
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun return IIO_VAL_INT;
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun
ad799x_event_handler(int irq,void * private)490*4882a593Smuzhiyun static irqreturn_t ad799x_event_handler(int irq, void *private)
491*4882a593Smuzhiyun {
492*4882a593Smuzhiyun struct iio_dev *indio_dev = private;
493*4882a593Smuzhiyun struct ad799x_state *st = iio_priv(private);
494*4882a593Smuzhiyun int i, ret;
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(st->client, AD7998_ALERT_STAT_REG);
497*4882a593Smuzhiyun if (ret <= 0)
498*4882a593Smuzhiyun goto done;
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun if (i2c_smbus_write_byte_data(st->client, AD7998_ALERT_STAT_REG,
501*4882a593Smuzhiyun AD7998_ALERT_STAT_CLEAR) < 0)
502*4882a593Smuzhiyun goto done;
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun for (i = 0; i < 8; i++) {
505*4882a593Smuzhiyun if (ret & BIT(i))
506*4882a593Smuzhiyun iio_push_event(indio_dev,
507*4882a593Smuzhiyun i & 0x1 ?
508*4882a593Smuzhiyun IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE,
509*4882a593Smuzhiyun (i >> 1),
510*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
511*4882a593Smuzhiyun IIO_EV_DIR_RISING) :
512*4882a593Smuzhiyun IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE,
513*4882a593Smuzhiyun (i >> 1),
514*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
515*4882a593Smuzhiyun IIO_EV_DIR_FALLING),
516*4882a593Smuzhiyun iio_get_time_ns(indio_dev));
517*4882a593Smuzhiyun }
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun done:
520*4882a593Smuzhiyun return IRQ_HANDLED;
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
524*4882a593Smuzhiyun ad799x_read_frequency,
525*4882a593Smuzhiyun ad799x_write_frequency);
526*4882a593Smuzhiyun static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("15625 7812 3906 1953 976 488 244 0");
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun static struct attribute *ad799x_event_attributes[] = {
529*4882a593Smuzhiyun &iio_dev_attr_sampling_frequency.dev_attr.attr,
530*4882a593Smuzhiyun &iio_const_attr_sampling_frequency_available.dev_attr.attr,
531*4882a593Smuzhiyun NULL,
532*4882a593Smuzhiyun };
533*4882a593Smuzhiyun
534*4882a593Smuzhiyun static const struct attribute_group ad799x_event_attrs_group = {
535*4882a593Smuzhiyun .attrs = ad799x_event_attributes,
536*4882a593Smuzhiyun };
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun static const struct iio_info ad7991_info = {
539*4882a593Smuzhiyun .read_raw = &ad799x_read_raw,
540*4882a593Smuzhiyun .update_scan_mode = ad799x_update_scan_mode,
541*4882a593Smuzhiyun };
542*4882a593Smuzhiyun
543*4882a593Smuzhiyun static const struct iio_info ad7993_4_7_8_noirq_info = {
544*4882a593Smuzhiyun .read_raw = &ad799x_read_raw,
545*4882a593Smuzhiyun .update_scan_mode = ad799x_update_scan_mode,
546*4882a593Smuzhiyun };
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun static const struct iio_info ad7993_4_7_8_irq_info = {
549*4882a593Smuzhiyun .read_raw = &ad799x_read_raw,
550*4882a593Smuzhiyun .event_attrs = &ad799x_event_attrs_group,
551*4882a593Smuzhiyun .read_event_config = &ad799x_read_event_config,
552*4882a593Smuzhiyun .write_event_config = &ad799x_write_event_config,
553*4882a593Smuzhiyun .read_event_value = &ad799x_read_event_value,
554*4882a593Smuzhiyun .write_event_value = &ad799x_write_event_value,
555*4882a593Smuzhiyun .update_scan_mode = ad799x_update_scan_mode,
556*4882a593Smuzhiyun };
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun static const struct iio_event_spec ad799x_events[] = {
559*4882a593Smuzhiyun {
560*4882a593Smuzhiyun .type = IIO_EV_TYPE_THRESH,
561*4882a593Smuzhiyun .dir = IIO_EV_DIR_RISING,
562*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_VALUE) |
563*4882a593Smuzhiyun BIT(IIO_EV_INFO_ENABLE),
564*4882a593Smuzhiyun }, {
565*4882a593Smuzhiyun .type = IIO_EV_TYPE_THRESH,
566*4882a593Smuzhiyun .dir = IIO_EV_DIR_FALLING,
567*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_VALUE) |
568*4882a593Smuzhiyun BIT(IIO_EV_INFO_ENABLE),
569*4882a593Smuzhiyun }, {
570*4882a593Smuzhiyun .type = IIO_EV_TYPE_THRESH,
571*4882a593Smuzhiyun .dir = IIO_EV_DIR_EITHER,
572*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_HYSTERESIS),
573*4882a593Smuzhiyun },
574*4882a593Smuzhiyun };
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun #define _AD799X_CHANNEL(_index, _realbits, _ev_spec, _num_ev_spec) { \
577*4882a593Smuzhiyun .type = IIO_VOLTAGE, \
578*4882a593Smuzhiyun .indexed = 1, \
579*4882a593Smuzhiyun .channel = (_index), \
580*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
581*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
582*4882a593Smuzhiyun .scan_index = (_index), \
583*4882a593Smuzhiyun .scan_type = { \
584*4882a593Smuzhiyun .sign = 'u', \
585*4882a593Smuzhiyun .realbits = (_realbits), \
586*4882a593Smuzhiyun .storagebits = 16, \
587*4882a593Smuzhiyun .shift = 12 - (_realbits), \
588*4882a593Smuzhiyun .endianness = IIO_BE, \
589*4882a593Smuzhiyun }, \
590*4882a593Smuzhiyun .event_spec = _ev_spec, \
591*4882a593Smuzhiyun .num_event_specs = _num_ev_spec, \
592*4882a593Smuzhiyun }
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun #define AD799X_CHANNEL(_index, _realbits) \
595*4882a593Smuzhiyun _AD799X_CHANNEL(_index, _realbits, NULL, 0)
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun #define AD799X_CHANNEL_WITH_EVENTS(_index, _realbits) \
598*4882a593Smuzhiyun _AD799X_CHANNEL(_index, _realbits, ad799x_events, \
599*4882a593Smuzhiyun ARRAY_SIZE(ad799x_events))
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun static const struct ad799x_chip_info ad799x_chip_info_tbl[] = {
602*4882a593Smuzhiyun [ad7991] = {
603*4882a593Smuzhiyun .num_channels = 5,
604*4882a593Smuzhiyun .noirq_config = {
605*4882a593Smuzhiyun .channel = {
606*4882a593Smuzhiyun AD799X_CHANNEL(0, 12),
607*4882a593Smuzhiyun AD799X_CHANNEL(1, 12),
608*4882a593Smuzhiyun AD799X_CHANNEL(2, 12),
609*4882a593Smuzhiyun AD799X_CHANNEL(3, 12),
610*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(4),
611*4882a593Smuzhiyun },
612*4882a593Smuzhiyun .info = &ad7991_info,
613*4882a593Smuzhiyun },
614*4882a593Smuzhiyun },
615*4882a593Smuzhiyun [ad7995] = {
616*4882a593Smuzhiyun .num_channels = 5,
617*4882a593Smuzhiyun .noirq_config = {
618*4882a593Smuzhiyun .channel = {
619*4882a593Smuzhiyun AD799X_CHANNEL(0, 10),
620*4882a593Smuzhiyun AD799X_CHANNEL(1, 10),
621*4882a593Smuzhiyun AD799X_CHANNEL(2, 10),
622*4882a593Smuzhiyun AD799X_CHANNEL(3, 10),
623*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(4),
624*4882a593Smuzhiyun },
625*4882a593Smuzhiyun .info = &ad7991_info,
626*4882a593Smuzhiyun },
627*4882a593Smuzhiyun },
628*4882a593Smuzhiyun [ad7999] = {
629*4882a593Smuzhiyun .num_channels = 5,
630*4882a593Smuzhiyun .noirq_config = {
631*4882a593Smuzhiyun .channel = {
632*4882a593Smuzhiyun AD799X_CHANNEL(0, 8),
633*4882a593Smuzhiyun AD799X_CHANNEL(1, 8),
634*4882a593Smuzhiyun AD799X_CHANNEL(2, 8),
635*4882a593Smuzhiyun AD799X_CHANNEL(3, 8),
636*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(4),
637*4882a593Smuzhiyun },
638*4882a593Smuzhiyun .info = &ad7991_info,
639*4882a593Smuzhiyun },
640*4882a593Smuzhiyun },
641*4882a593Smuzhiyun [ad7992] = {
642*4882a593Smuzhiyun .num_channels = 3,
643*4882a593Smuzhiyun .noirq_config = {
644*4882a593Smuzhiyun .channel = {
645*4882a593Smuzhiyun AD799X_CHANNEL(0, 12),
646*4882a593Smuzhiyun AD799X_CHANNEL(1, 12),
647*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(3),
648*4882a593Smuzhiyun },
649*4882a593Smuzhiyun .info = &ad7993_4_7_8_noirq_info,
650*4882a593Smuzhiyun },
651*4882a593Smuzhiyun .irq_config = {
652*4882a593Smuzhiyun .channel = {
653*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(0, 12),
654*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(1, 12),
655*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(3),
656*4882a593Smuzhiyun },
657*4882a593Smuzhiyun .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
658*4882a593Smuzhiyun .info = &ad7993_4_7_8_irq_info,
659*4882a593Smuzhiyun },
660*4882a593Smuzhiyun },
661*4882a593Smuzhiyun [ad7993] = {
662*4882a593Smuzhiyun .num_channels = 5,
663*4882a593Smuzhiyun .noirq_config = {
664*4882a593Smuzhiyun .channel = {
665*4882a593Smuzhiyun AD799X_CHANNEL(0, 10),
666*4882a593Smuzhiyun AD799X_CHANNEL(1, 10),
667*4882a593Smuzhiyun AD799X_CHANNEL(2, 10),
668*4882a593Smuzhiyun AD799X_CHANNEL(3, 10),
669*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(4),
670*4882a593Smuzhiyun },
671*4882a593Smuzhiyun .info = &ad7993_4_7_8_noirq_info,
672*4882a593Smuzhiyun },
673*4882a593Smuzhiyun .irq_config = {
674*4882a593Smuzhiyun .channel = {
675*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(0, 10),
676*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(1, 10),
677*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(2, 10),
678*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(3, 10),
679*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(4),
680*4882a593Smuzhiyun },
681*4882a593Smuzhiyun .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
682*4882a593Smuzhiyun .info = &ad7993_4_7_8_irq_info,
683*4882a593Smuzhiyun },
684*4882a593Smuzhiyun },
685*4882a593Smuzhiyun [ad7994] = {
686*4882a593Smuzhiyun .num_channels = 5,
687*4882a593Smuzhiyun .noirq_config = {
688*4882a593Smuzhiyun .channel = {
689*4882a593Smuzhiyun AD799X_CHANNEL(0, 12),
690*4882a593Smuzhiyun AD799X_CHANNEL(1, 12),
691*4882a593Smuzhiyun AD799X_CHANNEL(2, 12),
692*4882a593Smuzhiyun AD799X_CHANNEL(3, 12),
693*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(4),
694*4882a593Smuzhiyun },
695*4882a593Smuzhiyun .info = &ad7993_4_7_8_noirq_info,
696*4882a593Smuzhiyun },
697*4882a593Smuzhiyun .irq_config = {
698*4882a593Smuzhiyun .channel = {
699*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(0, 12),
700*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(1, 12),
701*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(2, 12),
702*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(3, 12),
703*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(4),
704*4882a593Smuzhiyun },
705*4882a593Smuzhiyun .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
706*4882a593Smuzhiyun .info = &ad7993_4_7_8_irq_info,
707*4882a593Smuzhiyun },
708*4882a593Smuzhiyun },
709*4882a593Smuzhiyun [ad7997] = {
710*4882a593Smuzhiyun .num_channels = 9,
711*4882a593Smuzhiyun .noirq_config = {
712*4882a593Smuzhiyun .channel = {
713*4882a593Smuzhiyun AD799X_CHANNEL(0, 10),
714*4882a593Smuzhiyun AD799X_CHANNEL(1, 10),
715*4882a593Smuzhiyun AD799X_CHANNEL(2, 10),
716*4882a593Smuzhiyun AD799X_CHANNEL(3, 10),
717*4882a593Smuzhiyun AD799X_CHANNEL(4, 10),
718*4882a593Smuzhiyun AD799X_CHANNEL(5, 10),
719*4882a593Smuzhiyun AD799X_CHANNEL(6, 10),
720*4882a593Smuzhiyun AD799X_CHANNEL(7, 10),
721*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(8),
722*4882a593Smuzhiyun },
723*4882a593Smuzhiyun .info = &ad7993_4_7_8_noirq_info,
724*4882a593Smuzhiyun },
725*4882a593Smuzhiyun .irq_config = {
726*4882a593Smuzhiyun .channel = {
727*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(0, 10),
728*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(1, 10),
729*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(2, 10),
730*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(3, 10),
731*4882a593Smuzhiyun AD799X_CHANNEL(4, 10),
732*4882a593Smuzhiyun AD799X_CHANNEL(5, 10),
733*4882a593Smuzhiyun AD799X_CHANNEL(6, 10),
734*4882a593Smuzhiyun AD799X_CHANNEL(7, 10),
735*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(8),
736*4882a593Smuzhiyun },
737*4882a593Smuzhiyun .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
738*4882a593Smuzhiyun .info = &ad7993_4_7_8_irq_info,
739*4882a593Smuzhiyun },
740*4882a593Smuzhiyun },
741*4882a593Smuzhiyun [ad7998] = {
742*4882a593Smuzhiyun .num_channels = 9,
743*4882a593Smuzhiyun .noirq_config = {
744*4882a593Smuzhiyun .channel = {
745*4882a593Smuzhiyun AD799X_CHANNEL(0, 12),
746*4882a593Smuzhiyun AD799X_CHANNEL(1, 12),
747*4882a593Smuzhiyun AD799X_CHANNEL(2, 12),
748*4882a593Smuzhiyun AD799X_CHANNEL(3, 12),
749*4882a593Smuzhiyun AD799X_CHANNEL(4, 12),
750*4882a593Smuzhiyun AD799X_CHANNEL(5, 12),
751*4882a593Smuzhiyun AD799X_CHANNEL(6, 12),
752*4882a593Smuzhiyun AD799X_CHANNEL(7, 12),
753*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(8),
754*4882a593Smuzhiyun },
755*4882a593Smuzhiyun .info = &ad7993_4_7_8_noirq_info,
756*4882a593Smuzhiyun },
757*4882a593Smuzhiyun .irq_config = {
758*4882a593Smuzhiyun .channel = {
759*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(0, 12),
760*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(1, 12),
761*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(2, 12),
762*4882a593Smuzhiyun AD799X_CHANNEL_WITH_EVENTS(3, 12),
763*4882a593Smuzhiyun AD799X_CHANNEL(4, 12),
764*4882a593Smuzhiyun AD799X_CHANNEL(5, 12),
765*4882a593Smuzhiyun AD799X_CHANNEL(6, 12),
766*4882a593Smuzhiyun AD799X_CHANNEL(7, 12),
767*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(8),
768*4882a593Smuzhiyun },
769*4882a593Smuzhiyun .default_config = AD7998_ALERT_EN | AD7998_BUSY_ALERT,
770*4882a593Smuzhiyun .info = &ad7993_4_7_8_irq_info,
771*4882a593Smuzhiyun },
772*4882a593Smuzhiyun },
773*4882a593Smuzhiyun };
774*4882a593Smuzhiyun
ad799x_probe(struct i2c_client * client,const struct i2c_device_id * id)775*4882a593Smuzhiyun static int ad799x_probe(struct i2c_client *client,
776*4882a593Smuzhiyun const struct i2c_device_id *id)
777*4882a593Smuzhiyun {
778*4882a593Smuzhiyun int ret;
779*4882a593Smuzhiyun struct ad799x_state *st;
780*4882a593Smuzhiyun struct iio_dev *indio_dev;
781*4882a593Smuzhiyun const struct ad799x_chip_info *chip_info =
782*4882a593Smuzhiyun &ad799x_chip_info_tbl[id->driver_data];
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
785*4882a593Smuzhiyun if (indio_dev == NULL)
786*4882a593Smuzhiyun return -ENOMEM;
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun st = iio_priv(indio_dev);
789*4882a593Smuzhiyun /* this is only used for device removal purposes */
790*4882a593Smuzhiyun i2c_set_clientdata(client, indio_dev);
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun st->id = id->driver_data;
793*4882a593Smuzhiyun if (client->irq > 0 && chip_info->irq_config.info)
794*4882a593Smuzhiyun st->chip_config = &chip_info->irq_config;
795*4882a593Smuzhiyun else
796*4882a593Smuzhiyun st->chip_config = &chip_info->noirq_config;
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun /* TODO: Add pdata options for filtering and bit delay */
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun st->reg = devm_regulator_get(&client->dev, "vcc");
801*4882a593Smuzhiyun if (IS_ERR(st->reg))
802*4882a593Smuzhiyun return PTR_ERR(st->reg);
803*4882a593Smuzhiyun ret = regulator_enable(st->reg);
804*4882a593Smuzhiyun if (ret)
805*4882a593Smuzhiyun return ret;
806*4882a593Smuzhiyun st->vref = devm_regulator_get(&client->dev, "vref");
807*4882a593Smuzhiyun if (IS_ERR(st->vref)) {
808*4882a593Smuzhiyun ret = PTR_ERR(st->vref);
809*4882a593Smuzhiyun goto error_disable_reg;
810*4882a593Smuzhiyun }
811*4882a593Smuzhiyun ret = regulator_enable(st->vref);
812*4882a593Smuzhiyun if (ret)
813*4882a593Smuzhiyun goto error_disable_reg;
814*4882a593Smuzhiyun
815*4882a593Smuzhiyun st->client = client;
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun indio_dev->name = id->name;
818*4882a593Smuzhiyun indio_dev->info = st->chip_config->info;
819*4882a593Smuzhiyun
820*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
821*4882a593Smuzhiyun indio_dev->channels = st->chip_config->channel;
822*4882a593Smuzhiyun indio_dev->num_channels = chip_info->num_channels;
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun ret = ad799x_update_config(st, st->chip_config->default_config);
825*4882a593Smuzhiyun if (ret)
826*4882a593Smuzhiyun goto error_disable_vref;
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun ret = iio_triggered_buffer_setup(indio_dev, NULL,
829*4882a593Smuzhiyun &ad799x_trigger_handler, NULL);
830*4882a593Smuzhiyun if (ret)
831*4882a593Smuzhiyun goto error_disable_vref;
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun if (client->irq > 0) {
834*4882a593Smuzhiyun ret = devm_request_threaded_irq(&client->dev,
835*4882a593Smuzhiyun client->irq,
836*4882a593Smuzhiyun NULL,
837*4882a593Smuzhiyun ad799x_event_handler,
838*4882a593Smuzhiyun IRQF_TRIGGER_FALLING |
839*4882a593Smuzhiyun IRQF_ONESHOT,
840*4882a593Smuzhiyun client->name,
841*4882a593Smuzhiyun indio_dev);
842*4882a593Smuzhiyun if (ret)
843*4882a593Smuzhiyun goto error_cleanup_ring;
844*4882a593Smuzhiyun }
845*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
846*4882a593Smuzhiyun if (ret)
847*4882a593Smuzhiyun goto error_cleanup_ring;
848*4882a593Smuzhiyun
849*4882a593Smuzhiyun return 0;
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun error_cleanup_ring:
852*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
853*4882a593Smuzhiyun error_disable_vref:
854*4882a593Smuzhiyun regulator_disable(st->vref);
855*4882a593Smuzhiyun error_disable_reg:
856*4882a593Smuzhiyun regulator_disable(st->reg);
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun return ret;
859*4882a593Smuzhiyun }
860*4882a593Smuzhiyun
ad799x_remove(struct i2c_client * client)861*4882a593Smuzhiyun static int ad799x_remove(struct i2c_client *client)
862*4882a593Smuzhiyun {
863*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(client);
864*4882a593Smuzhiyun struct ad799x_state *st = iio_priv(indio_dev);
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun iio_device_unregister(indio_dev);
867*4882a593Smuzhiyun
868*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
869*4882a593Smuzhiyun regulator_disable(st->vref);
870*4882a593Smuzhiyun regulator_disable(st->reg);
871*4882a593Smuzhiyun kfree(st->rx_buf);
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun return 0;
874*4882a593Smuzhiyun }
875*4882a593Smuzhiyun
ad799x_suspend(struct device * dev)876*4882a593Smuzhiyun static int __maybe_unused ad799x_suspend(struct device *dev)
877*4882a593Smuzhiyun {
878*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
879*4882a593Smuzhiyun struct ad799x_state *st = iio_priv(indio_dev);
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun regulator_disable(st->vref);
882*4882a593Smuzhiyun regulator_disable(st->reg);
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun return 0;
885*4882a593Smuzhiyun }
886*4882a593Smuzhiyun
ad799x_resume(struct device * dev)887*4882a593Smuzhiyun static int __maybe_unused ad799x_resume(struct device *dev)
888*4882a593Smuzhiyun {
889*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
890*4882a593Smuzhiyun struct ad799x_state *st = iio_priv(indio_dev);
891*4882a593Smuzhiyun int ret;
892*4882a593Smuzhiyun
893*4882a593Smuzhiyun ret = regulator_enable(st->reg);
894*4882a593Smuzhiyun if (ret) {
895*4882a593Smuzhiyun dev_err(dev, "Unable to enable vcc regulator\n");
896*4882a593Smuzhiyun return ret;
897*4882a593Smuzhiyun }
898*4882a593Smuzhiyun ret = regulator_enable(st->vref);
899*4882a593Smuzhiyun if (ret) {
900*4882a593Smuzhiyun regulator_disable(st->reg);
901*4882a593Smuzhiyun dev_err(dev, "Unable to enable vref regulator\n");
902*4882a593Smuzhiyun return ret;
903*4882a593Smuzhiyun }
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun /* resync config */
906*4882a593Smuzhiyun ret = ad799x_update_config(st, st->config);
907*4882a593Smuzhiyun if (ret) {
908*4882a593Smuzhiyun regulator_disable(st->vref);
909*4882a593Smuzhiyun regulator_disable(st->reg);
910*4882a593Smuzhiyun return ret;
911*4882a593Smuzhiyun }
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun return 0;
914*4882a593Smuzhiyun }
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(ad799x_pm_ops, ad799x_suspend, ad799x_resume);
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun static const struct i2c_device_id ad799x_id[] = {
919*4882a593Smuzhiyun { "ad7991", ad7991 },
920*4882a593Smuzhiyun { "ad7995", ad7995 },
921*4882a593Smuzhiyun { "ad7999", ad7999 },
922*4882a593Smuzhiyun { "ad7992", ad7992 },
923*4882a593Smuzhiyun { "ad7993", ad7993 },
924*4882a593Smuzhiyun { "ad7994", ad7994 },
925*4882a593Smuzhiyun { "ad7997", ad7997 },
926*4882a593Smuzhiyun { "ad7998", ad7998 },
927*4882a593Smuzhiyun {}
928*4882a593Smuzhiyun };
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, ad799x_id);
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun static struct i2c_driver ad799x_driver = {
933*4882a593Smuzhiyun .driver = {
934*4882a593Smuzhiyun .name = "ad799x",
935*4882a593Smuzhiyun .pm = &ad799x_pm_ops,
936*4882a593Smuzhiyun },
937*4882a593Smuzhiyun .probe = ad799x_probe,
938*4882a593Smuzhiyun .remove = ad799x_remove,
939*4882a593Smuzhiyun .id_table = ad799x_id,
940*4882a593Smuzhiyun };
941*4882a593Smuzhiyun module_i2c_driver(ad799x_driver);
942*4882a593Smuzhiyun
943*4882a593Smuzhiyun MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
944*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices AD799x ADC");
945*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
946