1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * AD7887 SPI ADC driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2010-2011 Analog Devices Inc.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/device.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun #include <linux/sysfs.h>
12*4882a593Smuzhiyun #include <linux/spi/spi.h>
13*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
14*4882a593Smuzhiyun #include <linux/err.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/interrupt.h>
17*4882a593Smuzhiyun #include <linux/bitops.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include <linux/iio/iio.h>
20*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
21*4882a593Smuzhiyun #include <linux/iio/buffer.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
24*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include <linux/platform_data/ad7887.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define AD7887_REF_DIS BIT(5) /* on-chip reference disable */
29*4882a593Smuzhiyun #define AD7887_DUAL BIT(4) /* dual-channel mode */
30*4882a593Smuzhiyun #define AD7887_CH_AIN1 BIT(3) /* convert on channel 1, DUAL=1 */
31*4882a593Smuzhiyun #define AD7887_CH_AIN0 0 /* convert on channel 0, DUAL=0,1 */
32*4882a593Smuzhiyun #define AD7887_PM_MODE1 0 /* CS based shutdown */
33*4882a593Smuzhiyun #define AD7887_PM_MODE2 1 /* full on */
34*4882a593Smuzhiyun #define AD7887_PM_MODE3 2 /* auto shutdown after conversion */
35*4882a593Smuzhiyun #define AD7887_PM_MODE4 3 /* standby mode */
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun enum ad7887_channels {
38*4882a593Smuzhiyun AD7887_CH0,
39*4882a593Smuzhiyun AD7887_CH0_CH1,
40*4882a593Smuzhiyun AD7887_CH1,
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /**
44*4882a593Smuzhiyun * struct ad7887_chip_info - chip specifc information
45*4882a593Smuzhiyun * @int_vref_mv: the internal reference voltage
46*4882a593Smuzhiyun * @channels: channels specification
47*4882a593Smuzhiyun * @num_channels: number of channels
48*4882a593Smuzhiyun * @dual_channels: channels specification in dual mode
49*4882a593Smuzhiyun * @num_dual_channels: number of channels in dual mode
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun struct ad7887_chip_info {
52*4882a593Smuzhiyun u16 int_vref_mv;
53*4882a593Smuzhiyun const struct iio_chan_spec *channels;
54*4882a593Smuzhiyun unsigned int num_channels;
55*4882a593Smuzhiyun const struct iio_chan_spec *dual_channels;
56*4882a593Smuzhiyun unsigned int num_dual_channels;
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun struct ad7887_state {
60*4882a593Smuzhiyun struct spi_device *spi;
61*4882a593Smuzhiyun const struct ad7887_chip_info *chip_info;
62*4882a593Smuzhiyun struct regulator *reg;
63*4882a593Smuzhiyun struct spi_transfer xfer[4];
64*4882a593Smuzhiyun struct spi_message msg[3];
65*4882a593Smuzhiyun struct spi_message *ring_msg;
66*4882a593Smuzhiyun unsigned char tx_cmd_buf[4];
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /*
69*4882a593Smuzhiyun * DMA (thus cache coherency maintenance) requires the
70*4882a593Smuzhiyun * transfer buffers to live in their own cache lines.
71*4882a593Smuzhiyun * Buffer needs to be large enough to hold two 16 bit samples and a
72*4882a593Smuzhiyun * 64 bit aligned 64 bit timestamp.
73*4882a593Smuzhiyun */
74*4882a593Smuzhiyun unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)]
75*4882a593Smuzhiyun ____cacheline_aligned;
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun enum ad7887_supported_device_ids {
79*4882a593Smuzhiyun ID_AD7887
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
ad7887_ring_preenable(struct iio_dev * indio_dev)82*4882a593Smuzhiyun static int ad7887_ring_preenable(struct iio_dev *indio_dev)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun struct ad7887_state *st = iio_priv(indio_dev);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* We know this is a single long so can 'cheat' */
87*4882a593Smuzhiyun switch (*indio_dev->active_scan_mask) {
88*4882a593Smuzhiyun case (1 << 0):
89*4882a593Smuzhiyun st->ring_msg = &st->msg[AD7887_CH0];
90*4882a593Smuzhiyun break;
91*4882a593Smuzhiyun case (1 << 1):
92*4882a593Smuzhiyun st->ring_msg = &st->msg[AD7887_CH1];
93*4882a593Smuzhiyun /* Dummy read: push CH1 setting down to hardware */
94*4882a593Smuzhiyun spi_sync(st->spi, st->ring_msg);
95*4882a593Smuzhiyun break;
96*4882a593Smuzhiyun case ((1 << 1) | (1 << 0)):
97*4882a593Smuzhiyun st->ring_msg = &st->msg[AD7887_CH0_CH1];
98*4882a593Smuzhiyun break;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun return 0;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
ad7887_ring_postdisable(struct iio_dev * indio_dev)104*4882a593Smuzhiyun static int ad7887_ring_postdisable(struct iio_dev *indio_dev)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun struct ad7887_state *st = iio_priv(indio_dev);
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /* dummy read: restore default CH0 settin */
109*4882a593Smuzhiyun return spi_sync(st->spi, &st->msg[AD7887_CH0]);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /*
113*4882a593Smuzhiyun * ad7887_trigger_handler() bh of trigger launched polling to ring buffer
114*4882a593Smuzhiyun *
115*4882a593Smuzhiyun * Currently there is no option in this driver to disable the saving of
116*4882a593Smuzhiyun * timestamps within the ring.
117*4882a593Smuzhiyun **/
ad7887_trigger_handler(int irq,void * p)118*4882a593Smuzhiyun static irqreturn_t ad7887_trigger_handler(int irq, void *p)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun struct iio_poll_func *pf = p;
121*4882a593Smuzhiyun struct iio_dev *indio_dev = pf->indio_dev;
122*4882a593Smuzhiyun struct ad7887_state *st = iio_priv(indio_dev);
123*4882a593Smuzhiyun int b_sent;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun b_sent = spi_sync(st->spi, st->ring_msg);
126*4882a593Smuzhiyun if (b_sent)
127*4882a593Smuzhiyun goto done;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun iio_push_to_buffers_with_timestamp(indio_dev, st->data,
130*4882a593Smuzhiyun iio_get_time_ns(indio_dev));
131*4882a593Smuzhiyun done:
132*4882a593Smuzhiyun iio_trigger_notify_done(indio_dev->trig);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun return IRQ_HANDLED;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun static const struct iio_buffer_setup_ops ad7887_ring_setup_ops = {
138*4882a593Smuzhiyun .preenable = &ad7887_ring_preenable,
139*4882a593Smuzhiyun .postdisable = &ad7887_ring_postdisable,
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun
ad7887_scan_direct(struct ad7887_state * st,unsigned ch)142*4882a593Smuzhiyun static int ad7887_scan_direct(struct ad7887_state *st, unsigned ch)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun int ret = spi_sync(st->spi, &st->msg[ch]);
145*4882a593Smuzhiyun if (ret)
146*4882a593Smuzhiyun return ret;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun return (st->data[(ch * 2)] << 8) | st->data[(ch * 2) + 1];
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
ad7887_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)151*4882a593Smuzhiyun static int ad7887_read_raw(struct iio_dev *indio_dev,
152*4882a593Smuzhiyun struct iio_chan_spec const *chan,
153*4882a593Smuzhiyun int *val,
154*4882a593Smuzhiyun int *val2,
155*4882a593Smuzhiyun long m)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun int ret;
158*4882a593Smuzhiyun struct ad7887_state *st = iio_priv(indio_dev);
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun switch (m) {
161*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
162*4882a593Smuzhiyun ret = iio_device_claim_direct_mode(indio_dev);
163*4882a593Smuzhiyun if (ret)
164*4882a593Smuzhiyun return ret;
165*4882a593Smuzhiyun ret = ad7887_scan_direct(st, chan->address);
166*4882a593Smuzhiyun iio_device_release_direct_mode(indio_dev);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun if (ret < 0)
169*4882a593Smuzhiyun return ret;
170*4882a593Smuzhiyun *val = ret >> chan->scan_type.shift;
171*4882a593Smuzhiyun *val &= GENMASK(chan->scan_type.realbits - 1, 0);
172*4882a593Smuzhiyun return IIO_VAL_INT;
173*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
174*4882a593Smuzhiyun if (st->reg) {
175*4882a593Smuzhiyun *val = regulator_get_voltage(st->reg);
176*4882a593Smuzhiyun if (*val < 0)
177*4882a593Smuzhiyun return *val;
178*4882a593Smuzhiyun *val /= 1000;
179*4882a593Smuzhiyun } else {
180*4882a593Smuzhiyun *val = st->chip_info->int_vref_mv;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun *val2 = chan->scan_type.realbits;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL_LOG2;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun return -EINVAL;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun #define AD7887_CHANNEL(x) { \
191*4882a593Smuzhiyun .type = IIO_VOLTAGE, \
192*4882a593Smuzhiyun .indexed = 1, \
193*4882a593Smuzhiyun .channel = (x), \
194*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
195*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
196*4882a593Smuzhiyun .address = (x), \
197*4882a593Smuzhiyun .scan_index = (x), \
198*4882a593Smuzhiyun .scan_type = { \
199*4882a593Smuzhiyun .sign = 'u', \
200*4882a593Smuzhiyun .realbits = 12, \
201*4882a593Smuzhiyun .storagebits = 16, \
202*4882a593Smuzhiyun .shift = 0, \
203*4882a593Smuzhiyun .endianness = IIO_BE, \
204*4882a593Smuzhiyun }, \
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun static const struct iio_chan_spec ad7887_channels[] = {
208*4882a593Smuzhiyun AD7887_CHANNEL(0),
209*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(1),
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun static const struct iio_chan_spec ad7887_dual_channels[] = {
213*4882a593Smuzhiyun AD7887_CHANNEL(0),
214*4882a593Smuzhiyun AD7887_CHANNEL(1),
215*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(2),
216*4882a593Smuzhiyun };
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun static const struct ad7887_chip_info ad7887_chip_info_tbl[] = {
219*4882a593Smuzhiyun /*
220*4882a593Smuzhiyun * More devices added in future
221*4882a593Smuzhiyun */
222*4882a593Smuzhiyun [ID_AD7887] = {
223*4882a593Smuzhiyun .channels = ad7887_channels,
224*4882a593Smuzhiyun .num_channels = ARRAY_SIZE(ad7887_channels),
225*4882a593Smuzhiyun .dual_channels = ad7887_dual_channels,
226*4882a593Smuzhiyun .num_dual_channels = ARRAY_SIZE(ad7887_dual_channels),
227*4882a593Smuzhiyun .int_vref_mv = 2500,
228*4882a593Smuzhiyun },
229*4882a593Smuzhiyun };
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun static const struct iio_info ad7887_info = {
232*4882a593Smuzhiyun .read_raw = &ad7887_read_raw,
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun
ad7887_probe(struct spi_device * spi)235*4882a593Smuzhiyun static int ad7887_probe(struct spi_device *spi)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun struct ad7887_platform_data *pdata = spi->dev.platform_data;
238*4882a593Smuzhiyun struct ad7887_state *st;
239*4882a593Smuzhiyun struct iio_dev *indio_dev;
240*4882a593Smuzhiyun uint8_t mode;
241*4882a593Smuzhiyun int ret;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
244*4882a593Smuzhiyun if (indio_dev == NULL)
245*4882a593Smuzhiyun return -ENOMEM;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun st = iio_priv(indio_dev);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun if (!pdata || !pdata->use_onchip_ref) {
250*4882a593Smuzhiyun st->reg = devm_regulator_get(&spi->dev, "vref");
251*4882a593Smuzhiyun if (IS_ERR(st->reg))
252*4882a593Smuzhiyun return PTR_ERR(st->reg);
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun ret = regulator_enable(st->reg);
255*4882a593Smuzhiyun if (ret)
256*4882a593Smuzhiyun return ret;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun st->chip_info =
260*4882a593Smuzhiyun &ad7887_chip_info_tbl[spi_get_device_id(spi)->driver_data];
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun spi_set_drvdata(spi, indio_dev);
263*4882a593Smuzhiyun st->spi = spi;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun indio_dev->name = spi_get_device_id(spi)->name;
266*4882a593Smuzhiyun indio_dev->info = &ad7887_info;
267*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun /* Setup default message */
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun mode = AD7887_PM_MODE4;
272*4882a593Smuzhiyun if (!pdata || !pdata->use_onchip_ref)
273*4882a593Smuzhiyun mode |= AD7887_REF_DIS;
274*4882a593Smuzhiyun if (pdata && pdata->en_dual)
275*4882a593Smuzhiyun mode |= AD7887_DUAL;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun st->tx_cmd_buf[0] = AD7887_CH_AIN0 | mode;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun st->xfer[0].rx_buf = &st->data[0];
280*4882a593Smuzhiyun st->xfer[0].tx_buf = &st->tx_cmd_buf[0];
281*4882a593Smuzhiyun st->xfer[0].len = 2;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun spi_message_init(&st->msg[AD7887_CH0]);
284*4882a593Smuzhiyun spi_message_add_tail(&st->xfer[0], &st->msg[AD7887_CH0]);
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun if (pdata && pdata->en_dual) {
287*4882a593Smuzhiyun st->tx_cmd_buf[2] = AD7887_CH_AIN1 | mode;
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun st->xfer[1].rx_buf = &st->data[0];
290*4882a593Smuzhiyun st->xfer[1].tx_buf = &st->tx_cmd_buf[2];
291*4882a593Smuzhiyun st->xfer[1].len = 2;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun st->xfer[2].rx_buf = &st->data[2];
294*4882a593Smuzhiyun st->xfer[2].tx_buf = &st->tx_cmd_buf[0];
295*4882a593Smuzhiyun st->xfer[2].len = 2;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun spi_message_init(&st->msg[AD7887_CH0_CH1]);
298*4882a593Smuzhiyun spi_message_add_tail(&st->xfer[1], &st->msg[AD7887_CH0_CH1]);
299*4882a593Smuzhiyun spi_message_add_tail(&st->xfer[2], &st->msg[AD7887_CH0_CH1]);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun st->xfer[3].rx_buf = &st->data[2];
302*4882a593Smuzhiyun st->xfer[3].tx_buf = &st->tx_cmd_buf[2];
303*4882a593Smuzhiyun st->xfer[3].len = 2;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun spi_message_init(&st->msg[AD7887_CH1]);
306*4882a593Smuzhiyun spi_message_add_tail(&st->xfer[3], &st->msg[AD7887_CH1]);
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun indio_dev->channels = st->chip_info->dual_channels;
309*4882a593Smuzhiyun indio_dev->num_channels = st->chip_info->num_dual_channels;
310*4882a593Smuzhiyun } else {
311*4882a593Smuzhiyun indio_dev->channels = st->chip_info->channels;
312*4882a593Smuzhiyun indio_dev->num_channels = st->chip_info->num_channels;
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
316*4882a593Smuzhiyun &ad7887_trigger_handler, &ad7887_ring_setup_ops);
317*4882a593Smuzhiyun if (ret)
318*4882a593Smuzhiyun goto error_disable_reg;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
321*4882a593Smuzhiyun if (ret)
322*4882a593Smuzhiyun goto error_unregister_ring;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun return 0;
325*4882a593Smuzhiyun error_unregister_ring:
326*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
327*4882a593Smuzhiyun error_disable_reg:
328*4882a593Smuzhiyun if (st->reg)
329*4882a593Smuzhiyun regulator_disable(st->reg);
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun return ret;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
ad7887_remove(struct spi_device * spi)334*4882a593Smuzhiyun static int ad7887_remove(struct spi_device *spi)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun struct iio_dev *indio_dev = spi_get_drvdata(spi);
337*4882a593Smuzhiyun struct ad7887_state *st = iio_priv(indio_dev);
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun iio_device_unregister(indio_dev);
340*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
341*4882a593Smuzhiyun if (st->reg)
342*4882a593Smuzhiyun regulator_disable(st->reg);
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun return 0;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun static const struct spi_device_id ad7887_id[] = {
348*4882a593Smuzhiyun {"ad7887", ID_AD7887},
349*4882a593Smuzhiyun {}
350*4882a593Smuzhiyun };
351*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ad7887_id);
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun static struct spi_driver ad7887_driver = {
354*4882a593Smuzhiyun .driver = {
355*4882a593Smuzhiyun .name = "ad7887",
356*4882a593Smuzhiyun },
357*4882a593Smuzhiyun .probe = ad7887_probe,
358*4882a593Smuzhiyun .remove = ad7887_remove,
359*4882a593Smuzhiyun .id_table = ad7887_id,
360*4882a593Smuzhiyun };
361*4882a593Smuzhiyun module_spi_driver(ad7887_driver);
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
364*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices AD7887 ADC");
365*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
366