xref: /OK3568_Linux_fs/kernel/drivers/iio/adc/ad7791.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * AD7787/AD7788/AD7789/AD7790/AD7791 SPI ADC driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2012 Analog Devices Inc.
6*4882a593Smuzhiyun  *  Author: Lars-Peter Clausen <lars@metafoo.de>
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun #include <linux/sysfs.h>
14*4882a593Smuzhiyun #include <linux/spi/spi.h>
15*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
16*4882a593Smuzhiyun #include <linux/err.h>
17*4882a593Smuzhiyun #include <linux/sched.h>
18*4882a593Smuzhiyun #include <linux/delay.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #include <linux/iio/iio.h>
22*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
23*4882a593Smuzhiyun #include <linux/iio/buffer.h>
24*4882a593Smuzhiyun #include <linux/iio/trigger.h>
25*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
26*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
27*4882a593Smuzhiyun #include <linux/iio/adc/ad_sigma_delta.h>
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #include <linux/platform_data/ad7791.h>
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define AD7791_REG_COMM			0x0 /* For writes */
32*4882a593Smuzhiyun #define AD7791_REG_STATUS		0x0 /* For reads */
33*4882a593Smuzhiyun #define AD7791_REG_MODE			0x1
34*4882a593Smuzhiyun #define AD7791_REG_FILTER		0x2
35*4882a593Smuzhiyun #define AD7791_REG_DATA			0x3
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define AD7791_MODE_CONTINUOUS		0x00
38*4882a593Smuzhiyun #define AD7791_MODE_SINGLE		0x02
39*4882a593Smuzhiyun #define AD7791_MODE_POWERDOWN		0x03
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define AD7791_CH_AIN1P_AIN1N		0x00
42*4882a593Smuzhiyun #define AD7791_CH_AIN2			0x01
43*4882a593Smuzhiyun #define AD7791_CH_AIN1N_AIN1N		0x02
44*4882a593Smuzhiyun #define AD7791_CH_AVDD_MONITOR		0x03
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define AD7791_FILTER_CLK_DIV_1		(0x0 << 4)
47*4882a593Smuzhiyun #define AD7791_FILTER_CLK_DIV_2		(0x1 << 4)
48*4882a593Smuzhiyun #define AD7791_FILTER_CLK_DIV_4		(0x2 << 4)
49*4882a593Smuzhiyun #define AD7791_FILTER_CLK_DIV_8		(0x3 << 4)
50*4882a593Smuzhiyun #define AD7791_FILTER_CLK_MASK		(0x3 << 4)
51*4882a593Smuzhiyun #define AD7791_FILTER_RATE_120		0x0
52*4882a593Smuzhiyun #define AD7791_FILTER_RATE_100		0x1
53*4882a593Smuzhiyun #define AD7791_FILTER_RATE_33_3		0x2
54*4882a593Smuzhiyun #define AD7791_FILTER_RATE_20		0x3
55*4882a593Smuzhiyun #define AD7791_FILTER_RATE_16_6		0x4
56*4882a593Smuzhiyun #define AD7791_FILTER_RATE_16_7		0x5
57*4882a593Smuzhiyun #define AD7791_FILTER_RATE_13_3		0x6
58*4882a593Smuzhiyun #define AD7791_FILTER_RATE_9_5		0x7
59*4882a593Smuzhiyun #define AD7791_FILTER_RATE_MASK		0x7
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun #define AD7791_MODE_BUFFER		BIT(1)
62*4882a593Smuzhiyun #define AD7791_MODE_UNIPOLAR		BIT(2)
63*4882a593Smuzhiyun #define AD7791_MODE_BURNOUT		BIT(3)
64*4882a593Smuzhiyun #define AD7791_MODE_SEL_MASK		(0x3 << 6)
65*4882a593Smuzhiyun #define AD7791_MODE_SEL(x)		((x) << 6)
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define __AD7991_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
68*4882a593Smuzhiyun 	_storagebits, _shift, _extend_name, _type, _mask_all) \
69*4882a593Smuzhiyun 	{ \
70*4882a593Smuzhiyun 		.type = (_type), \
71*4882a593Smuzhiyun 		.differential = (_channel2 == -1 ? 0 : 1), \
72*4882a593Smuzhiyun 		.indexed = 1, \
73*4882a593Smuzhiyun 		.channel = (_channel1), \
74*4882a593Smuzhiyun 		.channel2 = (_channel2), \
75*4882a593Smuzhiyun 		.address = (_address), \
76*4882a593Smuzhiyun 		.extend_name = (_extend_name), \
77*4882a593Smuzhiyun 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
78*4882a593Smuzhiyun 			BIT(IIO_CHAN_INFO_OFFSET), \
79*4882a593Smuzhiyun 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
80*4882a593Smuzhiyun 		.info_mask_shared_by_all = _mask_all, \
81*4882a593Smuzhiyun 		.scan_index = (_si), \
82*4882a593Smuzhiyun 		.scan_type = { \
83*4882a593Smuzhiyun 			.sign = 'u', \
84*4882a593Smuzhiyun 			.realbits = (_bits), \
85*4882a593Smuzhiyun 			.storagebits = (_storagebits), \
86*4882a593Smuzhiyun 			.shift = (_shift), \
87*4882a593Smuzhiyun 			.endianness = IIO_BE, \
88*4882a593Smuzhiyun 		}, \
89*4882a593Smuzhiyun 	}
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun #define AD7991_SHORTED_CHANNEL(_si, _channel, _address, _bits, \
92*4882a593Smuzhiyun 	_storagebits, _shift) \
93*4882a593Smuzhiyun 	__AD7991_CHANNEL(_si, _channel, _channel, _address, _bits, \
94*4882a593Smuzhiyun 		_storagebits, _shift, "shorted", IIO_VOLTAGE, \
95*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_SAMP_FREQ))
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun #define AD7991_CHANNEL(_si, _channel, _address, _bits, \
98*4882a593Smuzhiyun 	_storagebits, _shift) \
99*4882a593Smuzhiyun 	__AD7991_CHANNEL(_si, _channel, -1, _address, _bits, \
100*4882a593Smuzhiyun 		_storagebits, _shift, NULL, IIO_VOLTAGE, \
101*4882a593Smuzhiyun 		 BIT(IIO_CHAN_INFO_SAMP_FREQ))
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun #define AD7991_DIFF_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
104*4882a593Smuzhiyun 	_storagebits, _shift) \
105*4882a593Smuzhiyun 	__AD7991_CHANNEL(_si, _channel1, _channel2, _address, _bits, \
106*4882a593Smuzhiyun 		_storagebits, _shift, NULL, IIO_VOLTAGE, \
107*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_SAMP_FREQ))
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun #define AD7991_SUPPLY_CHANNEL(_si, _channel, _address, _bits, _storagebits, \
110*4882a593Smuzhiyun 	_shift) \
111*4882a593Smuzhiyun 	__AD7991_CHANNEL(_si, _channel, -1, _address, _bits, \
112*4882a593Smuzhiyun 		_storagebits, _shift, "supply", IIO_VOLTAGE, \
113*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_SAMP_FREQ))
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun #define DECLARE_AD7787_CHANNELS(name, bits, storagebits) \
116*4882a593Smuzhiyun const struct iio_chan_spec name[] = { \
117*4882a593Smuzhiyun 	AD7991_DIFF_CHANNEL(0, 0, 0, AD7791_CH_AIN1P_AIN1N, \
118*4882a593Smuzhiyun 		(bits), (storagebits), 0), \
119*4882a593Smuzhiyun 	AD7991_CHANNEL(1, 1, AD7791_CH_AIN2, (bits), (storagebits), 0), \
120*4882a593Smuzhiyun 	AD7991_SHORTED_CHANNEL(2, 0, AD7791_CH_AIN1N_AIN1N, \
121*4882a593Smuzhiyun 		(bits), (storagebits), 0), \
122*4882a593Smuzhiyun 	AD7991_SUPPLY_CHANNEL(3, 2, AD7791_CH_AVDD_MONITOR,  \
123*4882a593Smuzhiyun 		(bits), (storagebits), 0), \
124*4882a593Smuzhiyun 	IIO_CHAN_SOFT_TIMESTAMP(4), \
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun #define DECLARE_AD7791_CHANNELS(name, bits, storagebits) \
128*4882a593Smuzhiyun const struct iio_chan_spec name[] = { \
129*4882a593Smuzhiyun 	AD7991_DIFF_CHANNEL(0, 0, 0, AD7791_CH_AIN1P_AIN1N, \
130*4882a593Smuzhiyun 		(bits), (storagebits), 0), \
131*4882a593Smuzhiyun 	AD7991_SHORTED_CHANNEL(1, 0, AD7791_CH_AIN1N_AIN1N, \
132*4882a593Smuzhiyun 		(bits), (storagebits), 0), \
133*4882a593Smuzhiyun 	AD7991_SUPPLY_CHANNEL(2, 1, AD7791_CH_AVDD_MONITOR, \
134*4882a593Smuzhiyun 		(bits), (storagebits), 0), \
135*4882a593Smuzhiyun 	IIO_CHAN_SOFT_TIMESTAMP(3), \
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun static DECLARE_AD7787_CHANNELS(ad7787_channels, 24, 32);
139*4882a593Smuzhiyun static DECLARE_AD7791_CHANNELS(ad7790_channels, 16, 16);
140*4882a593Smuzhiyun static DECLARE_AD7791_CHANNELS(ad7791_channels, 24, 32);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun enum {
143*4882a593Smuzhiyun 	AD7787,
144*4882a593Smuzhiyun 	AD7788,
145*4882a593Smuzhiyun 	AD7789,
146*4882a593Smuzhiyun 	AD7790,
147*4882a593Smuzhiyun 	AD7791,
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun enum ad7791_chip_info_flags {
151*4882a593Smuzhiyun 	AD7791_FLAG_HAS_FILTER		= (1 << 0),
152*4882a593Smuzhiyun 	AD7791_FLAG_HAS_BUFFER		= (1 << 1),
153*4882a593Smuzhiyun 	AD7791_FLAG_HAS_UNIPOLAR	= (1 << 2),
154*4882a593Smuzhiyun 	AD7791_FLAG_HAS_BURNOUT		= (1 << 3),
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun struct ad7791_chip_info {
158*4882a593Smuzhiyun 	const struct iio_chan_spec *channels;
159*4882a593Smuzhiyun 	unsigned int num_channels;
160*4882a593Smuzhiyun 	enum ad7791_chip_info_flags flags;
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun static const struct ad7791_chip_info ad7791_chip_infos[] = {
164*4882a593Smuzhiyun 	[AD7787] = {
165*4882a593Smuzhiyun 		.channels = ad7787_channels,
166*4882a593Smuzhiyun 		.num_channels = ARRAY_SIZE(ad7787_channels),
167*4882a593Smuzhiyun 		.flags = AD7791_FLAG_HAS_FILTER | AD7791_FLAG_HAS_BUFFER |
168*4882a593Smuzhiyun 			AD7791_FLAG_HAS_UNIPOLAR | AD7791_FLAG_HAS_BURNOUT,
169*4882a593Smuzhiyun 	},
170*4882a593Smuzhiyun 	[AD7788] = {
171*4882a593Smuzhiyun 		.channels = ad7790_channels,
172*4882a593Smuzhiyun 		.num_channels = ARRAY_SIZE(ad7790_channels),
173*4882a593Smuzhiyun 		.flags = AD7791_FLAG_HAS_UNIPOLAR,
174*4882a593Smuzhiyun 	},
175*4882a593Smuzhiyun 	[AD7789] = {
176*4882a593Smuzhiyun 		.channels = ad7791_channels,
177*4882a593Smuzhiyun 		.num_channels = ARRAY_SIZE(ad7791_channels),
178*4882a593Smuzhiyun 		.flags = AD7791_FLAG_HAS_UNIPOLAR,
179*4882a593Smuzhiyun 	},
180*4882a593Smuzhiyun 	[AD7790] = {
181*4882a593Smuzhiyun 		.channels = ad7790_channels,
182*4882a593Smuzhiyun 		.num_channels = ARRAY_SIZE(ad7790_channels),
183*4882a593Smuzhiyun 		.flags = AD7791_FLAG_HAS_FILTER | AD7791_FLAG_HAS_BUFFER |
184*4882a593Smuzhiyun 			AD7791_FLAG_HAS_BURNOUT,
185*4882a593Smuzhiyun 	},
186*4882a593Smuzhiyun 	[AD7791] = {
187*4882a593Smuzhiyun 		.channels = ad7791_channels,
188*4882a593Smuzhiyun 		.num_channels = ARRAY_SIZE(ad7791_channels),
189*4882a593Smuzhiyun 		.flags = AD7791_FLAG_HAS_FILTER | AD7791_FLAG_HAS_BUFFER |
190*4882a593Smuzhiyun 			AD7791_FLAG_HAS_UNIPOLAR | AD7791_FLAG_HAS_BURNOUT,
191*4882a593Smuzhiyun 	},
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun struct ad7791_state {
195*4882a593Smuzhiyun 	struct ad_sigma_delta sd;
196*4882a593Smuzhiyun 	uint8_t mode;
197*4882a593Smuzhiyun 	uint8_t filter;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	struct regulator *reg;
200*4882a593Smuzhiyun 	const struct ad7791_chip_info *info;
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun static const int ad7791_sample_freq_avail[8][2] = {
204*4882a593Smuzhiyun 	[AD7791_FILTER_RATE_120] =  { 120, 0 },
205*4882a593Smuzhiyun 	[AD7791_FILTER_RATE_100] =  { 100, 0 },
206*4882a593Smuzhiyun 	[AD7791_FILTER_RATE_33_3] = { 33,  300000 },
207*4882a593Smuzhiyun 	[AD7791_FILTER_RATE_20] =   { 20,  0 },
208*4882a593Smuzhiyun 	[AD7791_FILTER_RATE_16_6] = { 16,  600000 },
209*4882a593Smuzhiyun 	[AD7791_FILTER_RATE_16_7] = { 16,  700000 },
210*4882a593Smuzhiyun 	[AD7791_FILTER_RATE_13_3] = { 13,  300000 },
211*4882a593Smuzhiyun 	[AD7791_FILTER_RATE_9_5] =  { 9,   500000 },
212*4882a593Smuzhiyun };
213*4882a593Smuzhiyun 
ad_sigma_delta_to_ad7791(struct ad_sigma_delta * sd)214*4882a593Smuzhiyun static struct ad7791_state *ad_sigma_delta_to_ad7791(struct ad_sigma_delta *sd)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun 	return container_of(sd, struct ad7791_state, sd);
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun 
ad7791_set_channel(struct ad_sigma_delta * sd,unsigned int channel)219*4882a593Smuzhiyun static int ad7791_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
220*4882a593Smuzhiyun {
221*4882a593Smuzhiyun 	ad_sd_set_comm(sd, channel);
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	return 0;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun 
ad7791_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)226*4882a593Smuzhiyun static int ad7791_set_mode(struct ad_sigma_delta *sd,
227*4882a593Smuzhiyun 	enum ad_sigma_delta_mode mode)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun 	struct ad7791_state *st = ad_sigma_delta_to_ad7791(sd);
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	switch (mode) {
232*4882a593Smuzhiyun 	case AD_SD_MODE_CONTINUOUS:
233*4882a593Smuzhiyun 		mode = AD7791_MODE_CONTINUOUS;
234*4882a593Smuzhiyun 		break;
235*4882a593Smuzhiyun 	case AD_SD_MODE_SINGLE:
236*4882a593Smuzhiyun 		mode = AD7791_MODE_SINGLE;
237*4882a593Smuzhiyun 		break;
238*4882a593Smuzhiyun 	case AD_SD_MODE_IDLE:
239*4882a593Smuzhiyun 	case AD_SD_MODE_POWERDOWN:
240*4882a593Smuzhiyun 		mode = AD7791_MODE_POWERDOWN;
241*4882a593Smuzhiyun 		break;
242*4882a593Smuzhiyun 	}
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	st->mode &= ~AD7791_MODE_SEL_MASK;
245*4882a593Smuzhiyun 	st->mode |= AD7791_MODE_SEL(mode);
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	return ad_sd_write_reg(sd, AD7791_REG_MODE, sizeof(st->mode), st->mode);
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun static const struct ad_sigma_delta_info ad7791_sigma_delta_info = {
251*4882a593Smuzhiyun 	.set_channel = ad7791_set_channel,
252*4882a593Smuzhiyun 	.set_mode = ad7791_set_mode,
253*4882a593Smuzhiyun 	.has_registers = true,
254*4882a593Smuzhiyun 	.addr_shift = 4,
255*4882a593Smuzhiyun 	.read_mask = BIT(3),
256*4882a593Smuzhiyun 	.irq_flags = IRQF_TRIGGER_LOW,
257*4882a593Smuzhiyun };
258*4882a593Smuzhiyun 
ad7791_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long info)259*4882a593Smuzhiyun static int ad7791_read_raw(struct iio_dev *indio_dev,
260*4882a593Smuzhiyun 	const struct iio_chan_spec *chan, int *val, int *val2, long info)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun 	struct ad7791_state *st = iio_priv(indio_dev);
263*4882a593Smuzhiyun 	bool unipolar = !!(st->mode & AD7791_MODE_UNIPOLAR);
264*4882a593Smuzhiyun 	unsigned int rate;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	switch (info) {
267*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
268*4882a593Smuzhiyun 		return ad_sigma_delta_single_conversion(indio_dev, chan, val);
269*4882a593Smuzhiyun 	case IIO_CHAN_INFO_OFFSET:
270*4882a593Smuzhiyun 		/**
271*4882a593Smuzhiyun 		 * Unipolar: 0 to VREF
272*4882a593Smuzhiyun 		 * Bipolar -VREF to VREF
273*4882a593Smuzhiyun 		 **/
274*4882a593Smuzhiyun 		if (unipolar)
275*4882a593Smuzhiyun 			*val = 0;
276*4882a593Smuzhiyun 		else
277*4882a593Smuzhiyun 			*val = -(1 << (chan->scan_type.realbits - 1));
278*4882a593Smuzhiyun 		return IIO_VAL_INT;
279*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
280*4882a593Smuzhiyun 		/* The monitor channel uses an internal reference. */
281*4882a593Smuzhiyun 		if (chan->address == AD7791_CH_AVDD_MONITOR) {
282*4882a593Smuzhiyun 			/*
283*4882a593Smuzhiyun 			 * The signal is attenuated by a factor of 5 and
284*4882a593Smuzhiyun 			 * compared against a 1.17V internal reference.
285*4882a593Smuzhiyun 			 */
286*4882a593Smuzhiyun 			*val = 1170 * 5;
287*4882a593Smuzhiyun 		} else {
288*4882a593Smuzhiyun 			int voltage_uv;
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun 			voltage_uv = regulator_get_voltage(st->reg);
291*4882a593Smuzhiyun 			if (voltage_uv < 0)
292*4882a593Smuzhiyun 				return voltage_uv;
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 			*val = voltage_uv / 1000;
295*4882a593Smuzhiyun 		}
296*4882a593Smuzhiyun 		if (unipolar)
297*4882a593Smuzhiyun 			*val2 = chan->scan_type.realbits;
298*4882a593Smuzhiyun 		else
299*4882a593Smuzhiyun 			*val2 = chan->scan_type.realbits - 1;
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 		return IIO_VAL_FRACTIONAL_LOG2;
302*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SAMP_FREQ:
303*4882a593Smuzhiyun 		rate = st->filter & AD7791_FILTER_RATE_MASK;
304*4882a593Smuzhiyun 		*val = ad7791_sample_freq_avail[rate][0];
305*4882a593Smuzhiyun 		*val2 = ad7791_sample_freq_avail[rate][1];
306*4882a593Smuzhiyun 		return IIO_VAL_INT_PLUS_MICRO;
307*4882a593Smuzhiyun 	}
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	return -EINVAL;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun 
ad7791_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)312*4882a593Smuzhiyun static int ad7791_write_raw(struct iio_dev *indio_dev,
313*4882a593Smuzhiyun 	struct iio_chan_spec const *chan, int val, int val2, long mask)
314*4882a593Smuzhiyun {
315*4882a593Smuzhiyun 	struct ad7791_state *st = iio_priv(indio_dev);
316*4882a593Smuzhiyun 	int ret, i;
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	ret = iio_device_claim_direct_mode(indio_dev);
319*4882a593Smuzhiyun 	if (ret)
320*4882a593Smuzhiyun 		return ret;
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	switch (mask) {
323*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SAMP_FREQ:
324*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(ad7791_sample_freq_avail); i++) {
325*4882a593Smuzhiyun 			if (ad7791_sample_freq_avail[i][0] == val &&
326*4882a593Smuzhiyun 			    ad7791_sample_freq_avail[i][1] == val2)
327*4882a593Smuzhiyun 				break;
328*4882a593Smuzhiyun 		}
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 		if (i == ARRAY_SIZE(ad7791_sample_freq_avail)) {
331*4882a593Smuzhiyun 			ret = -EINVAL;
332*4882a593Smuzhiyun 			break;
333*4882a593Smuzhiyun 		}
334*4882a593Smuzhiyun 
335*4882a593Smuzhiyun 		st->filter &= ~AD7791_FILTER_RATE_MASK;
336*4882a593Smuzhiyun 		st->filter |= i;
337*4882a593Smuzhiyun 		ad_sd_write_reg(&st->sd, AD7791_REG_FILTER,
338*4882a593Smuzhiyun 				sizeof(st->filter),
339*4882a593Smuzhiyun 				st->filter);
340*4882a593Smuzhiyun 		break;
341*4882a593Smuzhiyun 	default:
342*4882a593Smuzhiyun 		ret = -EINVAL;
343*4882a593Smuzhiyun 	}
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	iio_device_release_direct_mode(indio_dev);
346*4882a593Smuzhiyun 	return ret;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("120 100 33.3 20 16.7 16.6 13.3 9.5");
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun static struct attribute *ad7791_attributes[] = {
352*4882a593Smuzhiyun 	&iio_const_attr_sampling_frequency_available.dev_attr.attr,
353*4882a593Smuzhiyun 	NULL
354*4882a593Smuzhiyun };
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun static const struct attribute_group ad7791_attribute_group = {
357*4882a593Smuzhiyun 	.attrs = ad7791_attributes,
358*4882a593Smuzhiyun };
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun static const struct iio_info ad7791_info = {
361*4882a593Smuzhiyun 	.read_raw = &ad7791_read_raw,
362*4882a593Smuzhiyun 	.write_raw = &ad7791_write_raw,
363*4882a593Smuzhiyun 	.attrs = &ad7791_attribute_group,
364*4882a593Smuzhiyun 	.validate_trigger = ad_sd_validate_trigger,
365*4882a593Smuzhiyun };
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun static const struct iio_info ad7791_no_filter_info = {
368*4882a593Smuzhiyun 	.read_raw = &ad7791_read_raw,
369*4882a593Smuzhiyun 	.write_raw = &ad7791_write_raw,
370*4882a593Smuzhiyun 	.validate_trigger = ad_sd_validate_trigger,
371*4882a593Smuzhiyun };
372*4882a593Smuzhiyun 
ad7791_setup(struct ad7791_state * st,struct ad7791_platform_data * pdata)373*4882a593Smuzhiyun static int ad7791_setup(struct ad7791_state *st,
374*4882a593Smuzhiyun 			struct ad7791_platform_data *pdata)
375*4882a593Smuzhiyun {
376*4882a593Smuzhiyun 	/* Set to poweron-reset default values */
377*4882a593Smuzhiyun 	st->mode = AD7791_MODE_BUFFER;
378*4882a593Smuzhiyun 	st->filter = AD7791_FILTER_RATE_16_6;
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 	if (!pdata)
381*4882a593Smuzhiyun 		return 0;
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun 	if ((st->info->flags & AD7791_FLAG_HAS_BUFFER) && !pdata->buffered)
384*4882a593Smuzhiyun 		st->mode &= ~AD7791_MODE_BUFFER;
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 	if ((st->info->flags & AD7791_FLAG_HAS_BURNOUT) &&
387*4882a593Smuzhiyun 		pdata->burnout_current)
388*4882a593Smuzhiyun 		st->mode |= AD7791_MODE_BURNOUT;
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	if ((st->info->flags & AD7791_FLAG_HAS_UNIPOLAR) && pdata->unipolar)
391*4882a593Smuzhiyun 		st->mode |= AD7791_MODE_UNIPOLAR;
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	return ad_sd_write_reg(&st->sd, AD7791_REG_MODE, sizeof(st->mode),
394*4882a593Smuzhiyun 		st->mode);
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun 
ad7791_probe(struct spi_device * spi)397*4882a593Smuzhiyun static int ad7791_probe(struct spi_device *spi)
398*4882a593Smuzhiyun {
399*4882a593Smuzhiyun 	struct ad7791_platform_data *pdata = spi->dev.platform_data;
400*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
401*4882a593Smuzhiyun 	struct ad7791_state *st;
402*4882a593Smuzhiyun 	int ret;
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	if (!spi->irq) {
405*4882a593Smuzhiyun 		dev_err(&spi->dev, "Missing IRQ.\n");
406*4882a593Smuzhiyun 		return -ENXIO;
407*4882a593Smuzhiyun 	}
408*4882a593Smuzhiyun 
409*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
410*4882a593Smuzhiyun 	if (!indio_dev)
411*4882a593Smuzhiyun 		return -ENOMEM;
412*4882a593Smuzhiyun 
413*4882a593Smuzhiyun 	st = iio_priv(indio_dev);
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	st->reg = devm_regulator_get(&spi->dev, "refin");
416*4882a593Smuzhiyun 	if (IS_ERR(st->reg))
417*4882a593Smuzhiyun 		return PTR_ERR(st->reg);
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	ret = regulator_enable(st->reg);
420*4882a593Smuzhiyun 	if (ret)
421*4882a593Smuzhiyun 		return ret;
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	st->info = &ad7791_chip_infos[spi_get_device_id(spi)->driver_data];
424*4882a593Smuzhiyun 	ad_sd_init(&st->sd, indio_dev, spi, &ad7791_sigma_delta_info);
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun 	spi_set_drvdata(spi, indio_dev);
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	indio_dev->name = spi_get_device_id(spi)->name;
429*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
430*4882a593Smuzhiyun 	indio_dev->channels = st->info->channels;
431*4882a593Smuzhiyun 	indio_dev->num_channels = st->info->num_channels;
432*4882a593Smuzhiyun 	if (st->info->flags & AD7791_FLAG_HAS_FILTER)
433*4882a593Smuzhiyun 		indio_dev->info = &ad7791_info;
434*4882a593Smuzhiyun 	else
435*4882a593Smuzhiyun 		indio_dev->info = &ad7791_no_filter_info;
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	ret = ad_sd_setup_buffer_and_trigger(indio_dev);
438*4882a593Smuzhiyun 	if (ret)
439*4882a593Smuzhiyun 		goto error_disable_reg;
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun 	ret = ad7791_setup(st, pdata);
442*4882a593Smuzhiyun 	if (ret)
443*4882a593Smuzhiyun 		goto error_remove_trigger;
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	ret = iio_device_register(indio_dev);
446*4882a593Smuzhiyun 	if (ret)
447*4882a593Smuzhiyun 		goto error_remove_trigger;
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 	return 0;
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun error_remove_trigger:
452*4882a593Smuzhiyun 	ad_sd_cleanup_buffer_and_trigger(indio_dev);
453*4882a593Smuzhiyun error_disable_reg:
454*4882a593Smuzhiyun 	regulator_disable(st->reg);
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	return ret;
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun 
ad7791_remove(struct spi_device * spi)459*4882a593Smuzhiyun static int ad7791_remove(struct spi_device *spi)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
462*4882a593Smuzhiyun 	struct ad7791_state *st = iio_priv(indio_dev);
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun 	iio_device_unregister(indio_dev);
465*4882a593Smuzhiyun 	ad_sd_cleanup_buffer_and_trigger(indio_dev);
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun 	regulator_disable(st->reg);
468*4882a593Smuzhiyun 
469*4882a593Smuzhiyun 	return 0;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun static const struct spi_device_id ad7791_spi_ids[] = {
473*4882a593Smuzhiyun 	{ "ad7787", AD7787 },
474*4882a593Smuzhiyun 	{ "ad7788", AD7788 },
475*4882a593Smuzhiyun 	{ "ad7789", AD7789 },
476*4882a593Smuzhiyun 	{ "ad7790", AD7790 },
477*4882a593Smuzhiyun 	{ "ad7791", AD7791 },
478*4882a593Smuzhiyun 	{}
479*4882a593Smuzhiyun };
480*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ad7791_spi_ids);
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun static struct spi_driver ad7791_driver = {
483*4882a593Smuzhiyun 	.driver = {
484*4882a593Smuzhiyun 		.name	= "ad7791",
485*4882a593Smuzhiyun 	},
486*4882a593Smuzhiyun 	.probe		= ad7791_probe,
487*4882a593Smuzhiyun 	.remove		= ad7791_remove,
488*4882a593Smuzhiyun 	.id_table	= ad7791_spi_ids,
489*4882a593Smuzhiyun };
490*4882a593Smuzhiyun module_spi_driver(ad7791_driver);
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
493*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices AD7787/AD7788/AD7789/AD7790/AD7791 ADC driver");
494*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
495