xref: /OK3568_Linux_fs/kernel/drivers/iio/adc/ad7780.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * AD7170/AD7171 and AD7780/AD7781 SPI ADC driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2011 Analog Devices Inc.
6*4882a593Smuzhiyun  * Copyright 2019 Renato Lui Geh
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun #include <linux/sysfs.h>
14*4882a593Smuzhiyun #include <linux/spi/spi.h>
15*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
16*4882a593Smuzhiyun #include <linux/err.h>
17*4882a593Smuzhiyun #include <linux/sched.h>
18*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
19*4882a593Smuzhiyun #include <linux/module.h>
20*4882a593Smuzhiyun #include <linux/bits.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #include <linux/iio/iio.h>
23*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
24*4882a593Smuzhiyun #include <linux/iio/adc/ad_sigma_delta.h>
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #define AD7780_RDY		BIT(7)
27*4882a593Smuzhiyun #define AD7780_FILTER		BIT(6)
28*4882a593Smuzhiyun #define AD7780_ERR		BIT(5)
29*4882a593Smuzhiyun #define AD7780_ID1		BIT(4)
30*4882a593Smuzhiyun #define AD7780_ID0		BIT(3)
31*4882a593Smuzhiyun #define AD7780_GAIN		BIT(2)
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define AD7170_ID		0
34*4882a593Smuzhiyun #define AD7171_ID		1
35*4882a593Smuzhiyun #define AD7780_ID		1
36*4882a593Smuzhiyun #define AD7781_ID		0
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #define AD7780_ID_MASK		(AD7780_ID0 | AD7780_ID1)
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define AD7780_PATTERN_GOOD	1
41*4882a593Smuzhiyun #define AD7780_PATTERN_MASK	GENMASK(1, 0)
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun #define AD7170_PATTERN_GOOD	5
44*4882a593Smuzhiyun #define AD7170_PATTERN_MASK	GENMASK(2, 0)
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define AD7780_GAIN_MIDPOINT	64
47*4882a593Smuzhiyun #define AD7780_FILTER_MIDPOINT	13350
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun static const unsigned int ad778x_gain[2]      = { 1, 128 };
50*4882a593Smuzhiyun static const unsigned int ad778x_odr_avail[2] = { 10000, 16700 };
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun struct ad7780_chip_info {
53*4882a593Smuzhiyun 	struct iio_chan_spec	channel;
54*4882a593Smuzhiyun 	unsigned int		pattern_mask;
55*4882a593Smuzhiyun 	unsigned int		pattern;
56*4882a593Smuzhiyun 	bool			is_ad778x;
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun struct ad7780_state {
60*4882a593Smuzhiyun 	const struct ad7780_chip_info	*chip_info;
61*4882a593Smuzhiyun 	struct regulator		*reg;
62*4882a593Smuzhiyun 	struct gpio_desc		*powerdown_gpio;
63*4882a593Smuzhiyun 	struct gpio_desc		*gain_gpio;
64*4882a593Smuzhiyun 	struct gpio_desc		*filter_gpio;
65*4882a593Smuzhiyun 	unsigned int			gain;
66*4882a593Smuzhiyun 	unsigned int			odr;
67*4882a593Smuzhiyun 	unsigned int			int_vref_mv;
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	struct ad_sigma_delta sd;
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun enum ad7780_supported_device_ids {
73*4882a593Smuzhiyun 	ID_AD7170,
74*4882a593Smuzhiyun 	ID_AD7171,
75*4882a593Smuzhiyun 	ID_AD7780,
76*4882a593Smuzhiyun 	ID_AD7781,
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun 
ad_sigma_delta_to_ad7780(struct ad_sigma_delta * sd)79*4882a593Smuzhiyun static struct ad7780_state *ad_sigma_delta_to_ad7780(struct ad_sigma_delta *sd)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun 	return container_of(sd, struct ad7780_state, sd);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun 
ad7780_set_mode(struct ad_sigma_delta * sigma_delta,enum ad_sigma_delta_mode mode)84*4882a593Smuzhiyun static int ad7780_set_mode(struct ad_sigma_delta *sigma_delta,
85*4882a593Smuzhiyun 			   enum ad_sigma_delta_mode mode)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	struct ad7780_state *st = ad_sigma_delta_to_ad7780(sigma_delta);
88*4882a593Smuzhiyun 	unsigned int val;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	switch (mode) {
91*4882a593Smuzhiyun 	case AD_SD_MODE_SINGLE:
92*4882a593Smuzhiyun 	case AD_SD_MODE_CONTINUOUS:
93*4882a593Smuzhiyun 		val = 1;
94*4882a593Smuzhiyun 		break;
95*4882a593Smuzhiyun 	default:
96*4882a593Smuzhiyun 		val = 0;
97*4882a593Smuzhiyun 		break;
98*4882a593Smuzhiyun 	}
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	gpiod_set_value(st->powerdown_gpio, val);
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	return 0;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun 
ad7780_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)105*4882a593Smuzhiyun static int ad7780_read_raw(struct iio_dev *indio_dev,
106*4882a593Smuzhiyun 			   struct iio_chan_spec const *chan,
107*4882a593Smuzhiyun 			   int *val,
108*4882a593Smuzhiyun 			   int *val2,
109*4882a593Smuzhiyun 			   long m)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun 	struct ad7780_state *st = iio_priv(indio_dev);
112*4882a593Smuzhiyun 	int voltage_uv;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	switch (m) {
115*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
116*4882a593Smuzhiyun 		return ad_sigma_delta_single_conversion(indio_dev, chan, val);
117*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
118*4882a593Smuzhiyun 		voltage_uv = regulator_get_voltage(st->reg);
119*4882a593Smuzhiyun 		if (voltage_uv < 0)
120*4882a593Smuzhiyun 			return voltage_uv;
121*4882a593Smuzhiyun 		voltage_uv /= 1000;
122*4882a593Smuzhiyun 		*val = voltage_uv * st->gain;
123*4882a593Smuzhiyun 		*val2 = chan->scan_type.realbits - 1;
124*4882a593Smuzhiyun 		st->int_vref_mv = voltage_uv;
125*4882a593Smuzhiyun 		return IIO_VAL_FRACTIONAL_LOG2;
126*4882a593Smuzhiyun 	case IIO_CHAN_INFO_OFFSET:
127*4882a593Smuzhiyun 		*val = -(1 << (chan->scan_type.realbits - 1));
128*4882a593Smuzhiyun 		return IIO_VAL_INT;
129*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SAMP_FREQ:
130*4882a593Smuzhiyun 		*val = st->odr;
131*4882a593Smuzhiyun 		return IIO_VAL_INT;
132*4882a593Smuzhiyun 	default:
133*4882a593Smuzhiyun 		break;
134*4882a593Smuzhiyun 	}
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	return -EINVAL;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun 
ad7780_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long m)139*4882a593Smuzhiyun static int ad7780_write_raw(struct iio_dev *indio_dev,
140*4882a593Smuzhiyun 			    struct iio_chan_spec const *chan,
141*4882a593Smuzhiyun 			    int val,
142*4882a593Smuzhiyun 			    int val2,
143*4882a593Smuzhiyun 			    long m)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun 	struct ad7780_state *st = iio_priv(indio_dev);
146*4882a593Smuzhiyun 	const struct ad7780_chip_info *chip_info = st->chip_info;
147*4882a593Smuzhiyun 	unsigned long long vref;
148*4882a593Smuzhiyun 	unsigned int full_scale, gain;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	if (!chip_info->is_ad778x)
151*4882a593Smuzhiyun 		return -EINVAL;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	switch (m) {
154*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
155*4882a593Smuzhiyun 		if (val != 0)
156*4882a593Smuzhiyun 			return -EINVAL;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 		vref = st->int_vref_mv * 1000000LL;
159*4882a593Smuzhiyun 		full_scale = 1 << (chip_info->channel.scan_type.realbits - 1);
160*4882a593Smuzhiyun 		gain = DIV_ROUND_CLOSEST_ULL(vref, full_scale);
161*4882a593Smuzhiyun 		gain = DIV_ROUND_CLOSEST(gain, val2);
162*4882a593Smuzhiyun 		st->gain = gain;
163*4882a593Smuzhiyun 		if (gain < AD7780_GAIN_MIDPOINT)
164*4882a593Smuzhiyun 			gain = 0;
165*4882a593Smuzhiyun 		else
166*4882a593Smuzhiyun 			gain = 1;
167*4882a593Smuzhiyun 		gpiod_set_value(st->gain_gpio, gain);
168*4882a593Smuzhiyun 		break;
169*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SAMP_FREQ:
170*4882a593Smuzhiyun 		if (1000*val + val2/1000 < AD7780_FILTER_MIDPOINT)
171*4882a593Smuzhiyun 			val = 0;
172*4882a593Smuzhiyun 		else
173*4882a593Smuzhiyun 			val = 1;
174*4882a593Smuzhiyun 		st->odr = ad778x_odr_avail[val];
175*4882a593Smuzhiyun 		gpiod_set_value(st->filter_gpio, val);
176*4882a593Smuzhiyun 		break;
177*4882a593Smuzhiyun 	default:
178*4882a593Smuzhiyun 		break;
179*4882a593Smuzhiyun 	}
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	return 0;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun 
ad7780_postprocess_sample(struct ad_sigma_delta * sigma_delta,unsigned int raw_sample)184*4882a593Smuzhiyun static int ad7780_postprocess_sample(struct ad_sigma_delta *sigma_delta,
185*4882a593Smuzhiyun 				     unsigned int raw_sample)
186*4882a593Smuzhiyun {
187*4882a593Smuzhiyun 	struct ad7780_state *st = ad_sigma_delta_to_ad7780(sigma_delta);
188*4882a593Smuzhiyun 	const struct ad7780_chip_info *chip_info = st->chip_info;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	if ((raw_sample & AD7780_ERR) ||
191*4882a593Smuzhiyun 	    ((raw_sample & chip_info->pattern_mask) != chip_info->pattern))
192*4882a593Smuzhiyun 		return -EIO;
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	if (chip_info->is_ad778x) {
195*4882a593Smuzhiyun 		st->gain = ad778x_gain[raw_sample & AD7780_GAIN];
196*4882a593Smuzhiyun 		st->odr = ad778x_odr_avail[raw_sample & AD7780_FILTER];
197*4882a593Smuzhiyun 	}
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	return 0;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun static const struct ad_sigma_delta_info ad7780_sigma_delta_info = {
203*4882a593Smuzhiyun 	.set_mode = ad7780_set_mode,
204*4882a593Smuzhiyun 	.postprocess_sample = ad7780_postprocess_sample,
205*4882a593Smuzhiyun 	.has_registers = false,
206*4882a593Smuzhiyun 	.irq_flags = IRQF_TRIGGER_FALLING,
207*4882a593Smuzhiyun };
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun #define _AD7780_CHANNEL(_bits, _wordsize, _mask_all)		\
210*4882a593Smuzhiyun {								\
211*4882a593Smuzhiyun 	.type = IIO_VOLTAGE,					\
212*4882a593Smuzhiyun 	.indexed = 1,						\
213*4882a593Smuzhiyun 	.channel = 0,						\
214*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
215*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_OFFSET),			\
216*4882a593Smuzhiyun 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
217*4882a593Smuzhiyun 	.info_mask_shared_by_all = _mask_all,			\
218*4882a593Smuzhiyun 	.scan_index = 1,					\
219*4882a593Smuzhiyun 	.scan_type = {						\
220*4882a593Smuzhiyun 		.sign = 'u',					\
221*4882a593Smuzhiyun 		.realbits = (_bits),				\
222*4882a593Smuzhiyun 		.storagebits = 32,				\
223*4882a593Smuzhiyun 		.shift = (_wordsize) - (_bits),			\
224*4882a593Smuzhiyun 		.endianness = IIO_BE,				\
225*4882a593Smuzhiyun 	},							\
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun #define AD7780_CHANNEL(_bits, _wordsize)	\
229*4882a593Smuzhiyun 	_AD7780_CHANNEL(_bits, _wordsize, BIT(IIO_CHAN_INFO_SAMP_FREQ))
230*4882a593Smuzhiyun #define AD7170_CHANNEL(_bits, _wordsize)	\
231*4882a593Smuzhiyun 	_AD7780_CHANNEL(_bits, _wordsize, 0)
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun static const struct ad7780_chip_info ad7780_chip_info_tbl[] = {
234*4882a593Smuzhiyun 	[ID_AD7170] = {
235*4882a593Smuzhiyun 		.channel = AD7170_CHANNEL(12, 24),
236*4882a593Smuzhiyun 		.pattern = AD7170_PATTERN_GOOD,
237*4882a593Smuzhiyun 		.pattern_mask = AD7170_PATTERN_MASK,
238*4882a593Smuzhiyun 		.is_ad778x = false,
239*4882a593Smuzhiyun 	},
240*4882a593Smuzhiyun 	[ID_AD7171] = {
241*4882a593Smuzhiyun 		.channel = AD7170_CHANNEL(16, 24),
242*4882a593Smuzhiyun 		.pattern = AD7170_PATTERN_GOOD,
243*4882a593Smuzhiyun 		.pattern_mask = AD7170_PATTERN_MASK,
244*4882a593Smuzhiyun 		.is_ad778x = false,
245*4882a593Smuzhiyun 	},
246*4882a593Smuzhiyun 	[ID_AD7780] = {
247*4882a593Smuzhiyun 		.channel = AD7780_CHANNEL(24, 32),
248*4882a593Smuzhiyun 		.pattern = AD7780_PATTERN_GOOD,
249*4882a593Smuzhiyun 		.pattern_mask = AD7780_PATTERN_MASK,
250*4882a593Smuzhiyun 		.is_ad778x = true,
251*4882a593Smuzhiyun 	},
252*4882a593Smuzhiyun 	[ID_AD7781] = {
253*4882a593Smuzhiyun 		.channel = AD7780_CHANNEL(20, 32),
254*4882a593Smuzhiyun 		.pattern = AD7780_PATTERN_GOOD,
255*4882a593Smuzhiyun 		.pattern_mask = AD7780_PATTERN_MASK,
256*4882a593Smuzhiyun 		.is_ad778x = true,
257*4882a593Smuzhiyun 	},
258*4882a593Smuzhiyun };
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun static const struct iio_info ad7780_info = {
261*4882a593Smuzhiyun 	.read_raw = ad7780_read_raw,
262*4882a593Smuzhiyun 	.write_raw = ad7780_write_raw,
263*4882a593Smuzhiyun };
264*4882a593Smuzhiyun 
ad7780_init_gpios(struct device * dev,struct ad7780_state * st)265*4882a593Smuzhiyun static int ad7780_init_gpios(struct device *dev, struct ad7780_state *st)
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun 	int ret;
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	st->powerdown_gpio = devm_gpiod_get_optional(dev,
270*4882a593Smuzhiyun 						     "powerdown",
271*4882a593Smuzhiyun 						     GPIOD_OUT_LOW);
272*4882a593Smuzhiyun 	if (IS_ERR(st->powerdown_gpio)) {
273*4882a593Smuzhiyun 		ret = PTR_ERR(st->powerdown_gpio);
274*4882a593Smuzhiyun 		dev_err(dev, "Failed to request powerdown GPIO: %d\n", ret);
275*4882a593Smuzhiyun 		return ret;
276*4882a593Smuzhiyun 	}
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	if (!st->chip_info->is_ad778x)
279*4882a593Smuzhiyun 		return 0;
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	st->gain_gpio = devm_gpiod_get_optional(dev,
283*4882a593Smuzhiyun 						"adi,gain",
284*4882a593Smuzhiyun 						GPIOD_OUT_HIGH);
285*4882a593Smuzhiyun 	if (IS_ERR(st->gain_gpio)) {
286*4882a593Smuzhiyun 		ret = PTR_ERR(st->gain_gpio);
287*4882a593Smuzhiyun 		dev_err(dev, "Failed to request gain GPIO: %d\n", ret);
288*4882a593Smuzhiyun 		return ret;
289*4882a593Smuzhiyun 	}
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	st->filter_gpio = devm_gpiod_get_optional(dev,
292*4882a593Smuzhiyun 						  "adi,filter",
293*4882a593Smuzhiyun 						  GPIOD_OUT_HIGH);
294*4882a593Smuzhiyun 	if (IS_ERR(st->filter_gpio)) {
295*4882a593Smuzhiyun 		ret = PTR_ERR(st->filter_gpio);
296*4882a593Smuzhiyun 		dev_err(dev, "Failed to request filter GPIO: %d\n", ret);
297*4882a593Smuzhiyun 		return ret;
298*4882a593Smuzhiyun 	}
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	return 0;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun 
ad7780_probe(struct spi_device * spi)303*4882a593Smuzhiyun static int ad7780_probe(struct spi_device *spi)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun 	struct ad7780_state *st;
306*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
307*4882a593Smuzhiyun 	int ret;
308*4882a593Smuzhiyun 
309*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
310*4882a593Smuzhiyun 	if (!indio_dev)
311*4882a593Smuzhiyun 		return -ENOMEM;
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun 	st = iio_priv(indio_dev);
314*4882a593Smuzhiyun 	st->gain = 1;
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	ad_sd_init(&st->sd, indio_dev, spi, &ad7780_sigma_delta_info);
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	st->chip_info =
319*4882a593Smuzhiyun 		&ad7780_chip_info_tbl[spi_get_device_id(spi)->driver_data];
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	spi_set_drvdata(spi, indio_dev);
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 	indio_dev->name = spi_get_device_id(spi)->name;
324*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
325*4882a593Smuzhiyun 	indio_dev->channels = &st->chip_info->channel;
326*4882a593Smuzhiyun 	indio_dev->num_channels = 1;
327*4882a593Smuzhiyun 	indio_dev->info = &ad7780_info;
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	ret = ad7780_init_gpios(&spi->dev, st);
330*4882a593Smuzhiyun 	if (ret)
331*4882a593Smuzhiyun 		return ret;
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 	st->reg = devm_regulator_get(&spi->dev, "avdd");
334*4882a593Smuzhiyun 	if (IS_ERR(st->reg))
335*4882a593Smuzhiyun 		return PTR_ERR(st->reg);
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	ret = regulator_enable(st->reg);
338*4882a593Smuzhiyun 	if (ret) {
339*4882a593Smuzhiyun 		dev_err(&spi->dev, "Failed to enable specified AVdd supply\n");
340*4882a593Smuzhiyun 		return ret;
341*4882a593Smuzhiyun 	}
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	ret = ad_sd_setup_buffer_and_trigger(indio_dev);
344*4882a593Smuzhiyun 	if (ret)
345*4882a593Smuzhiyun 		goto error_disable_reg;
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	ret = iio_device_register(indio_dev);
348*4882a593Smuzhiyun 	if (ret)
349*4882a593Smuzhiyun 		goto error_cleanup_buffer_and_trigger;
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 	return 0;
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun error_cleanup_buffer_and_trigger:
354*4882a593Smuzhiyun 	ad_sd_cleanup_buffer_and_trigger(indio_dev);
355*4882a593Smuzhiyun error_disable_reg:
356*4882a593Smuzhiyun 	regulator_disable(st->reg);
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	return ret;
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun 
ad7780_remove(struct spi_device * spi)361*4882a593Smuzhiyun static int ad7780_remove(struct spi_device *spi)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
364*4882a593Smuzhiyun 	struct ad7780_state *st = iio_priv(indio_dev);
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun 	iio_device_unregister(indio_dev);
367*4882a593Smuzhiyun 	ad_sd_cleanup_buffer_and_trigger(indio_dev);
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	regulator_disable(st->reg);
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun 	return 0;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun static const struct spi_device_id ad7780_id[] = {
375*4882a593Smuzhiyun 	{"ad7170", ID_AD7170},
376*4882a593Smuzhiyun 	{"ad7171", ID_AD7171},
377*4882a593Smuzhiyun 	{"ad7780", ID_AD7780},
378*4882a593Smuzhiyun 	{"ad7781", ID_AD7781},
379*4882a593Smuzhiyun 	{}
380*4882a593Smuzhiyun };
381*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ad7780_id);
382*4882a593Smuzhiyun 
383*4882a593Smuzhiyun static struct spi_driver ad7780_driver = {
384*4882a593Smuzhiyun 	.driver = {
385*4882a593Smuzhiyun 		.name	= "ad7780",
386*4882a593Smuzhiyun 	},
387*4882a593Smuzhiyun 	.probe		= ad7780_probe,
388*4882a593Smuzhiyun 	.remove		= ad7780_remove,
389*4882a593Smuzhiyun 	.id_table	= ad7780_id,
390*4882a593Smuzhiyun };
391*4882a593Smuzhiyun module_spi_driver(ad7780_driver);
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
394*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices AD7780 and similar ADCs");
395*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
396