xref: /OK3568_Linux_fs/kernel/drivers/iio/adc/ad7606.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * AD7606 ADC driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2011 Analog Devices Inc.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef IIO_ADC_AD7606_H_
9*4882a593Smuzhiyun #define IIO_ADC_AD7606_H_
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #define AD760X_CHANNEL(num, mask_sep, mask_type, mask_all) {	\
12*4882a593Smuzhiyun 		.type = IIO_VOLTAGE,				\
13*4882a593Smuzhiyun 		.indexed = 1,					\
14*4882a593Smuzhiyun 		.channel = num,					\
15*4882a593Smuzhiyun 		.address = num,					\
16*4882a593Smuzhiyun 		.info_mask_separate = mask_sep,			\
17*4882a593Smuzhiyun 		.info_mask_shared_by_type = mask_type,		\
18*4882a593Smuzhiyun 		.info_mask_shared_by_all = mask_all,		\
19*4882a593Smuzhiyun 		.scan_index = num,				\
20*4882a593Smuzhiyun 		.scan_type = {					\
21*4882a593Smuzhiyun 			.sign = 's',				\
22*4882a593Smuzhiyun 			.realbits = 16,				\
23*4882a593Smuzhiyun 			.storagebits = 16,			\
24*4882a593Smuzhiyun 			.endianness = IIO_CPU,			\
25*4882a593Smuzhiyun 		},						\
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define AD7605_CHANNEL(num)				\
29*4882a593Smuzhiyun 	AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW),	\
30*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_SCALE), 0)
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define AD7606_CHANNEL(num)				\
33*4882a593Smuzhiyun 	AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW),	\
34*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_SCALE),		\
35*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO))
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define AD7616_CHANNEL(num)	\
38*4882a593Smuzhiyun 	AD760X_CHANNEL(num, BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),\
39*4882a593Smuzhiyun 		0, BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO))
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun /**
42*4882a593Smuzhiyun  * struct ad7606_chip_info - chip specific information
43*4882a593Smuzhiyun  * @channels:		channel specification
44*4882a593Smuzhiyun  * @num_channels:	number of channels
45*4882a593Smuzhiyun  * @oversampling_avail	pointer to the array which stores the available
46*4882a593Smuzhiyun  *			oversampling ratios.
47*4882a593Smuzhiyun  * @oversampling_num	number of elements stored in oversampling_avail array
48*4882a593Smuzhiyun  * @os_req_reset	some devices require a reset to update oversampling
49*4882a593Smuzhiyun  * @init_delay_ms	required delay in miliseconds for initialization
50*4882a593Smuzhiyun  *			after a restart
51*4882a593Smuzhiyun  */
52*4882a593Smuzhiyun struct ad7606_chip_info {
53*4882a593Smuzhiyun 	const struct iio_chan_spec	*channels;
54*4882a593Smuzhiyun 	unsigned int			num_channels;
55*4882a593Smuzhiyun 	const unsigned int		*oversampling_avail;
56*4882a593Smuzhiyun 	unsigned int			oversampling_num;
57*4882a593Smuzhiyun 	bool				os_req_reset;
58*4882a593Smuzhiyun 	unsigned long			init_delay_ms;
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun /**
62*4882a593Smuzhiyun  * struct ad7606_state - driver instance specific data
63*4882a593Smuzhiyun  * @dev		pointer to kernel device
64*4882a593Smuzhiyun  * @chip_info		entry in the table of chips that describes this device
65*4882a593Smuzhiyun  * @reg		regulator info for the the power supply of the device
66*4882a593Smuzhiyun  * @bops		bus operations (SPI or parallel)
67*4882a593Smuzhiyun  * @range		voltage range selection, selects which scale to apply
68*4882a593Smuzhiyun  * @oversampling	oversampling selection
69*4882a593Smuzhiyun  * @base_address	address from where to read data in parallel operation
70*4882a593Smuzhiyun  * @sw_mode_en		software mode enabled
71*4882a593Smuzhiyun  * @scale_avail		pointer to the array which stores the available scales
72*4882a593Smuzhiyun  * @num_scales		number of elements stored in the scale_avail array
73*4882a593Smuzhiyun  * @oversampling_avail	pointer to the array which stores the available
74*4882a593Smuzhiyun  *			oversampling ratios.
75*4882a593Smuzhiyun  * @num_os_ratios	number of elements stored in oversampling_avail array
76*4882a593Smuzhiyun  * @write_scale		pointer to the function which writes the scale
77*4882a593Smuzhiyun  * @write_os		pointer to the function which writes the os
78*4882a593Smuzhiyun  * @lock		protect sensor state from concurrent accesses to GPIOs
79*4882a593Smuzhiyun  * @gpio_convst	GPIO descriptor for conversion start signal (CONVST)
80*4882a593Smuzhiyun  * @gpio_reset		GPIO descriptor for device hard-reset
81*4882a593Smuzhiyun  * @gpio_range		GPIO descriptor for range selection
82*4882a593Smuzhiyun  * @gpio_standby	GPIO descriptor for stand-by signal (STBY),
83*4882a593Smuzhiyun  *			controls power-down mode of device
84*4882a593Smuzhiyun  * @gpio_frstdata	GPIO descriptor for reading from device when data
85*4882a593Smuzhiyun  *			is being read on the first channel
86*4882a593Smuzhiyun  * @gpio_os		GPIO descriptors to control oversampling on the device
87*4882a593Smuzhiyun  * @complete		completion to indicate end of conversion
88*4882a593Smuzhiyun  * @trig		The IIO trigger associated with the device.
89*4882a593Smuzhiyun  * @data		buffer for reading data from the device
90*4882a593Smuzhiyun  * @d16			be16 buffer for reading data from the device
91*4882a593Smuzhiyun  */
92*4882a593Smuzhiyun struct ad7606_state {
93*4882a593Smuzhiyun 	struct device			*dev;
94*4882a593Smuzhiyun 	const struct ad7606_chip_info	*chip_info;
95*4882a593Smuzhiyun 	struct regulator		*reg;
96*4882a593Smuzhiyun 	const struct ad7606_bus_ops	*bops;
97*4882a593Smuzhiyun 	unsigned int			range[16];
98*4882a593Smuzhiyun 	unsigned int			oversampling;
99*4882a593Smuzhiyun 	void __iomem			*base_address;
100*4882a593Smuzhiyun 	bool				sw_mode_en;
101*4882a593Smuzhiyun 	const unsigned int		*scale_avail;
102*4882a593Smuzhiyun 	unsigned int			num_scales;
103*4882a593Smuzhiyun 	const unsigned int		*oversampling_avail;
104*4882a593Smuzhiyun 	unsigned int			num_os_ratios;
105*4882a593Smuzhiyun 	int (*write_scale)(struct iio_dev *indio_dev, int ch, int val);
106*4882a593Smuzhiyun 	int (*write_os)(struct iio_dev *indio_dev, int val);
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	struct mutex			lock; /* protect sensor state */
109*4882a593Smuzhiyun 	struct gpio_desc		*gpio_convst;
110*4882a593Smuzhiyun 	struct gpio_desc		*gpio_reset;
111*4882a593Smuzhiyun 	struct gpio_desc		*gpio_range;
112*4882a593Smuzhiyun 	struct gpio_desc		*gpio_standby;
113*4882a593Smuzhiyun 	struct gpio_desc		*gpio_frstdata;
114*4882a593Smuzhiyun 	struct gpio_descs		*gpio_os;
115*4882a593Smuzhiyun 	struct iio_trigger		*trig;
116*4882a593Smuzhiyun 	struct completion		completion;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	/*
119*4882a593Smuzhiyun 	 * DMA (thus cache coherency maintenance) requires the
120*4882a593Smuzhiyun 	 * transfer buffers to live in their own cache lines.
121*4882a593Smuzhiyun 	 * 16 * 16-bit samples + 64-bit timestamp
122*4882a593Smuzhiyun 	 */
123*4882a593Smuzhiyun 	unsigned short			data[20] ____cacheline_aligned;
124*4882a593Smuzhiyun 	__be16				d16[2];
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun /**
128*4882a593Smuzhiyun  * struct ad7606_bus_ops - driver bus operations
129*4882a593Smuzhiyun  * @read_block		function pointer for reading blocks of data
130*4882a593Smuzhiyun  * @sw_mode_config:	pointer to a function which configured the device
131*4882a593Smuzhiyun  *			for software mode
132*4882a593Smuzhiyun  * @reg_read	function pointer for reading spi register
133*4882a593Smuzhiyun  * @reg_write	function pointer for writing spi register
134*4882a593Smuzhiyun  * @write_mask	function pointer for write spi register with mask
135*4882a593Smuzhiyun  * @rd_wr_cmd	pointer to the function which calculates the spi address
136*4882a593Smuzhiyun  */
137*4882a593Smuzhiyun struct ad7606_bus_ops {
138*4882a593Smuzhiyun 	/* more methods added in future? */
139*4882a593Smuzhiyun 	int (*read_block)(struct device *dev, int num, void *data);
140*4882a593Smuzhiyun 	int (*sw_mode_config)(struct iio_dev *indio_dev);
141*4882a593Smuzhiyun 	int (*reg_read)(struct ad7606_state *st, unsigned int addr);
142*4882a593Smuzhiyun 	int (*reg_write)(struct ad7606_state *st,
143*4882a593Smuzhiyun 				unsigned int addr,
144*4882a593Smuzhiyun 				unsigned int val);
145*4882a593Smuzhiyun 	int (*write_mask)(struct ad7606_state *st,
146*4882a593Smuzhiyun 				 unsigned int addr,
147*4882a593Smuzhiyun 				 unsigned long mask,
148*4882a593Smuzhiyun 				 unsigned int val);
149*4882a593Smuzhiyun 	u16 (*rd_wr_cmd)(int addr, char isWriteOp);
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun int ad7606_probe(struct device *dev, int irq, void __iomem *base_address,
153*4882a593Smuzhiyun 		 const char *name, unsigned int id,
154*4882a593Smuzhiyun 		 const struct ad7606_bus_ops *bops);
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun enum ad7606_supported_device_ids {
157*4882a593Smuzhiyun 	ID_AD7605_4,
158*4882a593Smuzhiyun 	ID_AD7606_8,
159*4882a593Smuzhiyun 	ID_AD7606_6,
160*4882a593Smuzhiyun 	ID_AD7606_4,
161*4882a593Smuzhiyun 	ID_AD7606B,
162*4882a593Smuzhiyun 	ID_AD7616,
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
166*4882a593Smuzhiyun extern const struct dev_pm_ops ad7606_pm_ops;
167*4882a593Smuzhiyun #define AD7606_PM_OPS (&ad7606_pm_ops)
168*4882a593Smuzhiyun #else
169*4882a593Smuzhiyun #define AD7606_PM_OPS NULL
170*4882a593Smuzhiyun #endif
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun #endif /* IIO_ADC_AD7606_H_ */
173