1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * AD7298 SPI ADC driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2011 Analog Devices Inc.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/device.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun #include <linux/sysfs.h>
12*4882a593Smuzhiyun #include <linux/spi/spi.h>
13*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
14*4882a593Smuzhiyun #include <linux/err.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/interrupt.h>
18*4882a593Smuzhiyun #include <linux/bitops.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <linux/iio/iio.h>
21*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
22*4882a593Smuzhiyun #include <linux/iio/buffer.h>
23*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
24*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include <linux/platform_data/ad7298.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define AD7298_WRITE BIT(15) /* write to the control register */
29*4882a593Smuzhiyun #define AD7298_REPEAT BIT(14) /* repeated conversion enable */
30*4882a593Smuzhiyun #define AD7298_CH(x) BIT(13 - (x)) /* channel select */
31*4882a593Smuzhiyun #define AD7298_TSENSE BIT(5) /* temperature conversion enable */
32*4882a593Smuzhiyun #define AD7298_EXTREF BIT(2) /* external reference enable */
33*4882a593Smuzhiyun #define AD7298_TAVG BIT(1) /* temperature sensor averaging enable */
34*4882a593Smuzhiyun #define AD7298_PDD BIT(0) /* partial power down enable */
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define AD7298_MAX_CHAN 8
37*4882a593Smuzhiyun #define AD7298_INTREF_mV 2500
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define AD7298_CH_TEMP 9
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun struct ad7298_state {
42*4882a593Smuzhiyun struct spi_device *spi;
43*4882a593Smuzhiyun struct regulator *reg;
44*4882a593Smuzhiyun unsigned ext_ref;
45*4882a593Smuzhiyun struct spi_transfer ring_xfer[10];
46*4882a593Smuzhiyun struct spi_transfer scan_single_xfer[3];
47*4882a593Smuzhiyun struct spi_message ring_msg;
48*4882a593Smuzhiyun struct spi_message scan_single_msg;
49*4882a593Smuzhiyun /*
50*4882a593Smuzhiyun * DMA (thus cache coherency maintenance) requires the
51*4882a593Smuzhiyun * transfer buffers to live in their own cache lines.
52*4882a593Smuzhiyun */
53*4882a593Smuzhiyun __be16 rx_buf[12] ____cacheline_aligned;
54*4882a593Smuzhiyun __be16 tx_buf[2];
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define AD7298_V_CHAN(index) \
58*4882a593Smuzhiyun { \
59*4882a593Smuzhiyun .type = IIO_VOLTAGE, \
60*4882a593Smuzhiyun .indexed = 1, \
61*4882a593Smuzhiyun .channel = index, \
62*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
63*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
64*4882a593Smuzhiyun .address = index, \
65*4882a593Smuzhiyun .scan_index = index, \
66*4882a593Smuzhiyun .scan_type = { \
67*4882a593Smuzhiyun .sign = 'u', \
68*4882a593Smuzhiyun .realbits = 12, \
69*4882a593Smuzhiyun .storagebits = 16, \
70*4882a593Smuzhiyun .endianness = IIO_BE, \
71*4882a593Smuzhiyun }, \
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun static const struct iio_chan_spec ad7298_channels[] = {
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun .type = IIO_TEMP,
77*4882a593Smuzhiyun .indexed = 1,
78*4882a593Smuzhiyun .channel = 0,
79*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
80*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE) |
81*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_OFFSET),
82*4882a593Smuzhiyun .address = AD7298_CH_TEMP,
83*4882a593Smuzhiyun .scan_index = -1,
84*4882a593Smuzhiyun .scan_type = {
85*4882a593Smuzhiyun .sign = 's',
86*4882a593Smuzhiyun .realbits = 32,
87*4882a593Smuzhiyun .storagebits = 32,
88*4882a593Smuzhiyun },
89*4882a593Smuzhiyun },
90*4882a593Smuzhiyun AD7298_V_CHAN(0),
91*4882a593Smuzhiyun AD7298_V_CHAN(1),
92*4882a593Smuzhiyun AD7298_V_CHAN(2),
93*4882a593Smuzhiyun AD7298_V_CHAN(3),
94*4882a593Smuzhiyun AD7298_V_CHAN(4),
95*4882a593Smuzhiyun AD7298_V_CHAN(5),
96*4882a593Smuzhiyun AD7298_V_CHAN(6),
97*4882a593Smuzhiyun AD7298_V_CHAN(7),
98*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(8),
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /*
102*4882a593Smuzhiyun * ad7298_update_scan_mode() setup the spi transfer buffer for the new scan mask
103*4882a593Smuzhiyun */
ad7298_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * active_scan_mask)104*4882a593Smuzhiyun static int ad7298_update_scan_mode(struct iio_dev *indio_dev,
105*4882a593Smuzhiyun const unsigned long *active_scan_mask)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun struct ad7298_state *st = iio_priv(indio_dev);
108*4882a593Smuzhiyun int i, m;
109*4882a593Smuzhiyun unsigned short command;
110*4882a593Smuzhiyun int scan_count;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun /* Now compute overall size */
113*4882a593Smuzhiyun scan_count = bitmap_weight(active_scan_mask, indio_dev->masklength);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun command = AD7298_WRITE | st->ext_ref;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun for (i = 0, m = AD7298_CH(0); i < AD7298_MAX_CHAN; i++, m >>= 1)
118*4882a593Smuzhiyun if (test_bit(i, active_scan_mask))
119*4882a593Smuzhiyun command |= m;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun st->tx_buf[0] = cpu_to_be16(command);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /* build spi ring message */
124*4882a593Smuzhiyun st->ring_xfer[0].tx_buf = &st->tx_buf[0];
125*4882a593Smuzhiyun st->ring_xfer[0].len = 2;
126*4882a593Smuzhiyun st->ring_xfer[0].cs_change = 1;
127*4882a593Smuzhiyun st->ring_xfer[1].tx_buf = &st->tx_buf[1];
128*4882a593Smuzhiyun st->ring_xfer[1].len = 2;
129*4882a593Smuzhiyun st->ring_xfer[1].cs_change = 1;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun spi_message_init(&st->ring_msg);
132*4882a593Smuzhiyun spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
133*4882a593Smuzhiyun spi_message_add_tail(&st->ring_xfer[1], &st->ring_msg);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun for (i = 0; i < scan_count; i++) {
136*4882a593Smuzhiyun st->ring_xfer[i + 2].rx_buf = &st->rx_buf[i];
137*4882a593Smuzhiyun st->ring_xfer[i + 2].len = 2;
138*4882a593Smuzhiyun st->ring_xfer[i + 2].cs_change = 1;
139*4882a593Smuzhiyun spi_message_add_tail(&st->ring_xfer[i + 2], &st->ring_msg);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun /* make sure last transfer cs_change is not set */
142*4882a593Smuzhiyun st->ring_xfer[i + 1].cs_change = 0;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun return 0;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /*
148*4882a593Smuzhiyun * ad7298_trigger_handler() bh of trigger launched polling to ring buffer
149*4882a593Smuzhiyun *
150*4882a593Smuzhiyun * Currently there is no option in this driver to disable the saving of
151*4882a593Smuzhiyun * timestamps within the ring.
152*4882a593Smuzhiyun */
ad7298_trigger_handler(int irq,void * p)153*4882a593Smuzhiyun static irqreturn_t ad7298_trigger_handler(int irq, void *p)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun struct iio_poll_func *pf = p;
156*4882a593Smuzhiyun struct iio_dev *indio_dev = pf->indio_dev;
157*4882a593Smuzhiyun struct ad7298_state *st = iio_priv(indio_dev);
158*4882a593Smuzhiyun int b_sent;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun b_sent = spi_sync(st->spi, &st->ring_msg);
161*4882a593Smuzhiyun if (b_sent)
162*4882a593Smuzhiyun goto done;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
165*4882a593Smuzhiyun iio_get_time_ns(indio_dev));
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun done:
168*4882a593Smuzhiyun iio_trigger_notify_done(indio_dev->trig);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun return IRQ_HANDLED;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun
ad7298_scan_direct(struct ad7298_state * st,unsigned ch)173*4882a593Smuzhiyun static int ad7298_scan_direct(struct ad7298_state *st, unsigned ch)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun int ret;
176*4882a593Smuzhiyun st->tx_buf[0] = cpu_to_be16(AD7298_WRITE | st->ext_ref |
177*4882a593Smuzhiyun (AD7298_CH(0) >> ch));
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun ret = spi_sync(st->spi, &st->scan_single_msg);
180*4882a593Smuzhiyun if (ret)
181*4882a593Smuzhiyun return ret;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun return be16_to_cpu(st->rx_buf[0]);
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
ad7298_scan_temp(struct ad7298_state * st,int * val)186*4882a593Smuzhiyun static int ad7298_scan_temp(struct ad7298_state *st, int *val)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun int ret;
189*4882a593Smuzhiyun __be16 buf;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun buf = cpu_to_be16(AD7298_WRITE | AD7298_TSENSE |
192*4882a593Smuzhiyun AD7298_TAVG | st->ext_ref);
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun ret = spi_write(st->spi, (u8 *)&buf, 2);
195*4882a593Smuzhiyun if (ret)
196*4882a593Smuzhiyun return ret;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun buf = cpu_to_be16(0);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun ret = spi_write(st->spi, (u8 *)&buf, 2);
201*4882a593Smuzhiyun if (ret)
202*4882a593Smuzhiyun return ret;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun usleep_range(101, 1000); /* sleep > 100us */
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun ret = spi_read(st->spi, (u8 *)&buf, 2);
207*4882a593Smuzhiyun if (ret)
208*4882a593Smuzhiyun return ret;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun *val = sign_extend32(be16_to_cpu(buf), 11);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun return 0;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
ad7298_get_ref_voltage(struct ad7298_state * st)215*4882a593Smuzhiyun static int ad7298_get_ref_voltage(struct ad7298_state *st)
216*4882a593Smuzhiyun {
217*4882a593Smuzhiyun int vref;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun if (st->ext_ref) {
220*4882a593Smuzhiyun vref = regulator_get_voltage(st->reg);
221*4882a593Smuzhiyun if (vref < 0)
222*4882a593Smuzhiyun return vref;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun return vref / 1000;
225*4882a593Smuzhiyun } else {
226*4882a593Smuzhiyun return AD7298_INTREF_mV;
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun
ad7298_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)230*4882a593Smuzhiyun static int ad7298_read_raw(struct iio_dev *indio_dev,
231*4882a593Smuzhiyun struct iio_chan_spec const *chan,
232*4882a593Smuzhiyun int *val,
233*4882a593Smuzhiyun int *val2,
234*4882a593Smuzhiyun long m)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun int ret;
237*4882a593Smuzhiyun struct ad7298_state *st = iio_priv(indio_dev);
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun switch (m) {
240*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
241*4882a593Smuzhiyun ret = iio_device_claim_direct_mode(indio_dev);
242*4882a593Smuzhiyun if (ret)
243*4882a593Smuzhiyun return ret;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun if (chan->address == AD7298_CH_TEMP)
246*4882a593Smuzhiyun ret = ad7298_scan_temp(st, val);
247*4882a593Smuzhiyun else
248*4882a593Smuzhiyun ret = ad7298_scan_direct(st, chan->address);
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun iio_device_release_direct_mode(indio_dev);
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun if (ret < 0)
253*4882a593Smuzhiyun return ret;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun if (chan->address != AD7298_CH_TEMP)
256*4882a593Smuzhiyun *val = ret & GENMASK(chan->scan_type.realbits - 1, 0);
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun return IIO_VAL_INT;
259*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
260*4882a593Smuzhiyun switch (chan->type) {
261*4882a593Smuzhiyun case IIO_VOLTAGE:
262*4882a593Smuzhiyun *val = ad7298_get_ref_voltage(st);
263*4882a593Smuzhiyun *val2 = chan->scan_type.realbits;
264*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL_LOG2;
265*4882a593Smuzhiyun case IIO_TEMP:
266*4882a593Smuzhiyun *val = ad7298_get_ref_voltage(st);
267*4882a593Smuzhiyun *val2 = 10;
268*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL;
269*4882a593Smuzhiyun default:
270*4882a593Smuzhiyun return -EINVAL;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun case IIO_CHAN_INFO_OFFSET:
273*4882a593Smuzhiyun *val = 1093 - 2732500 / ad7298_get_ref_voltage(st);
274*4882a593Smuzhiyun return IIO_VAL_INT;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun return -EINVAL;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun static const struct iio_info ad7298_info = {
280*4882a593Smuzhiyun .read_raw = &ad7298_read_raw,
281*4882a593Smuzhiyun .update_scan_mode = ad7298_update_scan_mode,
282*4882a593Smuzhiyun };
283*4882a593Smuzhiyun
ad7298_probe(struct spi_device * spi)284*4882a593Smuzhiyun static int ad7298_probe(struct spi_device *spi)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun struct ad7298_platform_data *pdata = spi->dev.platform_data;
287*4882a593Smuzhiyun struct ad7298_state *st;
288*4882a593Smuzhiyun struct iio_dev *indio_dev;
289*4882a593Smuzhiyun int ret;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
292*4882a593Smuzhiyun if (indio_dev == NULL)
293*4882a593Smuzhiyun return -ENOMEM;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun st = iio_priv(indio_dev);
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun if (pdata && pdata->ext_ref)
298*4882a593Smuzhiyun st->ext_ref = AD7298_EXTREF;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun if (st->ext_ref) {
301*4882a593Smuzhiyun st->reg = devm_regulator_get(&spi->dev, "vref");
302*4882a593Smuzhiyun if (IS_ERR(st->reg))
303*4882a593Smuzhiyun return PTR_ERR(st->reg);
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun ret = regulator_enable(st->reg);
306*4882a593Smuzhiyun if (ret)
307*4882a593Smuzhiyun return ret;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun spi_set_drvdata(spi, indio_dev);
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun st->spi = spi;
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun indio_dev->name = spi_get_device_id(spi)->name;
315*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
316*4882a593Smuzhiyun indio_dev->channels = ad7298_channels;
317*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(ad7298_channels);
318*4882a593Smuzhiyun indio_dev->info = &ad7298_info;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun /* Setup default message */
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
323*4882a593Smuzhiyun st->scan_single_xfer[0].len = 2;
324*4882a593Smuzhiyun st->scan_single_xfer[0].cs_change = 1;
325*4882a593Smuzhiyun st->scan_single_xfer[1].tx_buf = &st->tx_buf[1];
326*4882a593Smuzhiyun st->scan_single_xfer[1].len = 2;
327*4882a593Smuzhiyun st->scan_single_xfer[1].cs_change = 1;
328*4882a593Smuzhiyun st->scan_single_xfer[2].rx_buf = &st->rx_buf[0];
329*4882a593Smuzhiyun st->scan_single_xfer[2].len = 2;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun spi_message_init(&st->scan_single_msg);
332*4882a593Smuzhiyun spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
333*4882a593Smuzhiyun spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
334*4882a593Smuzhiyun spi_message_add_tail(&st->scan_single_xfer[2], &st->scan_single_msg);
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun ret = iio_triggered_buffer_setup(indio_dev, NULL,
337*4882a593Smuzhiyun &ad7298_trigger_handler, NULL);
338*4882a593Smuzhiyun if (ret)
339*4882a593Smuzhiyun goto error_disable_reg;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
342*4882a593Smuzhiyun if (ret)
343*4882a593Smuzhiyun goto error_cleanup_ring;
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun return 0;
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun error_cleanup_ring:
348*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
349*4882a593Smuzhiyun error_disable_reg:
350*4882a593Smuzhiyun if (st->ext_ref)
351*4882a593Smuzhiyun regulator_disable(st->reg);
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun return ret;
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun
ad7298_remove(struct spi_device * spi)356*4882a593Smuzhiyun static int ad7298_remove(struct spi_device *spi)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun struct iio_dev *indio_dev = spi_get_drvdata(spi);
359*4882a593Smuzhiyun struct ad7298_state *st = iio_priv(indio_dev);
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun iio_device_unregister(indio_dev);
362*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
363*4882a593Smuzhiyun if (st->ext_ref)
364*4882a593Smuzhiyun regulator_disable(st->reg);
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun return 0;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun static const struct spi_device_id ad7298_id[] = {
370*4882a593Smuzhiyun {"ad7298", 0},
371*4882a593Smuzhiyun {}
372*4882a593Smuzhiyun };
373*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ad7298_id);
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun static struct spi_driver ad7298_driver = {
376*4882a593Smuzhiyun .driver = {
377*4882a593Smuzhiyun .name = "ad7298",
378*4882a593Smuzhiyun },
379*4882a593Smuzhiyun .probe = ad7298_probe,
380*4882a593Smuzhiyun .remove = ad7298_remove,
381*4882a593Smuzhiyun .id_table = ad7298_id,
382*4882a593Smuzhiyun };
383*4882a593Smuzhiyun module_spi_driver(ad7298_driver);
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
386*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices AD7298 ADC");
387*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
388