xref: /OK3568_Linux_fs/kernel/drivers/iio/adc/ad7291.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * AD7291 8-Channel, I2C, 12-Bit SAR ADC with Temperature Sensor
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2010-2011 Analog Devices Inc.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/device.h>
9*4882a593Smuzhiyun #include <linux/err.h>
10*4882a593Smuzhiyun #include <linux/i2c.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/mutex.h>
15*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun #include <linux/sysfs.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <linux/iio/iio.h>
20*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
21*4882a593Smuzhiyun #include <linux/iio/events.h>
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun /*
24*4882a593Smuzhiyun  * Simplified handling
25*4882a593Smuzhiyun  *
26*4882a593Smuzhiyun  * If no events enabled - single polled channel read
27*4882a593Smuzhiyun  * If event enabled direct reads disable unless channel
28*4882a593Smuzhiyun  * is in the read mask.
29*4882a593Smuzhiyun  *
30*4882a593Smuzhiyun  * The noise-delayed bit as per datasheet suggestion is always enabled.
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun  * AD7291 registers definition
35*4882a593Smuzhiyun  */
36*4882a593Smuzhiyun #define AD7291_COMMAND			0x00
37*4882a593Smuzhiyun #define AD7291_VOLTAGE			0x01
38*4882a593Smuzhiyun #define AD7291_T_SENSE			0x02
39*4882a593Smuzhiyun #define AD7291_T_AVERAGE		0x03
40*4882a593Smuzhiyun #define AD7291_DATA_HIGH(x)		((x) * 3 + 0x4)
41*4882a593Smuzhiyun #define AD7291_DATA_LOW(x)		((x) * 3 + 0x5)
42*4882a593Smuzhiyun #define AD7291_HYST(x)			((x) * 3 + 0x6)
43*4882a593Smuzhiyun #define AD7291_VOLTAGE_ALERT_STATUS	0x1F
44*4882a593Smuzhiyun #define AD7291_T_ALERT_STATUS		0x20
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define AD7291_BITS			12
47*4882a593Smuzhiyun #define AD7291_VOLTAGE_LIMIT_COUNT	8
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun /*
51*4882a593Smuzhiyun  * AD7291 command
52*4882a593Smuzhiyun  */
53*4882a593Smuzhiyun #define AD7291_AUTOCYCLE		BIT(0)
54*4882a593Smuzhiyun #define AD7291_RESET			BIT(1)
55*4882a593Smuzhiyun #define AD7291_ALERT_CLEAR		BIT(2)
56*4882a593Smuzhiyun #define AD7291_ALERT_POLARITY		BIT(3)
57*4882a593Smuzhiyun #define AD7291_EXT_REF			BIT(4)
58*4882a593Smuzhiyun #define AD7291_NOISE_DELAY		BIT(5)
59*4882a593Smuzhiyun #define AD7291_T_SENSE_MASK		BIT(7)
60*4882a593Smuzhiyun #define AD7291_VOLTAGE_MASK		GENMASK(15, 8)
61*4882a593Smuzhiyun #define AD7291_VOLTAGE_OFFSET		8
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun /*
64*4882a593Smuzhiyun  * AD7291 value masks
65*4882a593Smuzhiyun  */
66*4882a593Smuzhiyun #define AD7291_VALUE_MASK		GENMASK(11, 0)
67*4882a593Smuzhiyun 
68*4882a593Smuzhiyun /*
69*4882a593Smuzhiyun  * AD7291 alert register bits
70*4882a593Smuzhiyun  */
71*4882a593Smuzhiyun #define AD7291_T_LOW			BIT(0)
72*4882a593Smuzhiyun #define AD7291_T_HIGH			BIT(1)
73*4882a593Smuzhiyun #define AD7291_T_AVG_LOW		BIT(2)
74*4882a593Smuzhiyun #define AD7291_T_AVG_HIGH		BIT(3)
75*4882a593Smuzhiyun #define AD7291_V_LOW(x)			BIT((x) * 2)
76*4882a593Smuzhiyun #define AD7291_V_HIGH(x)		BIT((x) * 2 + 1)
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun struct ad7291_chip_info {
80*4882a593Smuzhiyun 	struct i2c_client	*client;
81*4882a593Smuzhiyun 	struct regulator	*reg;
82*4882a593Smuzhiyun 	u16			command;
83*4882a593Smuzhiyun 	u16			c_mask;	/* Active voltage channels for events */
84*4882a593Smuzhiyun 	struct mutex		state_lock;
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun 
ad7291_i2c_read(struct ad7291_chip_info * chip,u8 reg,u16 * data)87*4882a593Smuzhiyun static int ad7291_i2c_read(struct ad7291_chip_info *chip, u8 reg, u16 *data)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun 	struct i2c_client *client = chip->client;
90*4882a593Smuzhiyun 	int ret = 0;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	ret = i2c_smbus_read_word_swapped(client, reg);
93*4882a593Smuzhiyun 	if (ret < 0) {
94*4882a593Smuzhiyun 		dev_err(&client->dev, "I2C read error\n");
95*4882a593Smuzhiyun 		return ret;
96*4882a593Smuzhiyun 	}
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	*data = ret;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	return 0;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun 
ad7291_i2c_write(struct ad7291_chip_info * chip,u8 reg,u16 data)103*4882a593Smuzhiyun static int ad7291_i2c_write(struct ad7291_chip_info *chip, u8 reg, u16 data)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun 	return i2c_smbus_write_word_swapped(chip->client, reg, data);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun 
ad7291_event_handler(int irq,void * private)108*4882a593Smuzhiyun static irqreturn_t ad7291_event_handler(int irq, void *private)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun 	struct iio_dev *indio_dev = private;
111*4882a593Smuzhiyun 	struct ad7291_chip_info *chip = iio_priv(private);
112*4882a593Smuzhiyun 	u16 t_status, v_status;
113*4882a593Smuzhiyun 	u16 command;
114*4882a593Smuzhiyun 	int i;
115*4882a593Smuzhiyun 	s64 timestamp = iio_get_time_ns(indio_dev);
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	if (ad7291_i2c_read(chip, AD7291_T_ALERT_STATUS, &t_status))
118*4882a593Smuzhiyun 		return IRQ_HANDLED;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	if (ad7291_i2c_read(chip, AD7291_VOLTAGE_ALERT_STATUS, &v_status))
121*4882a593Smuzhiyun 		return IRQ_HANDLED;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	if (!(t_status || v_status))
124*4882a593Smuzhiyun 		return IRQ_HANDLED;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	command = chip->command | AD7291_ALERT_CLEAR;
127*4882a593Smuzhiyun 	ad7291_i2c_write(chip, AD7291_COMMAND, command);
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	command = chip->command & ~AD7291_ALERT_CLEAR;
130*4882a593Smuzhiyun 	ad7291_i2c_write(chip, AD7291_COMMAND, command);
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	/* For now treat t_sense and t_sense_average the same */
133*4882a593Smuzhiyun 	if ((t_status & AD7291_T_LOW) || (t_status & AD7291_T_AVG_LOW))
134*4882a593Smuzhiyun 		iio_push_event(indio_dev,
135*4882a593Smuzhiyun 			       IIO_UNMOD_EVENT_CODE(IIO_TEMP,
136*4882a593Smuzhiyun 						    0,
137*4882a593Smuzhiyun 						    IIO_EV_TYPE_THRESH,
138*4882a593Smuzhiyun 						    IIO_EV_DIR_FALLING),
139*4882a593Smuzhiyun 			       timestamp);
140*4882a593Smuzhiyun 	if ((t_status & AD7291_T_HIGH) || (t_status & AD7291_T_AVG_HIGH))
141*4882a593Smuzhiyun 		iio_push_event(indio_dev,
142*4882a593Smuzhiyun 			       IIO_UNMOD_EVENT_CODE(IIO_TEMP,
143*4882a593Smuzhiyun 						    0,
144*4882a593Smuzhiyun 						    IIO_EV_TYPE_THRESH,
145*4882a593Smuzhiyun 						    IIO_EV_DIR_RISING),
146*4882a593Smuzhiyun 			       timestamp);
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	for (i = 0; i < AD7291_VOLTAGE_LIMIT_COUNT; i++) {
149*4882a593Smuzhiyun 		if (v_status & AD7291_V_LOW(i))
150*4882a593Smuzhiyun 			iio_push_event(indio_dev,
151*4882a593Smuzhiyun 				       IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE,
152*4882a593Smuzhiyun 							    i,
153*4882a593Smuzhiyun 							    IIO_EV_TYPE_THRESH,
154*4882a593Smuzhiyun 							    IIO_EV_DIR_FALLING),
155*4882a593Smuzhiyun 				       timestamp);
156*4882a593Smuzhiyun 		if (v_status & AD7291_V_HIGH(i))
157*4882a593Smuzhiyun 			iio_push_event(indio_dev,
158*4882a593Smuzhiyun 				       IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE,
159*4882a593Smuzhiyun 							    i,
160*4882a593Smuzhiyun 							    IIO_EV_TYPE_THRESH,
161*4882a593Smuzhiyun 							    IIO_EV_DIR_RISING),
162*4882a593Smuzhiyun 				       timestamp);
163*4882a593Smuzhiyun 	}
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 	return IRQ_HANDLED;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun 
ad7291_threshold_reg(const struct iio_chan_spec * chan,enum iio_event_direction dir,enum iio_event_info info)168*4882a593Smuzhiyun static unsigned int ad7291_threshold_reg(const struct iio_chan_spec *chan,
169*4882a593Smuzhiyun 					 enum iio_event_direction dir,
170*4882a593Smuzhiyun 					 enum iio_event_info info)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun 	unsigned int offset;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	switch (chan->type) {
175*4882a593Smuzhiyun 	case IIO_VOLTAGE:
176*4882a593Smuzhiyun 		offset = chan->channel;
177*4882a593Smuzhiyun 		break;
178*4882a593Smuzhiyun 	case IIO_TEMP:
179*4882a593Smuzhiyun 		offset = AD7291_VOLTAGE_OFFSET;
180*4882a593Smuzhiyun 		break;
181*4882a593Smuzhiyun 	default:
182*4882a593Smuzhiyun 	    return 0;
183*4882a593Smuzhiyun 	}
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	switch (info) {
186*4882a593Smuzhiyun 	case IIO_EV_INFO_VALUE:
187*4882a593Smuzhiyun 		if (dir == IIO_EV_DIR_FALLING)
188*4882a593Smuzhiyun 			return AD7291_DATA_HIGH(offset);
189*4882a593Smuzhiyun 		else
190*4882a593Smuzhiyun 			return AD7291_DATA_LOW(offset);
191*4882a593Smuzhiyun 	case IIO_EV_INFO_HYSTERESIS:
192*4882a593Smuzhiyun 		return AD7291_HYST(offset);
193*4882a593Smuzhiyun 	default:
194*4882a593Smuzhiyun 		break;
195*4882a593Smuzhiyun 	}
196*4882a593Smuzhiyun 	return 0;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun 
ad7291_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)199*4882a593Smuzhiyun static int ad7291_read_event_value(struct iio_dev *indio_dev,
200*4882a593Smuzhiyun 				   const struct iio_chan_spec *chan,
201*4882a593Smuzhiyun 				   enum iio_event_type type,
202*4882a593Smuzhiyun 				   enum iio_event_direction dir,
203*4882a593Smuzhiyun 				   enum iio_event_info info,
204*4882a593Smuzhiyun 				   int *val, int *val2)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun 	struct ad7291_chip_info *chip = iio_priv(indio_dev);
207*4882a593Smuzhiyun 	int ret;
208*4882a593Smuzhiyun 	u16 uval;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	ret = ad7291_i2c_read(chip, ad7291_threshold_reg(chan, dir, info),
211*4882a593Smuzhiyun 			      &uval);
212*4882a593Smuzhiyun 	if (ret < 0)
213*4882a593Smuzhiyun 		return ret;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	if (info == IIO_EV_INFO_HYSTERESIS || chan->type == IIO_VOLTAGE)
216*4882a593Smuzhiyun 		*val = uval & AD7291_VALUE_MASK;
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun 	else
219*4882a593Smuzhiyun 		*val = sign_extend32(uval, 11);
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	return IIO_VAL_INT;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun 
ad7291_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)224*4882a593Smuzhiyun static int ad7291_write_event_value(struct iio_dev *indio_dev,
225*4882a593Smuzhiyun 				    const struct iio_chan_spec *chan,
226*4882a593Smuzhiyun 				    enum iio_event_type type,
227*4882a593Smuzhiyun 				    enum iio_event_direction dir,
228*4882a593Smuzhiyun 				    enum iio_event_info info,
229*4882a593Smuzhiyun 				    int val, int val2)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun 	struct ad7291_chip_info *chip = iio_priv(indio_dev);
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	if (info == IIO_EV_INFO_HYSTERESIS || chan->type == IIO_VOLTAGE) {
234*4882a593Smuzhiyun 		if (val > AD7291_VALUE_MASK || val < 0)
235*4882a593Smuzhiyun 			return -EINVAL;
236*4882a593Smuzhiyun 	} else {
237*4882a593Smuzhiyun 		if (val > 2047 || val < -2048)
238*4882a593Smuzhiyun 			return -EINVAL;
239*4882a593Smuzhiyun 	}
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	return ad7291_i2c_write(chip, ad7291_threshold_reg(chan, dir, info),
242*4882a593Smuzhiyun 				val);
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun 
ad7291_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)245*4882a593Smuzhiyun static int ad7291_read_event_config(struct iio_dev *indio_dev,
246*4882a593Smuzhiyun 				    const struct iio_chan_spec *chan,
247*4882a593Smuzhiyun 				    enum iio_event_type type,
248*4882a593Smuzhiyun 				    enum iio_event_direction dir)
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun 	struct ad7291_chip_info *chip = iio_priv(indio_dev);
251*4882a593Smuzhiyun 	/*
252*4882a593Smuzhiyun 	 * To be enabled the channel must simply be on. If any are enabled
253*4882a593Smuzhiyun 	 * we are in continuous sampling mode
254*4882a593Smuzhiyun 	 */
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	switch (chan->type) {
257*4882a593Smuzhiyun 	case IIO_VOLTAGE:
258*4882a593Smuzhiyun 		return !!(chip->c_mask & BIT(15 - chan->channel));
259*4882a593Smuzhiyun 	case IIO_TEMP:
260*4882a593Smuzhiyun 		/* always on */
261*4882a593Smuzhiyun 		return 1;
262*4882a593Smuzhiyun 	default:
263*4882a593Smuzhiyun 		return -EINVAL;
264*4882a593Smuzhiyun 	}
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun 
ad7291_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)268*4882a593Smuzhiyun static int ad7291_write_event_config(struct iio_dev *indio_dev,
269*4882a593Smuzhiyun 				     const struct iio_chan_spec *chan,
270*4882a593Smuzhiyun 				     enum iio_event_type type,
271*4882a593Smuzhiyun 				     enum iio_event_direction dir,
272*4882a593Smuzhiyun 				     int state)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun 	int ret = 0;
275*4882a593Smuzhiyun 	struct ad7291_chip_info *chip = iio_priv(indio_dev);
276*4882a593Smuzhiyun 	unsigned int mask;
277*4882a593Smuzhiyun 	u16 regval;
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	mutex_lock(&chip->state_lock);
280*4882a593Smuzhiyun 	regval = chip->command;
281*4882a593Smuzhiyun 	/*
282*4882a593Smuzhiyun 	 * To be enabled the channel must simply be on. If any are enabled
283*4882a593Smuzhiyun 	 * use continuous sampling mode.
284*4882a593Smuzhiyun 	 * Possible to disable temp as well but that makes single read tricky.
285*4882a593Smuzhiyun 	 */
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	mask = BIT(15 - chan->channel);
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	switch (chan->type) {
290*4882a593Smuzhiyun 	case IIO_VOLTAGE:
291*4882a593Smuzhiyun 		if ((!state) && (chip->c_mask & mask))
292*4882a593Smuzhiyun 			chip->c_mask &= ~mask;
293*4882a593Smuzhiyun 		else if (state && (!(chip->c_mask & mask)))
294*4882a593Smuzhiyun 			chip->c_mask |= mask;
295*4882a593Smuzhiyun 		else
296*4882a593Smuzhiyun 			break;
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 		regval &= ~AD7291_AUTOCYCLE;
299*4882a593Smuzhiyun 		regval |= chip->c_mask;
300*4882a593Smuzhiyun 		if (chip->c_mask) /* Enable autocycle? */
301*4882a593Smuzhiyun 			regval |= AD7291_AUTOCYCLE;
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 		ret = ad7291_i2c_write(chip, AD7291_COMMAND, regval);
304*4882a593Smuzhiyun 		if (ret < 0)
305*4882a593Smuzhiyun 			goto error_ret;
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun 		chip->command = regval;
308*4882a593Smuzhiyun 		break;
309*4882a593Smuzhiyun 	default:
310*4882a593Smuzhiyun 		ret = -EINVAL;
311*4882a593Smuzhiyun 	}
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun error_ret:
314*4882a593Smuzhiyun 	mutex_unlock(&chip->state_lock);
315*4882a593Smuzhiyun 	return ret;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun 
ad7291_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)318*4882a593Smuzhiyun static int ad7291_read_raw(struct iio_dev *indio_dev,
319*4882a593Smuzhiyun 			   struct iio_chan_spec const *chan,
320*4882a593Smuzhiyun 			   int *val,
321*4882a593Smuzhiyun 			   int *val2,
322*4882a593Smuzhiyun 			   long mask)
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun 	int ret;
325*4882a593Smuzhiyun 	struct ad7291_chip_info *chip = iio_priv(indio_dev);
326*4882a593Smuzhiyun 	u16 regval;
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun 	switch (mask) {
329*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
330*4882a593Smuzhiyun 		switch (chan->type) {
331*4882a593Smuzhiyun 		case IIO_VOLTAGE:
332*4882a593Smuzhiyun 			mutex_lock(&chip->state_lock);
333*4882a593Smuzhiyun 			/* If in autocycle mode drop through */
334*4882a593Smuzhiyun 			if (chip->command & AD7291_AUTOCYCLE) {
335*4882a593Smuzhiyun 				mutex_unlock(&chip->state_lock);
336*4882a593Smuzhiyun 				return -EBUSY;
337*4882a593Smuzhiyun 			}
338*4882a593Smuzhiyun 			/* Enable this channel alone */
339*4882a593Smuzhiyun 			regval = chip->command & (~AD7291_VOLTAGE_MASK);
340*4882a593Smuzhiyun 			regval |= BIT(15 - chan->channel);
341*4882a593Smuzhiyun 			ret = ad7291_i2c_write(chip, AD7291_COMMAND, regval);
342*4882a593Smuzhiyun 			if (ret < 0) {
343*4882a593Smuzhiyun 				mutex_unlock(&chip->state_lock);
344*4882a593Smuzhiyun 				return ret;
345*4882a593Smuzhiyun 			}
346*4882a593Smuzhiyun 			/* Read voltage */
347*4882a593Smuzhiyun 			ret = i2c_smbus_read_word_swapped(chip->client,
348*4882a593Smuzhiyun 							  AD7291_VOLTAGE);
349*4882a593Smuzhiyun 			if (ret < 0) {
350*4882a593Smuzhiyun 				mutex_unlock(&chip->state_lock);
351*4882a593Smuzhiyun 				return ret;
352*4882a593Smuzhiyun 			}
353*4882a593Smuzhiyun 			*val = ret & AD7291_VALUE_MASK;
354*4882a593Smuzhiyun 			mutex_unlock(&chip->state_lock);
355*4882a593Smuzhiyun 			return IIO_VAL_INT;
356*4882a593Smuzhiyun 		case IIO_TEMP:
357*4882a593Smuzhiyun 			/* Assumes tsense bit of command register always set */
358*4882a593Smuzhiyun 			ret = i2c_smbus_read_word_swapped(chip->client,
359*4882a593Smuzhiyun 							  AD7291_T_SENSE);
360*4882a593Smuzhiyun 			if (ret < 0)
361*4882a593Smuzhiyun 				return ret;
362*4882a593Smuzhiyun 			*val = sign_extend32(ret, 11);
363*4882a593Smuzhiyun 			return IIO_VAL_INT;
364*4882a593Smuzhiyun 		default:
365*4882a593Smuzhiyun 			return -EINVAL;
366*4882a593Smuzhiyun 		}
367*4882a593Smuzhiyun 	case IIO_CHAN_INFO_AVERAGE_RAW:
368*4882a593Smuzhiyun 		ret = i2c_smbus_read_word_swapped(chip->client,
369*4882a593Smuzhiyun 						  AD7291_T_AVERAGE);
370*4882a593Smuzhiyun 			if (ret < 0)
371*4882a593Smuzhiyun 				return ret;
372*4882a593Smuzhiyun 			*val = sign_extend32(ret, 11);
373*4882a593Smuzhiyun 			return IIO_VAL_INT;
374*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
375*4882a593Smuzhiyun 		switch (chan->type) {
376*4882a593Smuzhiyun 		case IIO_VOLTAGE:
377*4882a593Smuzhiyun 			if (chip->reg) {
378*4882a593Smuzhiyun 				int vref;
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 				vref = regulator_get_voltage(chip->reg);
381*4882a593Smuzhiyun 				if (vref < 0)
382*4882a593Smuzhiyun 					return vref;
383*4882a593Smuzhiyun 				*val = vref / 1000;
384*4882a593Smuzhiyun 			} else {
385*4882a593Smuzhiyun 				*val = 2500;
386*4882a593Smuzhiyun 			}
387*4882a593Smuzhiyun 			*val2 = AD7291_BITS;
388*4882a593Smuzhiyun 			return IIO_VAL_FRACTIONAL_LOG2;
389*4882a593Smuzhiyun 		case IIO_TEMP:
390*4882a593Smuzhiyun 			/*
391*4882a593Smuzhiyun 			 * One LSB of the ADC corresponds to 0.25 deg C.
392*4882a593Smuzhiyun 			 * The temperature reading is in 12-bit twos
393*4882a593Smuzhiyun 			 * complement format
394*4882a593Smuzhiyun 			 */
395*4882a593Smuzhiyun 			*val = 250;
396*4882a593Smuzhiyun 			return IIO_VAL_INT;
397*4882a593Smuzhiyun 		default:
398*4882a593Smuzhiyun 			return -EINVAL;
399*4882a593Smuzhiyun 		}
400*4882a593Smuzhiyun 	default:
401*4882a593Smuzhiyun 		return -EINVAL;
402*4882a593Smuzhiyun 	}
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun static const struct iio_event_spec ad7291_events[] = {
406*4882a593Smuzhiyun 	{
407*4882a593Smuzhiyun 		.type = IIO_EV_TYPE_THRESH,
408*4882a593Smuzhiyun 		.dir = IIO_EV_DIR_RISING,
409*4882a593Smuzhiyun 		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
410*4882a593Smuzhiyun 			BIT(IIO_EV_INFO_ENABLE),
411*4882a593Smuzhiyun 	}, {
412*4882a593Smuzhiyun 		.type = IIO_EV_TYPE_THRESH,
413*4882a593Smuzhiyun 		.dir = IIO_EV_DIR_FALLING,
414*4882a593Smuzhiyun 		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
415*4882a593Smuzhiyun 			BIT(IIO_EV_INFO_ENABLE),
416*4882a593Smuzhiyun 	}, {
417*4882a593Smuzhiyun 		.type = IIO_EV_TYPE_THRESH,
418*4882a593Smuzhiyun 		.dir = IIO_EV_DIR_EITHER,
419*4882a593Smuzhiyun 		.mask_separate = BIT(IIO_EV_INFO_HYSTERESIS),
420*4882a593Smuzhiyun 	},
421*4882a593Smuzhiyun };
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun #define AD7291_VOLTAGE_CHAN(_chan)					\
424*4882a593Smuzhiyun {									\
425*4882a593Smuzhiyun 	.type = IIO_VOLTAGE,						\
426*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\
427*4882a593Smuzhiyun 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),		\
428*4882a593Smuzhiyun 	.indexed = 1,							\
429*4882a593Smuzhiyun 	.channel = _chan,						\
430*4882a593Smuzhiyun 	.event_spec = ad7291_events,					\
431*4882a593Smuzhiyun 	.num_event_specs = ARRAY_SIZE(ad7291_events),			\
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun static const struct iio_chan_spec ad7291_channels[] = {
435*4882a593Smuzhiyun 	AD7291_VOLTAGE_CHAN(0),
436*4882a593Smuzhiyun 	AD7291_VOLTAGE_CHAN(1),
437*4882a593Smuzhiyun 	AD7291_VOLTAGE_CHAN(2),
438*4882a593Smuzhiyun 	AD7291_VOLTAGE_CHAN(3),
439*4882a593Smuzhiyun 	AD7291_VOLTAGE_CHAN(4),
440*4882a593Smuzhiyun 	AD7291_VOLTAGE_CHAN(5),
441*4882a593Smuzhiyun 	AD7291_VOLTAGE_CHAN(6),
442*4882a593Smuzhiyun 	AD7291_VOLTAGE_CHAN(7),
443*4882a593Smuzhiyun 	{
444*4882a593Smuzhiyun 		.type = IIO_TEMP,
445*4882a593Smuzhiyun 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
446*4882a593Smuzhiyun 				BIT(IIO_CHAN_INFO_AVERAGE_RAW) |
447*4882a593Smuzhiyun 				BIT(IIO_CHAN_INFO_SCALE),
448*4882a593Smuzhiyun 		.indexed = 1,
449*4882a593Smuzhiyun 		.channel = 0,
450*4882a593Smuzhiyun 		.event_spec = ad7291_events,
451*4882a593Smuzhiyun 		.num_event_specs = ARRAY_SIZE(ad7291_events),
452*4882a593Smuzhiyun 	}
453*4882a593Smuzhiyun };
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun static const struct iio_info ad7291_info = {
456*4882a593Smuzhiyun 	.read_raw = &ad7291_read_raw,
457*4882a593Smuzhiyun 	.read_event_config = &ad7291_read_event_config,
458*4882a593Smuzhiyun 	.write_event_config = &ad7291_write_event_config,
459*4882a593Smuzhiyun 	.read_event_value = &ad7291_read_event_value,
460*4882a593Smuzhiyun 	.write_event_value = &ad7291_write_event_value,
461*4882a593Smuzhiyun };
462*4882a593Smuzhiyun 
ad7291_probe(struct i2c_client * client,const struct i2c_device_id * id)463*4882a593Smuzhiyun static int ad7291_probe(struct i2c_client *client,
464*4882a593Smuzhiyun 			const struct i2c_device_id *id)
465*4882a593Smuzhiyun {
466*4882a593Smuzhiyun 	struct ad7291_chip_info *chip;
467*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
468*4882a593Smuzhiyun 	int ret;
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*chip));
471*4882a593Smuzhiyun 	if (!indio_dev)
472*4882a593Smuzhiyun 		return -ENOMEM;
473*4882a593Smuzhiyun 	chip = iio_priv(indio_dev);
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun 	mutex_init(&chip->state_lock);
476*4882a593Smuzhiyun 	/* this is only used for device removal purposes */
477*4882a593Smuzhiyun 	i2c_set_clientdata(client, indio_dev);
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun 	chip->client = client;
480*4882a593Smuzhiyun 
481*4882a593Smuzhiyun 	chip->command = AD7291_NOISE_DELAY |
482*4882a593Smuzhiyun 			AD7291_T_SENSE_MASK | /* Tsense always enabled */
483*4882a593Smuzhiyun 			AD7291_ALERT_POLARITY; /* set irq polarity low level */
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 	chip->reg = devm_regulator_get_optional(&client->dev, "vref");
486*4882a593Smuzhiyun 	if (IS_ERR(chip->reg)) {
487*4882a593Smuzhiyun 		if (PTR_ERR(chip->reg) != -ENODEV)
488*4882a593Smuzhiyun 			return PTR_ERR(chip->reg);
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 		chip->reg = NULL;
491*4882a593Smuzhiyun 	}
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun 	if (chip->reg) {
494*4882a593Smuzhiyun 		ret = regulator_enable(chip->reg);
495*4882a593Smuzhiyun 		if (ret)
496*4882a593Smuzhiyun 			return ret;
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun 		chip->command |= AD7291_EXT_REF;
499*4882a593Smuzhiyun 	}
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun 	indio_dev->name = id->name;
502*4882a593Smuzhiyun 	indio_dev->channels = ad7291_channels;
503*4882a593Smuzhiyun 	indio_dev->num_channels = ARRAY_SIZE(ad7291_channels);
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun 	indio_dev->info = &ad7291_info;
506*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	ret = ad7291_i2c_write(chip, AD7291_COMMAND, AD7291_RESET);
509*4882a593Smuzhiyun 	if (ret) {
510*4882a593Smuzhiyun 		ret = -EIO;
511*4882a593Smuzhiyun 		goto error_disable_reg;
512*4882a593Smuzhiyun 	}
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun 	ret = ad7291_i2c_write(chip, AD7291_COMMAND, chip->command);
515*4882a593Smuzhiyun 	if (ret) {
516*4882a593Smuzhiyun 		ret = -EIO;
517*4882a593Smuzhiyun 		goto error_disable_reg;
518*4882a593Smuzhiyun 	}
519*4882a593Smuzhiyun 
520*4882a593Smuzhiyun 	if (client->irq > 0) {
521*4882a593Smuzhiyun 		ret = request_threaded_irq(client->irq,
522*4882a593Smuzhiyun 					   NULL,
523*4882a593Smuzhiyun 					   &ad7291_event_handler,
524*4882a593Smuzhiyun 					   IRQF_TRIGGER_LOW | IRQF_ONESHOT,
525*4882a593Smuzhiyun 					   id->name,
526*4882a593Smuzhiyun 					   indio_dev);
527*4882a593Smuzhiyun 		if (ret)
528*4882a593Smuzhiyun 			goto error_disable_reg;
529*4882a593Smuzhiyun 	}
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun 	ret = iio_device_register(indio_dev);
532*4882a593Smuzhiyun 	if (ret)
533*4882a593Smuzhiyun 		goto error_unreg_irq;
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	return 0;
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun error_unreg_irq:
538*4882a593Smuzhiyun 	if (client->irq)
539*4882a593Smuzhiyun 		free_irq(client->irq, indio_dev);
540*4882a593Smuzhiyun error_disable_reg:
541*4882a593Smuzhiyun 	if (chip->reg)
542*4882a593Smuzhiyun 		regulator_disable(chip->reg);
543*4882a593Smuzhiyun 
544*4882a593Smuzhiyun 	return ret;
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun 
ad7291_remove(struct i2c_client * client)547*4882a593Smuzhiyun static int ad7291_remove(struct i2c_client *client)
548*4882a593Smuzhiyun {
549*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
550*4882a593Smuzhiyun 	struct ad7291_chip_info *chip = iio_priv(indio_dev);
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun 	iio_device_unregister(indio_dev);
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun 	if (client->irq)
555*4882a593Smuzhiyun 		free_irq(client->irq, indio_dev);
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 	if (chip->reg)
558*4882a593Smuzhiyun 		regulator_disable(chip->reg);
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun 	return 0;
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun static const struct i2c_device_id ad7291_id[] = {
564*4882a593Smuzhiyun 	{ "ad7291", 0 },
565*4882a593Smuzhiyun 	{}
566*4882a593Smuzhiyun };
567*4882a593Smuzhiyun 
568*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, ad7291_id);
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun static const struct of_device_id ad7291_of_match[] = {
571*4882a593Smuzhiyun 	{ .compatible = "adi,ad7291" },
572*4882a593Smuzhiyun 	{}
573*4882a593Smuzhiyun };
574*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ad7291_of_match);
575*4882a593Smuzhiyun 
576*4882a593Smuzhiyun static struct i2c_driver ad7291_driver = {
577*4882a593Smuzhiyun 	.driver = {
578*4882a593Smuzhiyun 		.name = KBUILD_MODNAME,
579*4882a593Smuzhiyun 		.of_match_table = ad7291_of_match,
580*4882a593Smuzhiyun 	},
581*4882a593Smuzhiyun 	.probe = ad7291_probe,
582*4882a593Smuzhiyun 	.remove = ad7291_remove,
583*4882a593Smuzhiyun 	.id_table = ad7291_id,
584*4882a593Smuzhiyun };
585*4882a593Smuzhiyun module_i2c_driver(ad7291_driver);
586*4882a593Smuzhiyun 
587*4882a593Smuzhiyun MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
588*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices AD7291 ADC driver");
589*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
590