1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * AD7091RX Analog to Digital converter driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2014-2019 Analog Devices Inc.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/bitops.h>
9*4882a593Smuzhiyun #include <linux/iio/events.h>
10*4882a593Smuzhiyun #include <linux/iio/iio.h>
11*4882a593Smuzhiyun #include <linux/interrupt.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/regmap.h>
14*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "ad7091r-base.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define AD7091R_REG_RESULT 0
19*4882a593Smuzhiyun #define AD7091R_REG_CHANNEL 1
20*4882a593Smuzhiyun #define AD7091R_REG_CONF 2
21*4882a593Smuzhiyun #define AD7091R_REG_ALERT 3
22*4882a593Smuzhiyun #define AD7091R_REG_CH_LOW_LIMIT(ch) ((ch) * 3 + 4)
23*4882a593Smuzhiyun #define AD7091R_REG_CH_HIGH_LIMIT(ch) ((ch) * 3 + 5)
24*4882a593Smuzhiyun #define AD7091R_REG_CH_HYSTERESIS(ch) ((ch) * 3 + 6)
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* AD7091R_REG_RESULT */
27*4882a593Smuzhiyun #define AD7091R_REG_RESULT_CH_ID(x) (((x) >> 13) & 0x3)
28*4882a593Smuzhiyun #define AD7091R_REG_RESULT_CONV_RESULT(x) ((x) & 0xfff)
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* AD7091R_REG_CONF */
31*4882a593Smuzhiyun #define AD7091R_REG_CONF_AUTO BIT(8)
32*4882a593Smuzhiyun #define AD7091R_REG_CONF_CMD BIT(10)
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define AD7091R_REG_CONF_MODE_MASK \
35*4882a593Smuzhiyun (AD7091R_REG_CONF_AUTO | AD7091R_REG_CONF_CMD)
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun enum ad7091r_mode {
38*4882a593Smuzhiyun AD7091R_MODE_SAMPLE,
39*4882a593Smuzhiyun AD7091R_MODE_COMMAND,
40*4882a593Smuzhiyun AD7091R_MODE_AUTOCYCLE,
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun struct ad7091r_state {
44*4882a593Smuzhiyun struct device *dev;
45*4882a593Smuzhiyun struct regmap *map;
46*4882a593Smuzhiyun struct regulator *vref;
47*4882a593Smuzhiyun const struct ad7091r_chip_info *chip_info;
48*4882a593Smuzhiyun enum ad7091r_mode mode;
49*4882a593Smuzhiyun struct mutex lock; /*lock to prevent concurent reads */
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
ad7091r_set_mode(struct ad7091r_state * st,enum ad7091r_mode mode)52*4882a593Smuzhiyun static int ad7091r_set_mode(struct ad7091r_state *st, enum ad7091r_mode mode)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun int ret, conf;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun switch (mode) {
57*4882a593Smuzhiyun case AD7091R_MODE_SAMPLE:
58*4882a593Smuzhiyun conf = 0;
59*4882a593Smuzhiyun break;
60*4882a593Smuzhiyun case AD7091R_MODE_COMMAND:
61*4882a593Smuzhiyun conf = AD7091R_REG_CONF_CMD;
62*4882a593Smuzhiyun break;
63*4882a593Smuzhiyun case AD7091R_MODE_AUTOCYCLE:
64*4882a593Smuzhiyun conf = AD7091R_REG_CONF_AUTO;
65*4882a593Smuzhiyun break;
66*4882a593Smuzhiyun default:
67*4882a593Smuzhiyun return -EINVAL;
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun ret = regmap_update_bits(st->map, AD7091R_REG_CONF,
71*4882a593Smuzhiyun AD7091R_REG_CONF_MODE_MASK, conf);
72*4882a593Smuzhiyun if (ret)
73*4882a593Smuzhiyun return ret;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun st->mode = mode;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun return 0;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
ad7091r_set_channel(struct ad7091r_state * st,unsigned int channel)80*4882a593Smuzhiyun static int ad7091r_set_channel(struct ad7091r_state *st, unsigned int channel)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun unsigned int dummy;
83*4882a593Smuzhiyun int ret;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* AD7091R_REG_CHANNEL specified which channels to be converted */
86*4882a593Smuzhiyun ret = regmap_write(st->map, AD7091R_REG_CHANNEL,
87*4882a593Smuzhiyun BIT(channel) | (BIT(channel) << 8));
88*4882a593Smuzhiyun if (ret)
89*4882a593Smuzhiyun return ret;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /*
92*4882a593Smuzhiyun * There is a latency of one conversion before the channel conversion
93*4882a593Smuzhiyun * sequence is updated
94*4882a593Smuzhiyun */
95*4882a593Smuzhiyun return regmap_read(st->map, AD7091R_REG_RESULT, &dummy);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
ad7091r_read_one(struct iio_dev * iio_dev,unsigned int channel,unsigned int * read_val)98*4882a593Smuzhiyun static int ad7091r_read_one(struct iio_dev *iio_dev,
99*4882a593Smuzhiyun unsigned int channel, unsigned int *read_val)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun struct ad7091r_state *st = iio_priv(iio_dev);
102*4882a593Smuzhiyun unsigned int val;
103*4882a593Smuzhiyun int ret;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun ret = ad7091r_set_channel(st, channel);
106*4882a593Smuzhiyun if (ret)
107*4882a593Smuzhiyun return ret;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun ret = regmap_read(st->map, AD7091R_REG_RESULT, &val);
110*4882a593Smuzhiyun if (ret)
111*4882a593Smuzhiyun return ret;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun if (AD7091R_REG_RESULT_CH_ID(val) != channel)
114*4882a593Smuzhiyun return -EIO;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun *read_val = AD7091R_REG_RESULT_CONV_RESULT(val);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun return 0;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
ad7091r_read_raw(struct iio_dev * iio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)121*4882a593Smuzhiyun static int ad7091r_read_raw(struct iio_dev *iio_dev,
122*4882a593Smuzhiyun struct iio_chan_spec const *chan,
123*4882a593Smuzhiyun int *val, int *val2, long m)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun struct ad7091r_state *st = iio_priv(iio_dev);
126*4882a593Smuzhiyun unsigned int read_val;
127*4882a593Smuzhiyun int ret;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun mutex_lock(&st->lock);
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun switch (m) {
132*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
133*4882a593Smuzhiyun if (st->mode != AD7091R_MODE_COMMAND) {
134*4882a593Smuzhiyun ret = -EBUSY;
135*4882a593Smuzhiyun goto unlock;
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun ret = ad7091r_read_one(iio_dev, chan->channel, &read_val);
139*4882a593Smuzhiyun if (ret)
140*4882a593Smuzhiyun goto unlock;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun *val = read_val;
143*4882a593Smuzhiyun ret = IIO_VAL_INT;
144*4882a593Smuzhiyun break;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
147*4882a593Smuzhiyun if (st->vref) {
148*4882a593Smuzhiyun ret = regulator_get_voltage(st->vref);
149*4882a593Smuzhiyun if (ret < 0)
150*4882a593Smuzhiyun goto unlock;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun *val = ret / 1000;
153*4882a593Smuzhiyun } else {
154*4882a593Smuzhiyun *val = st->chip_info->vref_mV;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun *val2 = chan->scan_type.realbits;
158*4882a593Smuzhiyun ret = IIO_VAL_FRACTIONAL_LOG2;
159*4882a593Smuzhiyun break;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun default:
162*4882a593Smuzhiyun ret = -EINVAL;
163*4882a593Smuzhiyun break;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun unlock:
167*4882a593Smuzhiyun mutex_unlock(&st->lock);
168*4882a593Smuzhiyun return ret;
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun static const struct iio_info ad7091r_info = {
172*4882a593Smuzhiyun .read_raw = ad7091r_read_raw,
173*4882a593Smuzhiyun };
174*4882a593Smuzhiyun
ad7091r_event_handler(int irq,void * private)175*4882a593Smuzhiyun static irqreturn_t ad7091r_event_handler(int irq, void *private)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun struct ad7091r_state *st = (struct ad7091r_state *) private;
178*4882a593Smuzhiyun struct iio_dev *iio_dev = dev_get_drvdata(st->dev);
179*4882a593Smuzhiyun unsigned int i, read_val;
180*4882a593Smuzhiyun int ret;
181*4882a593Smuzhiyun s64 timestamp = iio_get_time_ns(iio_dev);
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun ret = regmap_read(st->map, AD7091R_REG_ALERT, &read_val);
184*4882a593Smuzhiyun if (ret)
185*4882a593Smuzhiyun return IRQ_HANDLED;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun for (i = 0; i < st->chip_info->num_channels; i++) {
188*4882a593Smuzhiyun if (read_val & BIT(i * 2))
189*4882a593Smuzhiyun iio_push_event(iio_dev,
190*4882a593Smuzhiyun IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, i,
191*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
192*4882a593Smuzhiyun IIO_EV_DIR_RISING), timestamp);
193*4882a593Smuzhiyun if (read_val & BIT(i * 2 + 1))
194*4882a593Smuzhiyun iio_push_event(iio_dev,
195*4882a593Smuzhiyun IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, i,
196*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
197*4882a593Smuzhiyun IIO_EV_DIR_FALLING), timestamp);
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return IRQ_HANDLED;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
ad7091r_remove(void * data)203*4882a593Smuzhiyun static void ad7091r_remove(void *data)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun struct ad7091r_state *st = data;
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun regulator_disable(st->vref);
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
ad7091r_probe(struct device * dev,const char * name,const struct ad7091r_chip_info * chip_info,struct regmap * map,int irq)210*4882a593Smuzhiyun int ad7091r_probe(struct device *dev, const char *name,
211*4882a593Smuzhiyun const struct ad7091r_chip_info *chip_info,
212*4882a593Smuzhiyun struct regmap *map, int irq)
213*4882a593Smuzhiyun {
214*4882a593Smuzhiyun struct iio_dev *iio_dev;
215*4882a593Smuzhiyun struct ad7091r_state *st;
216*4882a593Smuzhiyun int ret;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun iio_dev = devm_iio_device_alloc(dev, sizeof(*st));
219*4882a593Smuzhiyun if (!iio_dev)
220*4882a593Smuzhiyun return -ENOMEM;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun st = iio_priv(iio_dev);
223*4882a593Smuzhiyun st->dev = dev;
224*4882a593Smuzhiyun st->chip_info = chip_info;
225*4882a593Smuzhiyun st->map = map;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun iio_dev->name = name;
228*4882a593Smuzhiyun iio_dev->info = &ad7091r_info;
229*4882a593Smuzhiyun iio_dev->modes = INDIO_DIRECT_MODE;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun iio_dev->num_channels = chip_info->num_channels;
232*4882a593Smuzhiyun iio_dev->channels = chip_info->channels;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun if (irq) {
235*4882a593Smuzhiyun ret = devm_request_threaded_irq(dev, irq, NULL,
236*4882a593Smuzhiyun ad7091r_event_handler,
237*4882a593Smuzhiyun IRQF_TRIGGER_FALLING | IRQF_ONESHOT, name, st);
238*4882a593Smuzhiyun if (ret)
239*4882a593Smuzhiyun return ret;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun st->vref = devm_regulator_get_optional(dev, "vref");
243*4882a593Smuzhiyun if (IS_ERR(st->vref)) {
244*4882a593Smuzhiyun if (PTR_ERR(st->vref) == -EPROBE_DEFER)
245*4882a593Smuzhiyun return -EPROBE_DEFER;
246*4882a593Smuzhiyun st->vref = NULL;
247*4882a593Smuzhiyun } else {
248*4882a593Smuzhiyun ret = regulator_enable(st->vref);
249*4882a593Smuzhiyun if (ret)
250*4882a593Smuzhiyun return ret;
251*4882a593Smuzhiyun ret = devm_add_action_or_reset(dev, ad7091r_remove, st);
252*4882a593Smuzhiyun if (ret)
253*4882a593Smuzhiyun return ret;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun /* Use command mode by default to convert only desired channels*/
257*4882a593Smuzhiyun ret = ad7091r_set_mode(st, AD7091R_MODE_COMMAND);
258*4882a593Smuzhiyun if (ret)
259*4882a593Smuzhiyun return ret;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun return devm_iio_device_register(dev, iio_dev);
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ad7091r_probe);
264*4882a593Smuzhiyun
ad7091r_writeable_reg(struct device * dev,unsigned int reg)265*4882a593Smuzhiyun static bool ad7091r_writeable_reg(struct device *dev, unsigned int reg)
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun switch (reg) {
268*4882a593Smuzhiyun case AD7091R_REG_RESULT:
269*4882a593Smuzhiyun case AD7091R_REG_ALERT:
270*4882a593Smuzhiyun return false;
271*4882a593Smuzhiyun default:
272*4882a593Smuzhiyun return true;
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun
ad7091r_volatile_reg(struct device * dev,unsigned int reg)276*4882a593Smuzhiyun static bool ad7091r_volatile_reg(struct device *dev, unsigned int reg)
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun switch (reg) {
279*4882a593Smuzhiyun case AD7091R_REG_RESULT:
280*4882a593Smuzhiyun case AD7091R_REG_ALERT:
281*4882a593Smuzhiyun return true;
282*4882a593Smuzhiyun default:
283*4882a593Smuzhiyun return false;
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun const struct regmap_config ad7091r_regmap_config = {
288*4882a593Smuzhiyun .reg_bits = 8,
289*4882a593Smuzhiyun .val_bits = 16,
290*4882a593Smuzhiyun .writeable_reg = ad7091r_writeable_reg,
291*4882a593Smuzhiyun .volatile_reg = ad7091r_volatile_reg,
292*4882a593Smuzhiyun };
293*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ad7091r_regmap_config);
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun MODULE_AUTHOR("Beniamin Bia <beniamin.bia@analog.com>");
296*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices AD7091Rx multi-channel converters");
297*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
298