1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /**
3*4882a593Smuzhiyun * Sensortek STK8BA50 3-Axis Accelerometer
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2015, Intel Corporation.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * STK8BA50 7-bit I2C address: 0x18.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/acpi.h>
11*4882a593Smuzhiyun #include <linux/i2c.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/iio/buffer.h>
16*4882a593Smuzhiyun #include <linux/iio/iio.h>
17*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
18*4882a593Smuzhiyun #include <linux/iio/trigger.h>
19*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
20*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define STK8BA50_REG_XOUT 0x02
23*4882a593Smuzhiyun #define STK8BA50_REG_YOUT 0x04
24*4882a593Smuzhiyun #define STK8BA50_REG_ZOUT 0x06
25*4882a593Smuzhiyun #define STK8BA50_REG_RANGE 0x0F
26*4882a593Smuzhiyun #define STK8BA50_REG_BWSEL 0x10
27*4882a593Smuzhiyun #define STK8BA50_REG_POWMODE 0x11
28*4882a593Smuzhiyun #define STK8BA50_REG_SWRST 0x14
29*4882a593Smuzhiyun #define STK8BA50_REG_INTEN2 0x17
30*4882a593Smuzhiyun #define STK8BA50_REG_INTMAP2 0x1A
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define STK8BA50_MODE_NORMAL 0
33*4882a593Smuzhiyun #define STK8BA50_MODE_SUSPEND 1
34*4882a593Smuzhiyun #define STK8BA50_MODE_POWERBIT BIT(7)
35*4882a593Smuzhiyun #define STK8BA50_DATA_SHIFT 6
36*4882a593Smuzhiyun #define STK8BA50_RESET_CMD 0xB6
37*4882a593Smuzhiyun #define STK8BA50_SR_1792HZ_IDX 7
38*4882a593Smuzhiyun #define STK8BA50_DREADY_INT_MASK 0x10
39*4882a593Smuzhiyun #define STK8BA50_DREADY_INT_MAP 0x81
40*4882a593Smuzhiyun #define STK8BA50_ALL_CHANNEL_MASK 7
41*4882a593Smuzhiyun #define STK8BA50_ALL_CHANNEL_SIZE 6
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define STK8BA50_DRIVER_NAME "stk8ba50"
44*4882a593Smuzhiyun #define STK8BA50_IRQ_NAME "stk8ba50_event"
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #define STK8BA50_SCALE_AVAIL "0.0384 0.0767 0.1534 0.3069"
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun * The accelerometer has four measurement ranges:
50*4882a593Smuzhiyun * +/-2g; +/-4g; +/-8g; +/-16g
51*4882a593Smuzhiyun *
52*4882a593Smuzhiyun * Acceleration values are 10-bit, 2's complement.
53*4882a593Smuzhiyun * Scales are calculated as following:
54*4882a593Smuzhiyun *
55*4882a593Smuzhiyun * scale1 = (2 + 2) * 9.81 / (2^10 - 1) = 0.0384
56*4882a593Smuzhiyun * scale2 = (4 + 4) * 9.81 / (2^10 - 1) = 0.0767
57*4882a593Smuzhiyun * etc.
58*4882a593Smuzhiyun *
59*4882a593Smuzhiyun * Scales are stored in this format:
60*4882a593Smuzhiyun * { <register value>, <scale value> }
61*4882a593Smuzhiyun *
62*4882a593Smuzhiyun * Locally, the range is stored as a table index.
63*4882a593Smuzhiyun */
64*4882a593Smuzhiyun static const struct {
65*4882a593Smuzhiyun u8 reg_val;
66*4882a593Smuzhiyun u32 scale_val;
67*4882a593Smuzhiyun } stk8ba50_scale_table[] = {
68*4882a593Smuzhiyun {3, 38400}, {5, 76700}, {8, 153400}, {12, 306900}
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* Sample rates are stored as { <register value>, <Hz value> } */
72*4882a593Smuzhiyun static const struct {
73*4882a593Smuzhiyun u8 reg_val;
74*4882a593Smuzhiyun u16 samp_freq;
75*4882a593Smuzhiyun } stk8ba50_samp_freq_table[] = {
76*4882a593Smuzhiyun {0x08, 14}, {0x09, 25}, {0x0A, 56}, {0x0B, 112},
77*4882a593Smuzhiyun {0x0C, 224}, {0x0D, 448}, {0x0E, 896}, {0x0F, 1792}
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* Used to map scan mask bits to their corresponding channel register. */
81*4882a593Smuzhiyun static const int stk8ba50_channel_table[] = {
82*4882a593Smuzhiyun STK8BA50_REG_XOUT,
83*4882a593Smuzhiyun STK8BA50_REG_YOUT,
84*4882a593Smuzhiyun STK8BA50_REG_ZOUT
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun struct stk8ba50_data {
88*4882a593Smuzhiyun struct i2c_client *client;
89*4882a593Smuzhiyun struct mutex lock;
90*4882a593Smuzhiyun int range;
91*4882a593Smuzhiyun u8 sample_rate_idx;
92*4882a593Smuzhiyun struct iio_trigger *dready_trig;
93*4882a593Smuzhiyun bool dready_trigger_on;
94*4882a593Smuzhiyun /* Ensure timestamp is naturally aligned */
95*4882a593Smuzhiyun struct {
96*4882a593Smuzhiyun s16 chans[3];
97*4882a593Smuzhiyun s64 timetamp __aligned(8);
98*4882a593Smuzhiyun } scan;
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #define STK8BA50_ACCEL_CHANNEL(index, reg, axis) { \
102*4882a593Smuzhiyun .type = IIO_ACCEL, \
103*4882a593Smuzhiyun .address = reg, \
104*4882a593Smuzhiyun .modified = 1, \
105*4882a593Smuzhiyun .channel2 = IIO_MOD_##axis, \
106*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
107*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
108*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SAMP_FREQ), \
109*4882a593Smuzhiyun .scan_index = index, \
110*4882a593Smuzhiyun .scan_type = { \
111*4882a593Smuzhiyun .sign = 's', \
112*4882a593Smuzhiyun .realbits = 10, \
113*4882a593Smuzhiyun .storagebits = 16, \
114*4882a593Smuzhiyun .shift = STK8BA50_DATA_SHIFT, \
115*4882a593Smuzhiyun .endianness = IIO_CPU, \
116*4882a593Smuzhiyun }, \
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun static const struct iio_chan_spec stk8ba50_channels[] = {
120*4882a593Smuzhiyun STK8BA50_ACCEL_CHANNEL(0, STK8BA50_REG_XOUT, X),
121*4882a593Smuzhiyun STK8BA50_ACCEL_CHANNEL(1, STK8BA50_REG_YOUT, Y),
122*4882a593Smuzhiyun STK8BA50_ACCEL_CHANNEL(2, STK8BA50_REG_ZOUT, Z),
123*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(3),
124*4882a593Smuzhiyun };
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun static IIO_CONST_ATTR(in_accel_scale_available, STK8BA50_SCALE_AVAIL);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("14 25 56 112 224 448 896 1792");
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun static struct attribute *stk8ba50_attributes[] = {
131*4882a593Smuzhiyun &iio_const_attr_in_accel_scale_available.dev_attr.attr,
132*4882a593Smuzhiyun &iio_const_attr_sampling_frequency_available.dev_attr.attr,
133*4882a593Smuzhiyun NULL,
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun static const struct attribute_group stk8ba50_attribute_group = {
137*4882a593Smuzhiyun .attrs = stk8ba50_attributes
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun
stk8ba50_read_accel(struct stk8ba50_data * data,u8 reg)140*4882a593Smuzhiyun static int stk8ba50_read_accel(struct stk8ba50_data *data, u8 reg)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun int ret;
143*4882a593Smuzhiyun struct i2c_client *client = data->client;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun ret = i2c_smbus_read_word_data(client, reg);
146*4882a593Smuzhiyun if (ret < 0) {
147*4882a593Smuzhiyun dev_err(&client->dev, "register read failed\n");
148*4882a593Smuzhiyun return ret;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun return ret;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
stk8ba50_data_rdy_trigger_set_state(struct iio_trigger * trig,bool state)154*4882a593Smuzhiyun static int stk8ba50_data_rdy_trigger_set_state(struct iio_trigger *trig,
155*4882a593Smuzhiyun bool state)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
158*4882a593Smuzhiyun struct stk8ba50_data *data = iio_priv(indio_dev);
159*4882a593Smuzhiyun int ret;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun if (state)
162*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client,
163*4882a593Smuzhiyun STK8BA50_REG_INTEN2, STK8BA50_DREADY_INT_MASK);
164*4882a593Smuzhiyun else
165*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client,
166*4882a593Smuzhiyun STK8BA50_REG_INTEN2, 0x00);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun if (ret < 0)
169*4882a593Smuzhiyun dev_err(&data->client->dev, "failed to set trigger state\n");
170*4882a593Smuzhiyun else
171*4882a593Smuzhiyun data->dready_trigger_on = state;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun return ret;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun static const struct iio_trigger_ops stk8ba50_trigger_ops = {
177*4882a593Smuzhiyun .set_trigger_state = stk8ba50_data_rdy_trigger_set_state,
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun
stk8ba50_set_power(struct stk8ba50_data * data,bool mode)180*4882a593Smuzhiyun static int stk8ba50_set_power(struct stk8ba50_data *data, bool mode)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun int ret;
183*4882a593Smuzhiyun u8 masked_reg;
184*4882a593Smuzhiyun struct i2c_client *client = data->client;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(client, STK8BA50_REG_POWMODE);
187*4882a593Smuzhiyun if (ret < 0)
188*4882a593Smuzhiyun goto exit_err;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun if (mode)
191*4882a593Smuzhiyun masked_reg = ret | STK8BA50_MODE_POWERBIT;
192*4882a593Smuzhiyun else
193*4882a593Smuzhiyun masked_reg = ret & (~STK8BA50_MODE_POWERBIT);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(client, STK8BA50_REG_POWMODE,
196*4882a593Smuzhiyun masked_reg);
197*4882a593Smuzhiyun if (ret < 0)
198*4882a593Smuzhiyun goto exit_err;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return ret;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun exit_err:
203*4882a593Smuzhiyun dev_err(&client->dev, "failed to change sensor mode\n");
204*4882a593Smuzhiyun return ret;
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun
stk8ba50_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)207*4882a593Smuzhiyun static int stk8ba50_read_raw(struct iio_dev *indio_dev,
208*4882a593Smuzhiyun struct iio_chan_spec const *chan,
209*4882a593Smuzhiyun int *val, int *val2, long mask)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun struct stk8ba50_data *data = iio_priv(indio_dev);
212*4882a593Smuzhiyun int ret;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun switch (mask) {
215*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
216*4882a593Smuzhiyun if (iio_buffer_enabled(indio_dev))
217*4882a593Smuzhiyun return -EBUSY;
218*4882a593Smuzhiyun mutex_lock(&data->lock);
219*4882a593Smuzhiyun ret = stk8ba50_set_power(data, STK8BA50_MODE_NORMAL);
220*4882a593Smuzhiyun if (ret < 0) {
221*4882a593Smuzhiyun mutex_unlock(&data->lock);
222*4882a593Smuzhiyun return -EINVAL;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun ret = stk8ba50_read_accel(data, chan->address);
225*4882a593Smuzhiyun if (ret < 0) {
226*4882a593Smuzhiyun stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND);
227*4882a593Smuzhiyun mutex_unlock(&data->lock);
228*4882a593Smuzhiyun return -EINVAL;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun *val = sign_extend32(ret >> STK8BA50_DATA_SHIFT, 9);
231*4882a593Smuzhiyun stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND);
232*4882a593Smuzhiyun mutex_unlock(&data->lock);
233*4882a593Smuzhiyun return IIO_VAL_INT;
234*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
235*4882a593Smuzhiyun *val = 0;
236*4882a593Smuzhiyun *val2 = stk8ba50_scale_table[data->range].scale_val;
237*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
238*4882a593Smuzhiyun case IIO_CHAN_INFO_SAMP_FREQ:
239*4882a593Smuzhiyun *val = stk8ba50_samp_freq_table
240*4882a593Smuzhiyun [data->sample_rate_idx].samp_freq;
241*4882a593Smuzhiyun *val2 = 0;
242*4882a593Smuzhiyun return IIO_VAL_INT;
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun return -EINVAL;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
stk8ba50_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)248*4882a593Smuzhiyun static int stk8ba50_write_raw(struct iio_dev *indio_dev,
249*4882a593Smuzhiyun struct iio_chan_spec const *chan,
250*4882a593Smuzhiyun int val, int val2, long mask)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun int ret;
253*4882a593Smuzhiyun int i;
254*4882a593Smuzhiyun int index = -1;
255*4882a593Smuzhiyun struct stk8ba50_data *data = iio_priv(indio_dev);
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun switch (mask) {
258*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
259*4882a593Smuzhiyun if (val != 0)
260*4882a593Smuzhiyun return -EINVAL;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(stk8ba50_scale_table); i++)
263*4882a593Smuzhiyun if (val2 == stk8ba50_scale_table[i].scale_val) {
264*4882a593Smuzhiyun index = i;
265*4882a593Smuzhiyun break;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun if (index < 0)
268*4882a593Smuzhiyun return -EINVAL;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client,
271*4882a593Smuzhiyun STK8BA50_REG_RANGE,
272*4882a593Smuzhiyun stk8ba50_scale_table[index].reg_val);
273*4882a593Smuzhiyun if (ret < 0)
274*4882a593Smuzhiyun dev_err(&data->client->dev,
275*4882a593Smuzhiyun "failed to set measurement range\n");
276*4882a593Smuzhiyun else
277*4882a593Smuzhiyun data->range = index;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun return ret;
280*4882a593Smuzhiyun case IIO_CHAN_INFO_SAMP_FREQ:
281*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(stk8ba50_samp_freq_table); i++)
282*4882a593Smuzhiyun if (val == stk8ba50_samp_freq_table[i].samp_freq) {
283*4882a593Smuzhiyun index = i;
284*4882a593Smuzhiyun break;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun if (index < 0)
287*4882a593Smuzhiyun return -EINVAL;
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client,
290*4882a593Smuzhiyun STK8BA50_REG_BWSEL,
291*4882a593Smuzhiyun stk8ba50_samp_freq_table[index].reg_val);
292*4882a593Smuzhiyun if (ret < 0)
293*4882a593Smuzhiyun dev_err(&data->client->dev,
294*4882a593Smuzhiyun "failed to set sampling rate\n");
295*4882a593Smuzhiyun else
296*4882a593Smuzhiyun data->sample_rate_idx = index;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun return ret;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun return -EINVAL;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun static const struct iio_info stk8ba50_info = {
305*4882a593Smuzhiyun .read_raw = stk8ba50_read_raw,
306*4882a593Smuzhiyun .write_raw = stk8ba50_write_raw,
307*4882a593Smuzhiyun .attrs = &stk8ba50_attribute_group,
308*4882a593Smuzhiyun };
309*4882a593Smuzhiyun
stk8ba50_trigger_handler(int irq,void * p)310*4882a593Smuzhiyun static irqreturn_t stk8ba50_trigger_handler(int irq, void *p)
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun struct iio_poll_func *pf = p;
313*4882a593Smuzhiyun struct iio_dev *indio_dev = pf->indio_dev;
314*4882a593Smuzhiyun struct stk8ba50_data *data = iio_priv(indio_dev);
315*4882a593Smuzhiyun int bit, ret, i = 0;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun mutex_lock(&data->lock);
318*4882a593Smuzhiyun /*
319*4882a593Smuzhiyun * Do a bulk read if all channels are requested,
320*4882a593Smuzhiyun * from 0x02 (XOUT1) to 0x07 (ZOUT2)
321*4882a593Smuzhiyun */
322*4882a593Smuzhiyun if (*(indio_dev->active_scan_mask) == STK8BA50_ALL_CHANNEL_MASK) {
323*4882a593Smuzhiyun ret = i2c_smbus_read_i2c_block_data(data->client,
324*4882a593Smuzhiyun STK8BA50_REG_XOUT,
325*4882a593Smuzhiyun STK8BA50_ALL_CHANNEL_SIZE,
326*4882a593Smuzhiyun (u8 *)data->scan.chans);
327*4882a593Smuzhiyun if (ret < STK8BA50_ALL_CHANNEL_SIZE) {
328*4882a593Smuzhiyun dev_err(&data->client->dev, "register read failed\n");
329*4882a593Smuzhiyun goto err;
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun } else {
332*4882a593Smuzhiyun for_each_set_bit(bit, indio_dev->active_scan_mask,
333*4882a593Smuzhiyun indio_dev->masklength) {
334*4882a593Smuzhiyun ret = stk8ba50_read_accel(data,
335*4882a593Smuzhiyun stk8ba50_channel_table[bit]);
336*4882a593Smuzhiyun if (ret < 0)
337*4882a593Smuzhiyun goto err;
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun data->scan.chans[i++] = ret;
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
343*4882a593Smuzhiyun pf->timestamp);
344*4882a593Smuzhiyun err:
345*4882a593Smuzhiyun mutex_unlock(&data->lock);
346*4882a593Smuzhiyun iio_trigger_notify_done(indio_dev->trig);
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun return IRQ_HANDLED;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
stk8ba50_data_rdy_trig_poll(int irq,void * private)351*4882a593Smuzhiyun static irqreturn_t stk8ba50_data_rdy_trig_poll(int irq, void *private)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun struct iio_dev *indio_dev = private;
354*4882a593Smuzhiyun struct stk8ba50_data *data = iio_priv(indio_dev);
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun if (data->dready_trigger_on)
357*4882a593Smuzhiyun iio_trigger_poll(data->dready_trig);
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun return IRQ_HANDLED;
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
stk8ba50_buffer_preenable(struct iio_dev * indio_dev)362*4882a593Smuzhiyun static int stk8ba50_buffer_preenable(struct iio_dev *indio_dev)
363*4882a593Smuzhiyun {
364*4882a593Smuzhiyun struct stk8ba50_data *data = iio_priv(indio_dev);
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun return stk8ba50_set_power(data, STK8BA50_MODE_NORMAL);
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun
stk8ba50_buffer_postdisable(struct iio_dev * indio_dev)369*4882a593Smuzhiyun static int stk8ba50_buffer_postdisable(struct iio_dev *indio_dev)
370*4882a593Smuzhiyun {
371*4882a593Smuzhiyun struct stk8ba50_data *data = iio_priv(indio_dev);
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun return stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND);
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun static const struct iio_buffer_setup_ops stk8ba50_buffer_setup_ops = {
377*4882a593Smuzhiyun .preenable = stk8ba50_buffer_preenable,
378*4882a593Smuzhiyun .postdisable = stk8ba50_buffer_postdisable,
379*4882a593Smuzhiyun };
380*4882a593Smuzhiyun
stk8ba50_probe(struct i2c_client * client,const struct i2c_device_id * id)381*4882a593Smuzhiyun static int stk8ba50_probe(struct i2c_client *client,
382*4882a593Smuzhiyun const struct i2c_device_id *id)
383*4882a593Smuzhiyun {
384*4882a593Smuzhiyun int ret;
385*4882a593Smuzhiyun struct iio_dev *indio_dev;
386*4882a593Smuzhiyun struct stk8ba50_data *data;
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
389*4882a593Smuzhiyun if (!indio_dev) {
390*4882a593Smuzhiyun dev_err(&client->dev, "iio allocation failed!\n");
391*4882a593Smuzhiyun return -ENOMEM;
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun data = iio_priv(indio_dev);
395*4882a593Smuzhiyun data->client = client;
396*4882a593Smuzhiyun i2c_set_clientdata(client, indio_dev);
397*4882a593Smuzhiyun mutex_init(&data->lock);
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun indio_dev->info = &stk8ba50_info;
400*4882a593Smuzhiyun indio_dev->name = STK8BA50_DRIVER_NAME;
401*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
402*4882a593Smuzhiyun indio_dev->channels = stk8ba50_channels;
403*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(stk8ba50_channels);
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun /* Reset all registers on startup */
406*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(client,
407*4882a593Smuzhiyun STK8BA50_REG_SWRST, STK8BA50_RESET_CMD);
408*4882a593Smuzhiyun if (ret < 0) {
409*4882a593Smuzhiyun dev_err(&client->dev, "failed to reset sensor\n");
410*4882a593Smuzhiyun goto err_power_off;
411*4882a593Smuzhiyun }
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun /* The default range is +/-2g */
414*4882a593Smuzhiyun data->range = 0;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun /* The default sampling rate is 1792 Hz (maximum) */
417*4882a593Smuzhiyun data->sample_rate_idx = STK8BA50_SR_1792HZ_IDX;
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun /* Set up interrupts */
420*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(client,
421*4882a593Smuzhiyun STK8BA50_REG_INTEN2, STK8BA50_DREADY_INT_MASK);
422*4882a593Smuzhiyun if (ret < 0) {
423*4882a593Smuzhiyun dev_err(&client->dev, "failed to set up interrupts\n");
424*4882a593Smuzhiyun goto err_power_off;
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(client,
427*4882a593Smuzhiyun STK8BA50_REG_INTMAP2, STK8BA50_DREADY_INT_MAP);
428*4882a593Smuzhiyun if (ret < 0) {
429*4882a593Smuzhiyun dev_err(&client->dev, "failed to set up interrupts\n");
430*4882a593Smuzhiyun goto err_power_off;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun if (client->irq > 0) {
434*4882a593Smuzhiyun ret = devm_request_threaded_irq(&client->dev, client->irq,
435*4882a593Smuzhiyun stk8ba50_data_rdy_trig_poll,
436*4882a593Smuzhiyun NULL,
437*4882a593Smuzhiyun IRQF_TRIGGER_RISING |
438*4882a593Smuzhiyun IRQF_ONESHOT,
439*4882a593Smuzhiyun STK8BA50_IRQ_NAME,
440*4882a593Smuzhiyun indio_dev);
441*4882a593Smuzhiyun if (ret < 0) {
442*4882a593Smuzhiyun dev_err(&client->dev, "request irq %d failed\n",
443*4882a593Smuzhiyun client->irq);
444*4882a593Smuzhiyun goto err_power_off;
445*4882a593Smuzhiyun }
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun data->dready_trig = devm_iio_trigger_alloc(&client->dev,
448*4882a593Smuzhiyun "%s-dev%d",
449*4882a593Smuzhiyun indio_dev->name,
450*4882a593Smuzhiyun indio_dev->id);
451*4882a593Smuzhiyun if (!data->dready_trig) {
452*4882a593Smuzhiyun ret = -ENOMEM;
453*4882a593Smuzhiyun goto err_power_off;
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun data->dready_trig->dev.parent = &client->dev;
457*4882a593Smuzhiyun data->dready_trig->ops = &stk8ba50_trigger_ops;
458*4882a593Smuzhiyun iio_trigger_set_drvdata(data->dready_trig, indio_dev);
459*4882a593Smuzhiyun ret = iio_trigger_register(data->dready_trig);
460*4882a593Smuzhiyun if (ret) {
461*4882a593Smuzhiyun dev_err(&client->dev, "iio trigger register failed\n");
462*4882a593Smuzhiyun goto err_power_off;
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun ret = iio_triggered_buffer_setup(indio_dev,
467*4882a593Smuzhiyun iio_pollfunc_store_time,
468*4882a593Smuzhiyun stk8ba50_trigger_handler,
469*4882a593Smuzhiyun &stk8ba50_buffer_setup_ops);
470*4882a593Smuzhiyun if (ret < 0) {
471*4882a593Smuzhiyun dev_err(&client->dev, "iio triggered buffer setup failed\n");
472*4882a593Smuzhiyun goto err_trigger_unregister;
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
476*4882a593Smuzhiyun if (ret < 0) {
477*4882a593Smuzhiyun dev_err(&client->dev, "device_register failed\n");
478*4882a593Smuzhiyun goto err_buffer_cleanup;
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun return ret;
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun err_buffer_cleanup:
484*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
485*4882a593Smuzhiyun err_trigger_unregister:
486*4882a593Smuzhiyun if (data->dready_trig)
487*4882a593Smuzhiyun iio_trigger_unregister(data->dready_trig);
488*4882a593Smuzhiyun err_power_off:
489*4882a593Smuzhiyun stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND);
490*4882a593Smuzhiyun return ret;
491*4882a593Smuzhiyun }
492*4882a593Smuzhiyun
stk8ba50_remove(struct i2c_client * client)493*4882a593Smuzhiyun static int stk8ba50_remove(struct i2c_client *client)
494*4882a593Smuzhiyun {
495*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(client);
496*4882a593Smuzhiyun struct stk8ba50_data *data = iio_priv(indio_dev);
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun iio_device_unregister(indio_dev);
499*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun if (data->dready_trig)
502*4882a593Smuzhiyun iio_trigger_unregister(data->dready_trig);
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun return stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND);
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
stk8ba50_suspend(struct device * dev)508*4882a593Smuzhiyun static int stk8ba50_suspend(struct device *dev)
509*4882a593Smuzhiyun {
510*4882a593Smuzhiyun struct stk8ba50_data *data;
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun data = iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
513*4882a593Smuzhiyun
514*4882a593Smuzhiyun return stk8ba50_set_power(data, STK8BA50_MODE_SUSPEND);
515*4882a593Smuzhiyun }
516*4882a593Smuzhiyun
stk8ba50_resume(struct device * dev)517*4882a593Smuzhiyun static int stk8ba50_resume(struct device *dev)
518*4882a593Smuzhiyun {
519*4882a593Smuzhiyun struct stk8ba50_data *data;
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun data = iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun return stk8ba50_set_power(data, STK8BA50_MODE_NORMAL);
524*4882a593Smuzhiyun }
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(stk8ba50_pm_ops, stk8ba50_suspend, stk8ba50_resume);
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun #define STK8BA50_PM_OPS (&stk8ba50_pm_ops)
529*4882a593Smuzhiyun #else
530*4882a593Smuzhiyun #define STK8BA50_PM_OPS NULL
531*4882a593Smuzhiyun #endif
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun static const struct i2c_device_id stk8ba50_i2c_id[] = {
534*4882a593Smuzhiyun {"stk8ba50", 0},
535*4882a593Smuzhiyun {}
536*4882a593Smuzhiyun };
537*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, stk8ba50_i2c_id);
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun static const struct acpi_device_id stk8ba50_acpi_id[] = {
540*4882a593Smuzhiyun {"STK8BA50", 0},
541*4882a593Smuzhiyun {}
542*4882a593Smuzhiyun };
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, stk8ba50_acpi_id);
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun static struct i2c_driver stk8ba50_driver = {
547*4882a593Smuzhiyun .driver = {
548*4882a593Smuzhiyun .name = "stk8ba50",
549*4882a593Smuzhiyun .pm = STK8BA50_PM_OPS,
550*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(stk8ba50_acpi_id),
551*4882a593Smuzhiyun },
552*4882a593Smuzhiyun .probe = stk8ba50_probe,
553*4882a593Smuzhiyun .remove = stk8ba50_remove,
554*4882a593Smuzhiyun .id_table = stk8ba50_i2c_id,
555*4882a593Smuzhiyun };
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun module_i2c_driver(stk8ba50_driver);
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun MODULE_AUTHOR("Tiberiu Breana <tiberiu.a.breana@intel.com>");
560*4882a593Smuzhiyun MODULE_DESCRIPTION("STK8BA50 3-Axis Accelerometer driver");
561*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
562