1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Freescale MMA9553L Intelligent Pedometer driver
4*4882a593Smuzhiyun * Copyright (c) 2014, Intel Corporation.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/i2c.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun #include <linux/acpi.h>
12*4882a593Smuzhiyun #include <linux/iio/iio.h>
13*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
14*4882a593Smuzhiyun #include <linux/iio/events.h>
15*4882a593Smuzhiyun #include <linux/pm_runtime.h>
16*4882a593Smuzhiyun #include "mma9551_core.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #define MMA9553_DRV_NAME "mma9553"
19*4882a593Smuzhiyun #define MMA9553_IRQ_NAME "mma9553_event"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /* Pedometer configuration registers (R/W) */
22*4882a593Smuzhiyun #define MMA9553_REG_CONF_SLEEPMIN 0x00
23*4882a593Smuzhiyun #define MMA9553_REG_CONF_SLEEPMAX 0x02
24*4882a593Smuzhiyun #define MMA9553_REG_CONF_SLEEPTHD 0x04
25*4882a593Smuzhiyun #define MMA9553_MASK_CONF_WORD GENMASK(15, 0)
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define MMA9553_REG_CONF_CONF_STEPLEN 0x06
28*4882a593Smuzhiyun #define MMA9553_MASK_CONF_CONFIG BIT(15)
29*4882a593Smuzhiyun #define MMA9553_MASK_CONF_ACT_DBCNTM BIT(14)
30*4882a593Smuzhiyun #define MMA9553_MASK_CONF_SLP_DBCNTM BIT(13)
31*4882a593Smuzhiyun #define MMA9553_MASK_CONF_STEPLEN GENMASK(7, 0)
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define MMA9553_REG_CONF_HEIGHT_WEIGHT 0x08
34*4882a593Smuzhiyun #define MMA9553_MASK_CONF_HEIGHT GENMASK(15, 8)
35*4882a593Smuzhiyun #define MMA9553_MASK_CONF_WEIGHT GENMASK(7, 0)
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define MMA9553_REG_CONF_FILTER 0x0A
38*4882a593Smuzhiyun #define MMA9553_MASK_CONF_FILTSTEP GENMASK(15, 8)
39*4882a593Smuzhiyun #define MMA9553_MASK_CONF_MALE BIT(7)
40*4882a593Smuzhiyun #define MMA9553_MASK_CONF_FILTTIME GENMASK(6, 0)
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #define MMA9553_REG_CONF_SPEED_STEP 0x0C
43*4882a593Smuzhiyun #define MMA9553_MASK_CONF_SPDPRD GENMASK(15, 8)
44*4882a593Smuzhiyun #define MMA9553_MASK_CONF_STEPCOALESCE GENMASK(7, 0)
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #define MMA9553_REG_CONF_ACTTHD 0x0E
47*4882a593Smuzhiyun #define MMA9553_MAX_ACTTHD GENMASK(15, 0)
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Pedometer status registers (R-only) */
50*4882a593Smuzhiyun #define MMA9553_REG_STATUS 0x00
51*4882a593Smuzhiyun #define MMA9553_MASK_STATUS_MRGFL BIT(15)
52*4882a593Smuzhiyun #define MMA9553_MASK_STATUS_SUSPCHG BIT(14)
53*4882a593Smuzhiyun #define MMA9553_MASK_STATUS_STEPCHG BIT(13)
54*4882a593Smuzhiyun #define MMA9553_MASK_STATUS_ACTCHG BIT(12)
55*4882a593Smuzhiyun #define MMA9553_MASK_STATUS_SUSP BIT(11)
56*4882a593Smuzhiyun #define MMA9553_MASK_STATUS_ACTIVITY GENMASK(10, 8)
57*4882a593Smuzhiyun #define MMA9553_MASK_STATUS_VERSION GENMASK(7, 0)
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #define MMA9553_REG_STEPCNT 0x02
60*4882a593Smuzhiyun #define MMA9553_REG_DISTANCE 0x04
61*4882a593Smuzhiyun #define MMA9553_REG_SPEED 0x06
62*4882a593Smuzhiyun #define MMA9553_REG_CALORIES 0x08
63*4882a593Smuzhiyun #define MMA9553_REG_SLEEPCNT 0x0A
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Pedometer events are always mapped to this pin. */
66*4882a593Smuzhiyun #define MMA9553_DEFAULT_GPIO_PIN mma9551_gpio6
67*4882a593Smuzhiyun #define MMA9553_DEFAULT_GPIO_POLARITY 0
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* Bitnum used for GPIO configuration = bit number in high status byte */
70*4882a593Smuzhiyun #define MMA9553_STATUS_TO_BITNUM(bit) (ffs(bit) - 9)
71*4882a593Smuzhiyun #define MMA9553_MAX_BITNUM MMA9553_STATUS_TO_BITNUM(BIT(16))
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #define MMA9553_DEFAULT_SAMPLE_RATE 30 /* Hz */
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /*
76*4882a593Smuzhiyun * The internal activity level must be stable for ACTTHD samples before
77*4882a593Smuzhiyun * ACTIVITY is updated. The ACTIVITY variable contains the current activity
78*4882a593Smuzhiyun * level and is updated every time a step is detected or once a second
79*4882a593Smuzhiyun * if there are no steps.
80*4882a593Smuzhiyun */
81*4882a593Smuzhiyun #define MMA9553_ACTIVITY_THD_TO_SEC(thd) ((thd) / MMA9553_DEFAULT_SAMPLE_RATE)
82*4882a593Smuzhiyun #define MMA9553_ACTIVITY_SEC_TO_THD(sec) ((sec) * MMA9553_DEFAULT_SAMPLE_RATE)
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /*
85*4882a593Smuzhiyun * Autonomously suspend pedometer if acceleration vector magnitude
86*4882a593Smuzhiyun * is near 1g (4096 at 0.244 mg/LSB resolution) for 30 seconds.
87*4882a593Smuzhiyun */
88*4882a593Smuzhiyun #define MMA9553_DEFAULT_SLEEPMIN 3688 /* 0,9 g */
89*4882a593Smuzhiyun #define MMA9553_DEFAULT_SLEEPMAX 4508 /* 1,1 g */
90*4882a593Smuzhiyun #define MMA9553_DEFAULT_SLEEPTHD (MMA9553_DEFAULT_SAMPLE_RATE * 30)
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #define MMA9553_CONFIG_RETRIES 2
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* Status register - activity field */
95*4882a593Smuzhiyun enum activity_level {
96*4882a593Smuzhiyun ACTIVITY_UNKNOWN,
97*4882a593Smuzhiyun ACTIVITY_REST,
98*4882a593Smuzhiyun ACTIVITY_WALKING,
99*4882a593Smuzhiyun ACTIVITY_JOGGING,
100*4882a593Smuzhiyun ACTIVITY_RUNNING,
101*4882a593Smuzhiyun };
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun static struct mma9553_event_info {
104*4882a593Smuzhiyun enum iio_chan_type type;
105*4882a593Smuzhiyun enum iio_modifier mod;
106*4882a593Smuzhiyun enum iio_event_direction dir;
107*4882a593Smuzhiyun } mma9553_events_info[] = {
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun .type = IIO_STEPS,
110*4882a593Smuzhiyun .mod = IIO_NO_MOD,
111*4882a593Smuzhiyun .dir = IIO_EV_DIR_NONE,
112*4882a593Smuzhiyun },
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun .type = IIO_ACTIVITY,
115*4882a593Smuzhiyun .mod = IIO_MOD_STILL,
116*4882a593Smuzhiyun .dir = IIO_EV_DIR_RISING,
117*4882a593Smuzhiyun },
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun .type = IIO_ACTIVITY,
120*4882a593Smuzhiyun .mod = IIO_MOD_STILL,
121*4882a593Smuzhiyun .dir = IIO_EV_DIR_FALLING,
122*4882a593Smuzhiyun },
123*4882a593Smuzhiyun {
124*4882a593Smuzhiyun .type = IIO_ACTIVITY,
125*4882a593Smuzhiyun .mod = IIO_MOD_WALKING,
126*4882a593Smuzhiyun .dir = IIO_EV_DIR_RISING,
127*4882a593Smuzhiyun },
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun .type = IIO_ACTIVITY,
130*4882a593Smuzhiyun .mod = IIO_MOD_WALKING,
131*4882a593Smuzhiyun .dir = IIO_EV_DIR_FALLING,
132*4882a593Smuzhiyun },
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun .type = IIO_ACTIVITY,
135*4882a593Smuzhiyun .mod = IIO_MOD_JOGGING,
136*4882a593Smuzhiyun .dir = IIO_EV_DIR_RISING,
137*4882a593Smuzhiyun },
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun .type = IIO_ACTIVITY,
140*4882a593Smuzhiyun .mod = IIO_MOD_JOGGING,
141*4882a593Smuzhiyun .dir = IIO_EV_DIR_FALLING,
142*4882a593Smuzhiyun },
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun .type = IIO_ACTIVITY,
145*4882a593Smuzhiyun .mod = IIO_MOD_RUNNING,
146*4882a593Smuzhiyun .dir = IIO_EV_DIR_RISING,
147*4882a593Smuzhiyun },
148*4882a593Smuzhiyun {
149*4882a593Smuzhiyun .type = IIO_ACTIVITY,
150*4882a593Smuzhiyun .mod = IIO_MOD_RUNNING,
151*4882a593Smuzhiyun .dir = IIO_EV_DIR_FALLING,
152*4882a593Smuzhiyun },
153*4882a593Smuzhiyun };
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun #define MMA9553_EVENTS_INFO_SIZE ARRAY_SIZE(mma9553_events_info)
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun struct mma9553_event {
158*4882a593Smuzhiyun struct mma9553_event_info *info;
159*4882a593Smuzhiyun bool enabled;
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun struct mma9553_conf_regs {
163*4882a593Smuzhiyun u16 sleepmin;
164*4882a593Smuzhiyun u16 sleepmax;
165*4882a593Smuzhiyun u16 sleepthd;
166*4882a593Smuzhiyun u16 config;
167*4882a593Smuzhiyun u16 height_weight;
168*4882a593Smuzhiyun u16 filter;
169*4882a593Smuzhiyun u16 speed_step;
170*4882a593Smuzhiyun u16 actthd;
171*4882a593Smuzhiyun } __packed;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun struct mma9553_data {
174*4882a593Smuzhiyun struct i2c_client *client;
175*4882a593Smuzhiyun /*
176*4882a593Smuzhiyun * 1. Serialize access to HW (requested by mma9551_core API).
177*4882a593Smuzhiyun * 2. Serialize sequences that power on/off the device and access HW.
178*4882a593Smuzhiyun */
179*4882a593Smuzhiyun struct mutex mutex;
180*4882a593Smuzhiyun struct mma9553_conf_regs conf;
181*4882a593Smuzhiyun struct mma9553_event events[MMA9553_EVENTS_INFO_SIZE];
182*4882a593Smuzhiyun int num_events;
183*4882a593Smuzhiyun u8 gpio_bitnum;
184*4882a593Smuzhiyun /*
185*4882a593Smuzhiyun * This is used for all features that depend on step count:
186*4882a593Smuzhiyun * step count, distance, speed, calories.
187*4882a593Smuzhiyun */
188*4882a593Smuzhiyun bool stepcnt_enabled;
189*4882a593Smuzhiyun u16 stepcnt;
190*4882a593Smuzhiyun u8 activity;
191*4882a593Smuzhiyun s64 timestamp;
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun
mma9553_get_bits(u16 val,u16 mask)194*4882a593Smuzhiyun static u8 mma9553_get_bits(u16 val, u16 mask)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun return (val & mask) >> (ffs(mask) - 1);
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
mma9553_set_bits(u16 current_val,u16 val,u16 mask)199*4882a593Smuzhiyun static u16 mma9553_set_bits(u16 current_val, u16 val, u16 mask)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun return (current_val & ~mask) | (val << (ffs(mask) - 1));
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
mma9553_activity_to_mod(enum activity_level activity)204*4882a593Smuzhiyun static enum iio_modifier mma9553_activity_to_mod(enum activity_level activity)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun switch (activity) {
207*4882a593Smuzhiyun case ACTIVITY_RUNNING:
208*4882a593Smuzhiyun return IIO_MOD_RUNNING;
209*4882a593Smuzhiyun case ACTIVITY_JOGGING:
210*4882a593Smuzhiyun return IIO_MOD_JOGGING;
211*4882a593Smuzhiyun case ACTIVITY_WALKING:
212*4882a593Smuzhiyun return IIO_MOD_WALKING;
213*4882a593Smuzhiyun case ACTIVITY_REST:
214*4882a593Smuzhiyun return IIO_MOD_STILL;
215*4882a593Smuzhiyun case ACTIVITY_UNKNOWN:
216*4882a593Smuzhiyun default:
217*4882a593Smuzhiyun return IIO_NO_MOD;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
mma9553_init_events(struct mma9553_data * data)221*4882a593Smuzhiyun static void mma9553_init_events(struct mma9553_data *data)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun int i;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun data->num_events = MMA9553_EVENTS_INFO_SIZE;
226*4882a593Smuzhiyun for (i = 0; i < data->num_events; i++) {
227*4882a593Smuzhiyun data->events[i].info = &mma9553_events_info[i];
228*4882a593Smuzhiyun data->events[i].enabled = false;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
mma9553_get_event(struct mma9553_data * data,enum iio_chan_type type,enum iio_modifier mod,enum iio_event_direction dir)232*4882a593Smuzhiyun static struct mma9553_event *mma9553_get_event(struct mma9553_data *data,
233*4882a593Smuzhiyun enum iio_chan_type type,
234*4882a593Smuzhiyun enum iio_modifier mod,
235*4882a593Smuzhiyun enum iio_event_direction dir)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun int i;
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun for (i = 0; i < data->num_events; i++)
240*4882a593Smuzhiyun if (data->events[i].info->type == type &&
241*4882a593Smuzhiyun data->events[i].info->mod == mod &&
242*4882a593Smuzhiyun data->events[i].info->dir == dir)
243*4882a593Smuzhiyun return &data->events[i];
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun return NULL;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
mma9553_is_any_event_enabled(struct mma9553_data * data,bool check_type,enum iio_chan_type type)248*4882a593Smuzhiyun static bool mma9553_is_any_event_enabled(struct mma9553_data *data,
249*4882a593Smuzhiyun bool check_type,
250*4882a593Smuzhiyun enum iio_chan_type type)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun int i;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun for (i = 0; i < data->num_events; i++)
255*4882a593Smuzhiyun if ((check_type && data->events[i].info->type == type &&
256*4882a593Smuzhiyun data->events[i].enabled) ||
257*4882a593Smuzhiyun (!check_type && data->events[i].enabled))
258*4882a593Smuzhiyun return true;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun return false;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
mma9553_set_config(struct mma9553_data * data,u16 reg,u16 * p_reg_val,u16 val,u16 mask)263*4882a593Smuzhiyun static int mma9553_set_config(struct mma9553_data *data, u16 reg,
264*4882a593Smuzhiyun u16 *p_reg_val, u16 val, u16 mask)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun int ret, retries;
267*4882a593Smuzhiyun u16 reg_val, config;
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun reg_val = *p_reg_val;
270*4882a593Smuzhiyun if (val == mma9553_get_bits(reg_val, mask))
271*4882a593Smuzhiyun return 0;
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun reg_val = mma9553_set_bits(reg_val, val, mask);
274*4882a593Smuzhiyun ret = mma9551_write_config_word(data->client, MMA9551_APPID_PEDOMETER,
275*4882a593Smuzhiyun reg, reg_val);
276*4882a593Smuzhiyun if (ret < 0) {
277*4882a593Smuzhiyun dev_err(&data->client->dev,
278*4882a593Smuzhiyun "error writing config register 0x%x\n", reg);
279*4882a593Smuzhiyun return ret;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun *p_reg_val = reg_val;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun /* Reinitializes the pedometer with current configuration values */
285*4882a593Smuzhiyun config = mma9553_set_bits(data->conf.config, 1,
286*4882a593Smuzhiyun MMA9553_MASK_CONF_CONFIG);
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun ret = mma9551_write_config_word(data->client, MMA9551_APPID_PEDOMETER,
289*4882a593Smuzhiyun MMA9553_REG_CONF_CONF_STEPLEN, config);
290*4882a593Smuzhiyun if (ret < 0) {
291*4882a593Smuzhiyun dev_err(&data->client->dev,
292*4882a593Smuzhiyun "error writing config register 0x%x\n",
293*4882a593Smuzhiyun MMA9553_REG_CONF_CONF_STEPLEN);
294*4882a593Smuzhiyun return ret;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun retries = MMA9553_CONFIG_RETRIES;
298*4882a593Smuzhiyun do {
299*4882a593Smuzhiyun mma9551_sleep(MMA9553_DEFAULT_SAMPLE_RATE);
300*4882a593Smuzhiyun ret = mma9551_read_config_word(data->client,
301*4882a593Smuzhiyun MMA9551_APPID_PEDOMETER,
302*4882a593Smuzhiyun MMA9553_REG_CONF_CONF_STEPLEN,
303*4882a593Smuzhiyun &config);
304*4882a593Smuzhiyun if (ret < 0)
305*4882a593Smuzhiyun return ret;
306*4882a593Smuzhiyun } while (mma9553_get_bits(config, MMA9553_MASK_CONF_CONFIG) &&
307*4882a593Smuzhiyun --retries > 0);
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun return 0;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
mma9553_read_activity_stepcnt(struct mma9553_data * data,u8 * activity,u16 * stepcnt)312*4882a593Smuzhiyun static int mma9553_read_activity_stepcnt(struct mma9553_data *data,
313*4882a593Smuzhiyun u8 *activity, u16 *stepcnt)
314*4882a593Smuzhiyun {
315*4882a593Smuzhiyun u16 buf[2];
316*4882a593Smuzhiyun int ret;
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun ret = mma9551_read_status_words(data->client, MMA9551_APPID_PEDOMETER,
319*4882a593Smuzhiyun MMA9553_REG_STATUS, ARRAY_SIZE(buf),
320*4882a593Smuzhiyun buf);
321*4882a593Smuzhiyun if (ret < 0) {
322*4882a593Smuzhiyun dev_err(&data->client->dev,
323*4882a593Smuzhiyun "error reading status and stepcnt\n");
324*4882a593Smuzhiyun return ret;
325*4882a593Smuzhiyun }
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun *activity = mma9553_get_bits(buf[0], MMA9553_MASK_STATUS_ACTIVITY);
328*4882a593Smuzhiyun *stepcnt = buf[1];
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun return 0;
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun
mma9553_conf_gpio(struct mma9553_data * data)333*4882a593Smuzhiyun static int mma9553_conf_gpio(struct mma9553_data *data)
334*4882a593Smuzhiyun {
335*4882a593Smuzhiyun u8 bitnum = 0, appid = MMA9551_APPID_PEDOMETER;
336*4882a593Smuzhiyun int ret;
337*4882a593Smuzhiyun struct mma9553_event *ev_step_detect;
338*4882a593Smuzhiyun bool activity_enabled;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun activity_enabled = mma9553_is_any_event_enabled(data, true,
341*4882a593Smuzhiyun IIO_ACTIVITY);
342*4882a593Smuzhiyun ev_step_detect = mma9553_get_event(data, IIO_STEPS, IIO_NO_MOD,
343*4882a593Smuzhiyun IIO_EV_DIR_NONE);
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun /*
346*4882a593Smuzhiyun * If both step detector and activity are enabled, use the MRGFL bit.
347*4882a593Smuzhiyun * This bit is the logical OR of the SUSPCHG, STEPCHG, and ACTCHG flags.
348*4882a593Smuzhiyun */
349*4882a593Smuzhiyun if (activity_enabled && ev_step_detect->enabled)
350*4882a593Smuzhiyun bitnum = MMA9553_STATUS_TO_BITNUM(MMA9553_MASK_STATUS_MRGFL);
351*4882a593Smuzhiyun else if (ev_step_detect->enabled)
352*4882a593Smuzhiyun bitnum = MMA9553_STATUS_TO_BITNUM(MMA9553_MASK_STATUS_STEPCHG);
353*4882a593Smuzhiyun else if (activity_enabled)
354*4882a593Smuzhiyun bitnum = MMA9553_STATUS_TO_BITNUM(MMA9553_MASK_STATUS_ACTCHG);
355*4882a593Smuzhiyun else /* Reset */
356*4882a593Smuzhiyun appid = MMA9551_APPID_NONE;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun if (data->gpio_bitnum == bitnum)
359*4882a593Smuzhiyun return 0;
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun /* Save initial values for activity and stepcnt */
362*4882a593Smuzhiyun if (activity_enabled || ev_step_detect->enabled) {
363*4882a593Smuzhiyun ret = mma9553_read_activity_stepcnt(data, &data->activity,
364*4882a593Smuzhiyun &data->stepcnt);
365*4882a593Smuzhiyun if (ret < 0)
366*4882a593Smuzhiyun return ret;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun ret = mma9551_gpio_config(data->client, MMA9553_DEFAULT_GPIO_PIN, appid,
370*4882a593Smuzhiyun bitnum, MMA9553_DEFAULT_GPIO_POLARITY);
371*4882a593Smuzhiyun if (ret < 0)
372*4882a593Smuzhiyun return ret;
373*4882a593Smuzhiyun data->gpio_bitnum = bitnum;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun return 0;
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun
mma9553_init(struct mma9553_data * data)378*4882a593Smuzhiyun static int mma9553_init(struct mma9553_data *data)
379*4882a593Smuzhiyun {
380*4882a593Smuzhiyun int ret;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun ret = mma9551_read_version(data->client);
383*4882a593Smuzhiyun if (ret)
384*4882a593Smuzhiyun return ret;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun /*
387*4882a593Smuzhiyun * Read all the pedometer configuration registers. This is used as
388*4882a593Smuzhiyun * a device identification command to differentiate the MMA9553L
389*4882a593Smuzhiyun * from the MMA9550L.
390*4882a593Smuzhiyun */
391*4882a593Smuzhiyun ret = mma9551_read_config_words(data->client, MMA9551_APPID_PEDOMETER,
392*4882a593Smuzhiyun MMA9553_REG_CONF_SLEEPMIN,
393*4882a593Smuzhiyun sizeof(data->conf) / sizeof(u16),
394*4882a593Smuzhiyun (u16 *)&data->conf);
395*4882a593Smuzhiyun if (ret < 0) {
396*4882a593Smuzhiyun dev_err(&data->client->dev,
397*4882a593Smuzhiyun "failed to read configuration registers\n");
398*4882a593Smuzhiyun return ret;
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun /* Reset GPIO */
402*4882a593Smuzhiyun data->gpio_bitnum = MMA9553_MAX_BITNUM;
403*4882a593Smuzhiyun ret = mma9553_conf_gpio(data);
404*4882a593Smuzhiyun if (ret < 0)
405*4882a593Smuzhiyun return ret;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun ret = mma9551_app_reset(data->client, MMA9551_RSC_PED);
408*4882a593Smuzhiyun if (ret < 0)
409*4882a593Smuzhiyun return ret;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun /* Init config registers */
412*4882a593Smuzhiyun data->conf.sleepmin = MMA9553_DEFAULT_SLEEPMIN;
413*4882a593Smuzhiyun data->conf.sleepmax = MMA9553_DEFAULT_SLEEPMAX;
414*4882a593Smuzhiyun data->conf.sleepthd = MMA9553_DEFAULT_SLEEPTHD;
415*4882a593Smuzhiyun data->conf.config = mma9553_set_bits(data->conf.config, 1,
416*4882a593Smuzhiyun MMA9553_MASK_CONF_CONFIG);
417*4882a593Smuzhiyun /*
418*4882a593Smuzhiyun * Clear the activity debounce counter when the activity level changes,
419*4882a593Smuzhiyun * so that the confidence level applies for any activity level.
420*4882a593Smuzhiyun */
421*4882a593Smuzhiyun data->conf.config = mma9553_set_bits(data->conf.config, 1,
422*4882a593Smuzhiyun MMA9553_MASK_CONF_ACT_DBCNTM);
423*4882a593Smuzhiyun ret = mma9551_write_config_words(data->client, MMA9551_APPID_PEDOMETER,
424*4882a593Smuzhiyun MMA9553_REG_CONF_SLEEPMIN,
425*4882a593Smuzhiyun sizeof(data->conf) / sizeof(u16),
426*4882a593Smuzhiyun (u16 *)&data->conf);
427*4882a593Smuzhiyun if (ret < 0) {
428*4882a593Smuzhiyun dev_err(&data->client->dev,
429*4882a593Smuzhiyun "failed to write configuration registers\n");
430*4882a593Smuzhiyun return ret;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun return mma9551_set_device_state(data->client, true);
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
mma9553_read_status_word(struct mma9553_data * data,u16 reg,u16 * tmp)436*4882a593Smuzhiyun static int mma9553_read_status_word(struct mma9553_data *data, u16 reg,
437*4882a593Smuzhiyun u16 *tmp)
438*4882a593Smuzhiyun {
439*4882a593Smuzhiyun bool powered_on;
440*4882a593Smuzhiyun int ret;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun /*
443*4882a593Smuzhiyun * The HW only counts steps and other dependent
444*4882a593Smuzhiyun * parameters (speed, distance, calories, activity)
445*4882a593Smuzhiyun * if power is on (from enabling an event or the
446*4882a593Smuzhiyun * step counter).
447*4882a593Smuzhiyun */
448*4882a593Smuzhiyun powered_on = mma9553_is_any_event_enabled(data, false, 0) ||
449*4882a593Smuzhiyun data->stepcnt_enabled;
450*4882a593Smuzhiyun if (!powered_on) {
451*4882a593Smuzhiyun dev_err(&data->client->dev, "No channels enabled\n");
452*4882a593Smuzhiyun return -EINVAL;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun mutex_lock(&data->mutex);
456*4882a593Smuzhiyun ret = mma9551_read_status_word(data->client, MMA9551_APPID_PEDOMETER,
457*4882a593Smuzhiyun reg, tmp);
458*4882a593Smuzhiyun mutex_unlock(&data->mutex);
459*4882a593Smuzhiyun return ret;
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun
mma9553_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)462*4882a593Smuzhiyun static int mma9553_read_raw(struct iio_dev *indio_dev,
463*4882a593Smuzhiyun struct iio_chan_spec const *chan,
464*4882a593Smuzhiyun int *val, int *val2, long mask)
465*4882a593Smuzhiyun {
466*4882a593Smuzhiyun struct mma9553_data *data = iio_priv(indio_dev);
467*4882a593Smuzhiyun int ret;
468*4882a593Smuzhiyun u16 tmp;
469*4882a593Smuzhiyun u8 activity;
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun switch (mask) {
472*4882a593Smuzhiyun case IIO_CHAN_INFO_PROCESSED:
473*4882a593Smuzhiyun switch (chan->type) {
474*4882a593Smuzhiyun case IIO_STEPS:
475*4882a593Smuzhiyun ret = mma9553_read_status_word(data,
476*4882a593Smuzhiyun MMA9553_REG_STEPCNT,
477*4882a593Smuzhiyun &tmp);
478*4882a593Smuzhiyun if (ret < 0)
479*4882a593Smuzhiyun return ret;
480*4882a593Smuzhiyun *val = tmp;
481*4882a593Smuzhiyun return IIO_VAL_INT;
482*4882a593Smuzhiyun case IIO_DISTANCE:
483*4882a593Smuzhiyun ret = mma9553_read_status_word(data,
484*4882a593Smuzhiyun MMA9553_REG_DISTANCE,
485*4882a593Smuzhiyun &tmp);
486*4882a593Smuzhiyun if (ret < 0)
487*4882a593Smuzhiyun return ret;
488*4882a593Smuzhiyun *val = tmp;
489*4882a593Smuzhiyun return IIO_VAL_INT;
490*4882a593Smuzhiyun case IIO_ACTIVITY:
491*4882a593Smuzhiyun ret = mma9553_read_status_word(data,
492*4882a593Smuzhiyun MMA9553_REG_STATUS,
493*4882a593Smuzhiyun &tmp);
494*4882a593Smuzhiyun if (ret < 0)
495*4882a593Smuzhiyun return ret;
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun activity =
498*4882a593Smuzhiyun mma9553_get_bits(tmp, MMA9553_MASK_STATUS_ACTIVITY);
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun /*
501*4882a593Smuzhiyun * The device does not support confidence value levels,
502*4882a593Smuzhiyun * so we will always have 100% for current activity and
503*4882a593Smuzhiyun * 0% for the others.
504*4882a593Smuzhiyun */
505*4882a593Smuzhiyun if (chan->channel2 == mma9553_activity_to_mod(activity))
506*4882a593Smuzhiyun *val = 100;
507*4882a593Smuzhiyun else
508*4882a593Smuzhiyun *val = 0;
509*4882a593Smuzhiyun return IIO_VAL_INT;
510*4882a593Smuzhiyun default:
511*4882a593Smuzhiyun return -EINVAL;
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
514*4882a593Smuzhiyun switch (chan->type) {
515*4882a593Smuzhiyun case IIO_VELOCITY: /* m/h */
516*4882a593Smuzhiyun if (chan->channel2 != IIO_MOD_ROOT_SUM_SQUARED_X_Y_Z)
517*4882a593Smuzhiyun return -EINVAL;
518*4882a593Smuzhiyun ret = mma9553_read_status_word(data,
519*4882a593Smuzhiyun MMA9553_REG_SPEED,
520*4882a593Smuzhiyun &tmp);
521*4882a593Smuzhiyun if (ret < 0)
522*4882a593Smuzhiyun return ret;
523*4882a593Smuzhiyun *val = tmp;
524*4882a593Smuzhiyun return IIO_VAL_INT;
525*4882a593Smuzhiyun case IIO_ENERGY: /* Cal or kcal */
526*4882a593Smuzhiyun ret = mma9553_read_status_word(data,
527*4882a593Smuzhiyun MMA9553_REG_CALORIES,
528*4882a593Smuzhiyun &tmp);
529*4882a593Smuzhiyun if (ret < 0)
530*4882a593Smuzhiyun return ret;
531*4882a593Smuzhiyun *val = tmp;
532*4882a593Smuzhiyun return IIO_VAL_INT;
533*4882a593Smuzhiyun case IIO_ACCEL:
534*4882a593Smuzhiyun mutex_lock(&data->mutex);
535*4882a593Smuzhiyun ret = mma9551_read_accel_chan(data->client,
536*4882a593Smuzhiyun chan, val, val2);
537*4882a593Smuzhiyun mutex_unlock(&data->mutex);
538*4882a593Smuzhiyun return ret;
539*4882a593Smuzhiyun default:
540*4882a593Smuzhiyun return -EINVAL;
541*4882a593Smuzhiyun }
542*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
543*4882a593Smuzhiyun switch (chan->type) {
544*4882a593Smuzhiyun case IIO_VELOCITY: /* m/h to m/s */
545*4882a593Smuzhiyun if (chan->channel2 != IIO_MOD_ROOT_SUM_SQUARED_X_Y_Z)
546*4882a593Smuzhiyun return -EINVAL;
547*4882a593Smuzhiyun *val = 0;
548*4882a593Smuzhiyun *val2 = 277; /* 0.000277 */
549*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
550*4882a593Smuzhiyun case IIO_ENERGY: /* Cal or kcal to J */
551*4882a593Smuzhiyun *val = 4184;
552*4882a593Smuzhiyun return IIO_VAL_INT;
553*4882a593Smuzhiyun case IIO_ACCEL:
554*4882a593Smuzhiyun return mma9551_read_accel_scale(val, val2);
555*4882a593Smuzhiyun default:
556*4882a593Smuzhiyun return -EINVAL;
557*4882a593Smuzhiyun }
558*4882a593Smuzhiyun case IIO_CHAN_INFO_ENABLE:
559*4882a593Smuzhiyun *val = data->stepcnt_enabled;
560*4882a593Smuzhiyun return IIO_VAL_INT;
561*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBHEIGHT:
562*4882a593Smuzhiyun tmp = mma9553_get_bits(data->conf.height_weight,
563*4882a593Smuzhiyun MMA9553_MASK_CONF_HEIGHT);
564*4882a593Smuzhiyun *val = tmp / 100; /* cm to m */
565*4882a593Smuzhiyun *val2 = (tmp % 100) * 10000;
566*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
567*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBWEIGHT:
568*4882a593Smuzhiyun *val = mma9553_get_bits(data->conf.height_weight,
569*4882a593Smuzhiyun MMA9553_MASK_CONF_WEIGHT);
570*4882a593Smuzhiyun return IIO_VAL_INT;
571*4882a593Smuzhiyun case IIO_CHAN_INFO_DEBOUNCE_COUNT:
572*4882a593Smuzhiyun switch (chan->type) {
573*4882a593Smuzhiyun case IIO_STEPS:
574*4882a593Smuzhiyun *val = mma9553_get_bits(data->conf.filter,
575*4882a593Smuzhiyun MMA9553_MASK_CONF_FILTSTEP);
576*4882a593Smuzhiyun return IIO_VAL_INT;
577*4882a593Smuzhiyun default:
578*4882a593Smuzhiyun return -EINVAL;
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun case IIO_CHAN_INFO_DEBOUNCE_TIME:
581*4882a593Smuzhiyun switch (chan->type) {
582*4882a593Smuzhiyun case IIO_STEPS:
583*4882a593Smuzhiyun *val = mma9553_get_bits(data->conf.filter,
584*4882a593Smuzhiyun MMA9553_MASK_CONF_FILTTIME);
585*4882a593Smuzhiyun return IIO_VAL_INT;
586*4882a593Smuzhiyun default:
587*4882a593Smuzhiyun return -EINVAL;
588*4882a593Smuzhiyun }
589*4882a593Smuzhiyun case IIO_CHAN_INFO_INT_TIME:
590*4882a593Smuzhiyun switch (chan->type) {
591*4882a593Smuzhiyun case IIO_VELOCITY:
592*4882a593Smuzhiyun if (chan->channel2 != IIO_MOD_ROOT_SUM_SQUARED_X_Y_Z)
593*4882a593Smuzhiyun return -EINVAL;
594*4882a593Smuzhiyun *val = mma9553_get_bits(data->conf.speed_step,
595*4882a593Smuzhiyun MMA9553_MASK_CONF_SPDPRD);
596*4882a593Smuzhiyun return IIO_VAL_INT;
597*4882a593Smuzhiyun default:
598*4882a593Smuzhiyun return -EINVAL;
599*4882a593Smuzhiyun }
600*4882a593Smuzhiyun default:
601*4882a593Smuzhiyun return -EINVAL;
602*4882a593Smuzhiyun }
603*4882a593Smuzhiyun }
604*4882a593Smuzhiyun
mma9553_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)605*4882a593Smuzhiyun static int mma9553_write_raw(struct iio_dev *indio_dev,
606*4882a593Smuzhiyun struct iio_chan_spec const *chan,
607*4882a593Smuzhiyun int val, int val2, long mask)
608*4882a593Smuzhiyun {
609*4882a593Smuzhiyun struct mma9553_data *data = iio_priv(indio_dev);
610*4882a593Smuzhiyun int ret, tmp;
611*4882a593Smuzhiyun
612*4882a593Smuzhiyun switch (mask) {
613*4882a593Smuzhiyun case IIO_CHAN_INFO_ENABLE:
614*4882a593Smuzhiyun if (data->stepcnt_enabled == !!val)
615*4882a593Smuzhiyun return 0;
616*4882a593Smuzhiyun mutex_lock(&data->mutex);
617*4882a593Smuzhiyun ret = mma9551_set_power_state(data->client, val);
618*4882a593Smuzhiyun if (ret < 0) {
619*4882a593Smuzhiyun mutex_unlock(&data->mutex);
620*4882a593Smuzhiyun return ret;
621*4882a593Smuzhiyun }
622*4882a593Smuzhiyun data->stepcnt_enabled = val;
623*4882a593Smuzhiyun mutex_unlock(&data->mutex);
624*4882a593Smuzhiyun return 0;
625*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBHEIGHT:
626*4882a593Smuzhiyun /* m to cm */
627*4882a593Smuzhiyun tmp = val * 100 + val2 / 10000;
628*4882a593Smuzhiyun if (tmp < 0 || tmp > 255)
629*4882a593Smuzhiyun return -EINVAL;
630*4882a593Smuzhiyun mutex_lock(&data->mutex);
631*4882a593Smuzhiyun ret = mma9553_set_config(data,
632*4882a593Smuzhiyun MMA9553_REG_CONF_HEIGHT_WEIGHT,
633*4882a593Smuzhiyun &data->conf.height_weight,
634*4882a593Smuzhiyun tmp, MMA9553_MASK_CONF_HEIGHT);
635*4882a593Smuzhiyun mutex_unlock(&data->mutex);
636*4882a593Smuzhiyun return ret;
637*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBWEIGHT:
638*4882a593Smuzhiyun if (val < 0 || val > 255)
639*4882a593Smuzhiyun return -EINVAL;
640*4882a593Smuzhiyun mutex_lock(&data->mutex);
641*4882a593Smuzhiyun ret = mma9553_set_config(data,
642*4882a593Smuzhiyun MMA9553_REG_CONF_HEIGHT_WEIGHT,
643*4882a593Smuzhiyun &data->conf.height_weight,
644*4882a593Smuzhiyun val, MMA9553_MASK_CONF_WEIGHT);
645*4882a593Smuzhiyun mutex_unlock(&data->mutex);
646*4882a593Smuzhiyun return ret;
647*4882a593Smuzhiyun case IIO_CHAN_INFO_DEBOUNCE_COUNT:
648*4882a593Smuzhiyun switch (chan->type) {
649*4882a593Smuzhiyun case IIO_STEPS:
650*4882a593Smuzhiyun /*
651*4882a593Smuzhiyun * Set to 0 to disable step filtering. If the value
652*4882a593Smuzhiyun * specified is greater than 6, then 6 will be used.
653*4882a593Smuzhiyun */
654*4882a593Smuzhiyun if (val < 0)
655*4882a593Smuzhiyun return -EINVAL;
656*4882a593Smuzhiyun if (val > 6)
657*4882a593Smuzhiyun val = 6;
658*4882a593Smuzhiyun mutex_lock(&data->mutex);
659*4882a593Smuzhiyun ret = mma9553_set_config(data, MMA9553_REG_CONF_FILTER,
660*4882a593Smuzhiyun &data->conf.filter, val,
661*4882a593Smuzhiyun MMA9553_MASK_CONF_FILTSTEP);
662*4882a593Smuzhiyun mutex_unlock(&data->mutex);
663*4882a593Smuzhiyun return ret;
664*4882a593Smuzhiyun default:
665*4882a593Smuzhiyun return -EINVAL;
666*4882a593Smuzhiyun }
667*4882a593Smuzhiyun case IIO_CHAN_INFO_DEBOUNCE_TIME:
668*4882a593Smuzhiyun switch (chan->type) {
669*4882a593Smuzhiyun case IIO_STEPS:
670*4882a593Smuzhiyun if (val < 0 || val > 127)
671*4882a593Smuzhiyun return -EINVAL;
672*4882a593Smuzhiyun mutex_lock(&data->mutex);
673*4882a593Smuzhiyun ret = mma9553_set_config(data, MMA9553_REG_CONF_FILTER,
674*4882a593Smuzhiyun &data->conf.filter, val,
675*4882a593Smuzhiyun MMA9553_MASK_CONF_FILTTIME);
676*4882a593Smuzhiyun mutex_unlock(&data->mutex);
677*4882a593Smuzhiyun return ret;
678*4882a593Smuzhiyun default:
679*4882a593Smuzhiyun return -EINVAL;
680*4882a593Smuzhiyun }
681*4882a593Smuzhiyun case IIO_CHAN_INFO_INT_TIME:
682*4882a593Smuzhiyun switch (chan->type) {
683*4882a593Smuzhiyun case IIO_VELOCITY:
684*4882a593Smuzhiyun if (chan->channel2 != IIO_MOD_ROOT_SUM_SQUARED_X_Y_Z)
685*4882a593Smuzhiyun return -EINVAL;
686*4882a593Smuzhiyun /*
687*4882a593Smuzhiyun * If set to a value greater than 5, then 5 will be
688*4882a593Smuzhiyun * used. Warning: Do not set SPDPRD to 0 or 1 as
689*4882a593Smuzhiyun * this may cause undesirable behavior.
690*4882a593Smuzhiyun */
691*4882a593Smuzhiyun if (val < 2)
692*4882a593Smuzhiyun return -EINVAL;
693*4882a593Smuzhiyun if (val > 5)
694*4882a593Smuzhiyun val = 5;
695*4882a593Smuzhiyun mutex_lock(&data->mutex);
696*4882a593Smuzhiyun ret = mma9553_set_config(data,
697*4882a593Smuzhiyun MMA9553_REG_CONF_SPEED_STEP,
698*4882a593Smuzhiyun &data->conf.speed_step, val,
699*4882a593Smuzhiyun MMA9553_MASK_CONF_SPDPRD);
700*4882a593Smuzhiyun mutex_unlock(&data->mutex);
701*4882a593Smuzhiyun return ret;
702*4882a593Smuzhiyun default:
703*4882a593Smuzhiyun return -EINVAL;
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun default:
706*4882a593Smuzhiyun return -EINVAL;
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun }
709*4882a593Smuzhiyun
mma9553_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)710*4882a593Smuzhiyun static int mma9553_read_event_config(struct iio_dev *indio_dev,
711*4882a593Smuzhiyun const struct iio_chan_spec *chan,
712*4882a593Smuzhiyun enum iio_event_type type,
713*4882a593Smuzhiyun enum iio_event_direction dir)
714*4882a593Smuzhiyun {
715*4882a593Smuzhiyun struct mma9553_data *data = iio_priv(indio_dev);
716*4882a593Smuzhiyun struct mma9553_event *event;
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun event = mma9553_get_event(data, chan->type, chan->channel2, dir);
719*4882a593Smuzhiyun if (!event)
720*4882a593Smuzhiyun return -EINVAL;
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun return event->enabled;
723*4882a593Smuzhiyun }
724*4882a593Smuzhiyun
mma9553_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)725*4882a593Smuzhiyun static int mma9553_write_event_config(struct iio_dev *indio_dev,
726*4882a593Smuzhiyun const struct iio_chan_spec *chan,
727*4882a593Smuzhiyun enum iio_event_type type,
728*4882a593Smuzhiyun enum iio_event_direction dir, int state)
729*4882a593Smuzhiyun {
730*4882a593Smuzhiyun struct mma9553_data *data = iio_priv(indio_dev);
731*4882a593Smuzhiyun struct mma9553_event *event;
732*4882a593Smuzhiyun int ret;
733*4882a593Smuzhiyun
734*4882a593Smuzhiyun event = mma9553_get_event(data, chan->type, chan->channel2, dir);
735*4882a593Smuzhiyun if (!event)
736*4882a593Smuzhiyun return -EINVAL;
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun if (event->enabled == state)
739*4882a593Smuzhiyun return 0;
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun mutex_lock(&data->mutex);
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun ret = mma9551_set_power_state(data->client, state);
744*4882a593Smuzhiyun if (ret < 0)
745*4882a593Smuzhiyun goto err_out;
746*4882a593Smuzhiyun event->enabled = state;
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun ret = mma9553_conf_gpio(data);
749*4882a593Smuzhiyun if (ret < 0)
750*4882a593Smuzhiyun goto err_conf_gpio;
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun mutex_unlock(&data->mutex);
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun return 0;
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun err_conf_gpio:
757*4882a593Smuzhiyun if (state) {
758*4882a593Smuzhiyun event->enabled = false;
759*4882a593Smuzhiyun mma9551_set_power_state(data->client, false);
760*4882a593Smuzhiyun }
761*4882a593Smuzhiyun err_out:
762*4882a593Smuzhiyun mutex_unlock(&data->mutex);
763*4882a593Smuzhiyun return ret;
764*4882a593Smuzhiyun }
765*4882a593Smuzhiyun
mma9553_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)766*4882a593Smuzhiyun static int mma9553_read_event_value(struct iio_dev *indio_dev,
767*4882a593Smuzhiyun const struct iio_chan_spec *chan,
768*4882a593Smuzhiyun enum iio_event_type type,
769*4882a593Smuzhiyun enum iio_event_direction dir,
770*4882a593Smuzhiyun enum iio_event_info info,
771*4882a593Smuzhiyun int *val, int *val2)
772*4882a593Smuzhiyun {
773*4882a593Smuzhiyun struct mma9553_data *data = iio_priv(indio_dev);
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun *val2 = 0;
776*4882a593Smuzhiyun switch (info) {
777*4882a593Smuzhiyun case IIO_EV_INFO_VALUE:
778*4882a593Smuzhiyun switch (chan->type) {
779*4882a593Smuzhiyun case IIO_STEPS:
780*4882a593Smuzhiyun *val = mma9553_get_bits(data->conf.speed_step,
781*4882a593Smuzhiyun MMA9553_MASK_CONF_STEPCOALESCE);
782*4882a593Smuzhiyun return IIO_VAL_INT;
783*4882a593Smuzhiyun case IIO_ACTIVITY:
784*4882a593Smuzhiyun /*
785*4882a593Smuzhiyun * The device does not support confidence value levels.
786*4882a593Smuzhiyun * We set an average of 50%.
787*4882a593Smuzhiyun */
788*4882a593Smuzhiyun *val = 50;
789*4882a593Smuzhiyun return IIO_VAL_INT;
790*4882a593Smuzhiyun default:
791*4882a593Smuzhiyun return -EINVAL;
792*4882a593Smuzhiyun }
793*4882a593Smuzhiyun case IIO_EV_INFO_PERIOD:
794*4882a593Smuzhiyun switch (chan->type) {
795*4882a593Smuzhiyun case IIO_ACTIVITY:
796*4882a593Smuzhiyun *val = MMA9553_ACTIVITY_THD_TO_SEC(data->conf.actthd);
797*4882a593Smuzhiyun return IIO_VAL_INT;
798*4882a593Smuzhiyun default:
799*4882a593Smuzhiyun return -EINVAL;
800*4882a593Smuzhiyun }
801*4882a593Smuzhiyun default:
802*4882a593Smuzhiyun return -EINVAL;
803*4882a593Smuzhiyun }
804*4882a593Smuzhiyun }
805*4882a593Smuzhiyun
mma9553_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)806*4882a593Smuzhiyun static int mma9553_write_event_value(struct iio_dev *indio_dev,
807*4882a593Smuzhiyun const struct iio_chan_spec *chan,
808*4882a593Smuzhiyun enum iio_event_type type,
809*4882a593Smuzhiyun enum iio_event_direction dir,
810*4882a593Smuzhiyun enum iio_event_info info,
811*4882a593Smuzhiyun int val, int val2)
812*4882a593Smuzhiyun {
813*4882a593Smuzhiyun struct mma9553_data *data = iio_priv(indio_dev);
814*4882a593Smuzhiyun int ret;
815*4882a593Smuzhiyun
816*4882a593Smuzhiyun switch (info) {
817*4882a593Smuzhiyun case IIO_EV_INFO_VALUE:
818*4882a593Smuzhiyun switch (chan->type) {
819*4882a593Smuzhiyun case IIO_STEPS:
820*4882a593Smuzhiyun if (val < 0 || val > 255)
821*4882a593Smuzhiyun return -EINVAL;
822*4882a593Smuzhiyun mutex_lock(&data->mutex);
823*4882a593Smuzhiyun ret = mma9553_set_config(data,
824*4882a593Smuzhiyun MMA9553_REG_CONF_SPEED_STEP,
825*4882a593Smuzhiyun &data->conf.speed_step, val,
826*4882a593Smuzhiyun MMA9553_MASK_CONF_STEPCOALESCE);
827*4882a593Smuzhiyun mutex_unlock(&data->mutex);
828*4882a593Smuzhiyun return ret;
829*4882a593Smuzhiyun default:
830*4882a593Smuzhiyun return -EINVAL;
831*4882a593Smuzhiyun }
832*4882a593Smuzhiyun case IIO_EV_INFO_PERIOD:
833*4882a593Smuzhiyun switch (chan->type) {
834*4882a593Smuzhiyun case IIO_ACTIVITY:
835*4882a593Smuzhiyun if (val < 0 || val > MMA9553_ACTIVITY_THD_TO_SEC(
836*4882a593Smuzhiyun MMA9553_MAX_ACTTHD))
837*4882a593Smuzhiyun return -EINVAL;
838*4882a593Smuzhiyun mutex_lock(&data->mutex);
839*4882a593Smuzhiyun ret = mma9553_set_config(data, MMA9553_REG_CONF_ACTTHD,
840*4882a593Smuzhiyun &data->conf.actthd,
841*4882a593Smuzhiyun MMA9553_ACTIVITY_SEC_TO_THD
842*4882a593Smuzhiyun (val), MMA9553_MASK_CONF_WORD);
843*4882a593Smuzhiyun mutex_unlock(&data->mutex);
844*4882a593Smuzhiyun return ret;
845*4882a593Smuzhiyun default:
846*4882a593Smuzhiyun return -EINVAL;
847*4882a593Smuzhiyun }
848*4882a593Smuzhiyun default:
849*4882a593Smuzhiyun return -EINVAL;
850*4882a593Smuzhiyun }
851*4882a593Smuzhiyun }
852*4882a593Smuzhiyun
mma9553_get_calibgender_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)853*4882a593Smuzhiyun static int mma9553_get_calibgender_mode(struct iio_dev *indio_dev,
854*4882a593Smuzhiyun const struct iio_chan_spec *chan)
855*4882a593Smuzhiyun {
856*4882a593Smuzhiyun struct mma9553_data *data = iio_priv(indio_dev);
857*4882a593Smuzhiyun u8 gender;
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun gender = mma9553_get_bits(data->conf.filter, MMA9553_MASK_CONF_MALE);
860*4882a593Smuzhiyun /*
861*4882a593Smuzhiyun * HW expects 0 for female and 1 for male,
862*4882a593Smuzhiyun * while iio index is 0 for male and 1 for female.
863*4882a593Smuzhiyun */
864*4882a593Smuzhiyun return !gender;
865*4882a593Smuzhiyun }
866*4882a593Smuzhiyun
mma9553_set_calibgender_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)867*4882a593Smuzhiyun static int mma9553_set_calibgender_mode(struct iio_dev *indio_dev,
868*4882a593Smuzhiyun const struct iio_chan_spec *chan,
869*4882a593Smuzhiyun unsigned int mode)
870*4882a593Smuzhiyun {
871*4882a593Smuzhiyun struct mma9553_data *data = iio_priv(indio_dev);
872*4882a593Smuzhiyun u8 gender = !mode;
873*4882a593Smuzhiyun int ret;
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun if ((mode != 0) && (mode != 1))
876*4882a593Smuzhiyun return -EINVAL;
877*4882a593Smuzhiyun mutex_lock(&data->mutex);
878*4882a593Smuzhiyun ret = mma9553_set_config(data, MMA9553_REG_CONF_FILTER,
879*4882a593Smuzhiyun &data->conf.filter, gender,
880*4882a593Smuzhiyun MMA9553_MASK_CONF_MALE);
881*4882a593Smuzhiyun mutex_unlock(&data->mutex);
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun return ret;
884*4882a593Smuzhiyun }
885*4882a593Smuzhiyun
886*4882a593Smuzhiyun static const struct iio_event_spec mma9553_step_event = {
887*4882a593Smuzhiyun .type = IIO_EV_TYPE_CHANGE,
888*4882a593Smuzhiyun .dir = IIO_EV_DIR_NONE,
889*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_VALUE),
890*4882a593Smuzhiyun };
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun static const struct iio_event_spec mma9553_activity_events[] = {
893*4882a593Smuzhiyun {
894*4882a593Smuzhiyun .type = IIO_EV_TYPE_THRESH,
895*4882a593Smuzhiyun .dir = IIO_EV_DIR_RISING,
896*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
897*4882a593Smuzhiyun BIT(IIO_EV_INFO_VALUE) |
898*4882a593Smuzhiyun BIT(IIO_EV_INFO_PERIOD),
899*4882a593Smuzhiyun },
900*4882a593Smuzhiyun {
901*4882a593Smuzhiyun .type = IIO_EV_TYPE_THRESH,
902*4882a593Smuzhiyun .dir = IIO_EV_DIR_FALLING,
903*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
904*4882a593Smuzhiyun BIT(IIO_EV_INFO_VALUE) |
905*4882a593Smuzhiyun BIT(IIO_EV_INFO_PERIOD),
906*4882a593Smuzhiyun },
907*4882a593Smuzhiyun };
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun static const char * const mma9553_calibgender_modes[] = { "male", "female" };
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun static const struct iio_enum mma9553_calibgender_enum = {
912*4882a593Smuzhiyun .items = mma9553_calibgender_modes,
913*4882a593Smuzhiyun .num_items = ARRAY_SIZE(mma9553_calibgender_modes),
914*4882a593Smuzhiyun .get = mma9553_get_calibgender_mode,
915*4882a593Smuzhiyun .set = mma9553_set_calibgender_mode,
916*4882a593Smuzhiyun };
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun static const struct iio_chan_spec_ext_info mma9553_ext_info[] = {
919*4882a593Smuzhiyun IIO_ENUM("calibgender", IIO_SHARED_BY_TYPE, &mma9553_calibgender_enum),
920*4882a593Smuzhiyun IIO_ENUM_AVAILABLE("calibgender", &mma9553_calibgender_enum),
921*4882a593Smuzhiyun {},
922*4882a593Smuzhiyun };
923*4882a593Smuzhiyun
924*4882a593Smuzhiyun #define MMA9553_PEDOMETER_CHANNEL(_type, _mask) { \
925*4882a593Smuzhiyun .type = _type, \
926*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_ENABLE) | \
927*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBHEIGHT) | \
928*4882a593Smuzhiyun _mask, \
929*4882a593Smuzhiyun .ext_info = mma9553_ext_info, \
930*4882a593Smuzhiyun }
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun #define MMA9553_ACTIVITY_CHANNEL(_chan2) { \
933*4882a593Smuzhiyun .type = IIO_ACTIVITY, \
934*4882a593Smuzhiyun .modified = 1, \
935*4882a593Smuzhiyun .channel2 = _chan2, \
936*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
937*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBHEIGHT) | \
938*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_ENABLE), \
939*4882a593Smuzhiyun .event_spec = mma9553_activity_events, \
940*4882a593Smuzhiyun .num_event_specs = ARRAY_SIZE(mma9553_activity_events), \
941*4882a593Smuzhiyun .ext_info = mma9553_ext_info, \
942*4882a593Smuzhiyun }
943*4882a593Smuzhiyun
944*4882a593Smuzhiyun static const struct iio_chan_spec mma9553_channels[] = {
945*4882a593Smuzhiyun MMA9551_ACCEL_CHANNEL(IIO_MOD_X),
946*4882a593Smuzhiyun MMA9551_ACCEL_CHANNEL(IIO_MOD_Y),
947*4882a593Smuzhiyun MMA9551_ACCEL_CHANNEL(IIO_MOD_Z),
948*4882a593Smuzhiyun
949*4882a593Smuzhiyun {
950*4882a593Smuzhiyun .type = IIO_STEPS,
951*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
952*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_ENABLE) |
953*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_DEBOUNCE_COUNT) |
954*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_DEBOUNCE_TIME),
955*4882a593Smuzhiyun .event_spec = &mma9553_step_event,
956*4882a593Smuzhiyun .num_event_specs = 1,
957*4882a593Smuzhiyun },
958*4882a593Smuzhiyun
959*4882a593Smuzhiyun MMA9553_PEDOMETER_CHANNEL(IIO_DISTANCE, BIT(IIO_CHAN_INFO_PROCESSED)),
960*4882a593Smuzhiyun {
961*4882a593Smuzhiyun .type = IIO_VELOCITY,
962*4882a593Smuzhiyun .modified = 1,
963*4882a593Smuzhiyun .channel2 = IIO_MOD_ROOT_SUM_SQUARED_X_Y_Z,
964*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
965*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE) |
966*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_INT_TIME) |
967*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_ENABLE),
968*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBHEIGHT),
969*4882a593Smuzhiyun .ext_info = mma9553_ext_info,
970*4882a593Smuzhiyun },
971*4882a593Smuzhiyun MMA9553_PEDOMETER_CHANNEL(IIO_ENERGY, BIT(IIO_CHAN_INFO_RAW) |
972*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE) |
973*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBWEIGHT)),
974*4882a593Smuzhiyun
975*4882a593Smuzhiyun MMA9553_ACTIVITY_CHANNEL(IIO_MOD_RUNNING),
976*4882a593Smuzhiyun MMA9553_ACTIVITY_CHANNEL(IIO_MOD_JOGGING),
977*4882a593Smuzhiyun MMA9553_ACTIVITY_CHANNEL(IIO_MOD_WALKING),
978*4882a593Smuzhiyun MMA9553_ACTIVITY_CHANNEL(IIO_MOD_STILL),
979*4882a593Smuzhiyun };
980*4882a593Smuzhiyun
981*4882a593Smuzhiyun static const struct iio_info mma9553_info = {
982*4882a593Smuzhiyun .read_raw = mma9553_read_raw,
983*4882a593Smuzhiyun .write_raw = mma9553_write_raw,
984*4882a593Smuzhiyun .read_event_config = mma9553_read_event_config,
985*4882a593Smuzhiyun .write_event_config = mma9553_write_event_config,
986*4882a593Smuzhiyun .read_event_value = mma9553_read_event_value,
987*4882a593Smuzhiyun .write_event_value = mma9553_write_event_value,
988*4882a593Smuzhiyun };
989*4882a593Smuzhiyun
mma9553_irq_handler(int irq,void * private)990*4882a593Smuzhiyun static irqreturn_t mma9553_irq_handler(int irq, void *private)
991*4882a593Smuzhiyun {
992*4882a593Smuzhiyun struct iio_dev *indio_dev = private;
993*4882a593Smuzhiyun struct mma9553_data *data = iio_priv(indio_dev);
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun data->timestamp = iio_get_time_ns(indio_dev);
996*4882a593Smuzhiyun /*
997*4882a593Smuzhiyun * Since we only configure the interrupt pin when an
998*4882a593Smuzhiyun * event is enabled, we are sure we have at least
999*4882a593Smuzhiyun * one event enabled at this point.
1000*4882a593Smuzhiyun */
1001*4882a593Smuzhiyun return IRQ_WAKE_THREAD;
1002*4882a593Smuzhiyun }
1003*4882a593Smuzhiyun
mma9553_event_handler(int irq,void * private)1004*4882a593Smuzhiyun static irqreturn_t mma9553_event_handler(int irq, void *private)
1005*4882a593Smuzhiyun {
1006*4882a593Smuzhiyun struct iio_dev *indio_dev = private;
1007*4882a593Smuzhiyun struct mma9553_data *data = iio_priv(indio_dev);
1008*4882a593Smuzhiyun u16 stepcnt;
1009*4882a593Smuzhiyun u8 activity;
1010*4882a593Smuzhiyun struct mma9553_event *ev_activity, *ev_prev_activity, *ev_step_detect;
1011*4882a593Smuzhiyun int ret;
1012*4882a593Smuzhiyun
1013*4882a593Smuzhiyun mutex_lock(&data->mutex);
1014*4882a593Smuzhiyun ret = mma9553_read_activity_stepcnt(data, &activity, &stepcnt);
1015*4882a593Smuzhiyun if (ret < 0) {
1016*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1017*4882a593Smuzhiyun return IRQ_HANDLED;
1018*4882a593Smuzhiyun }
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun ev_prev_activity = mma9553_get_event(data, IIO_ACTIVITY,
1021*4882a593Smuzhiyun mma9553_activity_to_mod(
1022*4882a593Smuzhiyun data->activity),
1023*4882a593Smuzhiyun IIO_EV_DIR_FALLING);
1024*4882a593Smuzhiyun ev_activity = mma9553_get_event(data, IIO_ACTIVITY,
1025*4882a593Smuzhiyun mma9553_activity_to_mod(activity),
1026*4882a593Smuzhiyun IIO_EV_DIR_RISING);
1027*4882a593Smuzhiyun ev_step_detect = mma9553_get_event(data, IIO_STEPS, IIO_NO_MOD,
1028*4882a593Smuzhiyun IIO_EV_DIR_NONE);
1029*4882a593Smuzhiyun
1030*4882a593Smuzhiyun if (ev_step_detect->enabled && (stepcnt != data->stepcnt)) {
1031*4882a593Smuzhiyun data->stepcnt = stepcnt;
1032*4882a593Smuzhiyun iio_push_event(indio_dev,
1033*4882a593Smuzhiyun IIO_EVENT_CODE(IIO_STEPS, 0, IIO_NO_MOD,
1034*4882a593Smuzhiyun IIO_EV_DIR_NONE,
1035*4882a593Smuzhiyun IIO_EV_TYPE_CHANGE, 0, 0, 0),
1036*4882a593Smuzhiyun data->timestamp);
1037*4882a593Smuzhiyun }
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun if (activity != data->activity) {
1040*4882a593Smuzhiyun data->activity = activity;
1041*4882a593Smuzhiyun /* ev_activity can be NULL if activity == ACTIVITY_UNKNOWN */
1042*4882a593Smuzhiyun if (ev_prev_activity && ev_prev_activity->enabled)
1043*4882a593Smuzhiyun iio_push_event(indio_dev,
1044*4882a593Smuzhiyun IIO_EVENT_CODE(IIO_ACTIVITY, 0,
1045*4882a593Smuzhiyun ev_prev_activity->info->mod,
1046*4882a593Smuzhiyun IIO_EV_DIR_FALLING,
1047*4882a593Smuzhiyun IIO_EV_TYPE_THRESH, 0, 0,
1048*4882a593Smuzhiyun 0),
1049*4882a593Smuzhiyun data->timestamp);
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun if (ev_activity && ev_activity->enabled)
1052*4882a593Smuzhiyun iio_push_event(indio_dev,
1053*4882a593Smuzhiyun IIO_EVENT_CODE(IIO_ACTIVITY, 0,
1054*4882a593Smuzhiyun ev_activity->info->mod,
1055*4882a593Smuzhiyun IIO_EV_DIR_RISING,
1056*4882a593Smuzhiyun IIO_EV_TYPE_THRESH, 0, 0,
1057*4882a593Smuzhiyun 0),
1058*4882a593Smuzhiyun data->timestamp);
1059*4882a593Smuzhiyun }
1060*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1061*4882a593Smuzhiyun
1062*4882a593Smuzhiyun return IRQ_HANDLED;
1063*4882a593Smuzhiyun }
1064*4882a593Smuzhiyun
mma9553_match_acpi_device(struct device * dev)1065*4882a593Smuzhiyun static const char *mma9553_match_acpi_device(struct device *dev)
1066*4882a593Smuzhiyun {
1067*4882a593Smuzhiyun const struct acpi_device_id *id;
1068*4882a593Smuzhiyun
1069*4882a593Smuzhiyun id = acpi_match_device(dev->driver->acpi_match_table, dev);
1070*4882a593Smuzhiyun if (!id)
1071*4882a593Smuzhiyun return NULL;
1072*4882a593Smuzhiyun
1073*4882a593Smuzhiyun return dev_name(dev);
1074*4882a593Smuzhiyun }
1075*4882a593Smuzhiyun
mma9553_probe(struct i2c_client * client,const struct i2c_device_id * id)1076*4882a593Smuzhiyun static int mma9553_probe(struct i2c_client *client,
1077*4882a593Smuzhiyun const struct i2c_device_id *id)
1078*4882a593Smuzhiyun {
1079*4882a593Smuzhiyun struct mma9553_data *data;
1080*4882a593Smuzhiyun struct iio_dev *indio_dev;
1081*4882a593Smuzhiyun const char *name = NULL;
1082*4882a593Smuzhiyun int ret;
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1085*4882a593Smuzhiyun if (!indio_dev)
1086*4882a593Smuzhiyun return -ENOMEM;
1087*4882a593Smuzhiyun
1088*4882a593Smuzhiyun data = iio_priv(indio_dev);
1089*4882a593Smuzhiyun i2c_set_clientdata(client, indio_dev);
1090*4882a593Smuzhiyun data->client = client;
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun if (id)
1093*4882a593Smuzhiyun name = id->name;
1094*4882a593Smuzhiyun else if (ACPI_HANDLE(&client->dev))
1095*4882a593Smuzhiyun name = mma9553_match_acpi_device(&client->dev);
1096*4882a593Smuzhiyun else
1097*4882a593Smuzhiyun return -ENOSYS;
1098*4882a593Smuzhiyun
1099*4882a593Smuzhiyun mutex_init(&data->mutex);
1100*4882a593Smuzhiyun mma9553_init_events(data);
1101*4882a593Smuzhiyun
1102*4882a593Smuzhiyun ret = mma9553_init(data);
1103*4882a593Smuzhiyun if (ret < 0)
1104*4882a593Smuzhiyun return ret;
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun indio_dev->channels = mma9553_channels;
1107*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(mma9553_channels);
1108*4882a593Smuzhiyun indio_dev->name = name;
1109*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
1110*4882a593Smuzhiyun indio_dev->info = &mma9553_info;
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun if (client->irq > 0) {
1113*4882a593Smuzhiyun ret = devm_request_threaded_irq(&client->dev, client->irq,
1114*4882a593Smuzhiyun mma9553_irq_handler,
1115*4882a593Smuzhiyun mma9553_event_handler,
1116*4882a593Smuzhiyun IRQF_TRIGGER_RISING,
1117*4882a593Smuzhiyun MMA9553_IRQ_NAME, indio_dev);
1118*4882a593Smuzhiyun if (ret < 0) {
1119*4882a593Smuzhiyun dev_err(&client->dev, "request irq %d failed\n",
1120*4882a593Smuzhiyun client->irq);
1121*4882a593Smuzhiyun goto out_poweroff;
1122*4882a593Smuzhiyun }
1123*4882a593Smuzhiyun }
1124*4882a593Smuzhiyun
1125*4882a593Smuzhiyun ret = pm_runtime_set_active(&client->dev);
1126*4882a593Smuzhiyun if (ret < 0)
1127*4882a593Smuzhiyun goto out_poweroff;
1128*4882a593Smuzhiyun
1129*4882a593Smuzhiyun pm_runtime_enable(&client->dev);
1130*4882a593Smuzhiyun pm_runtime_set_autosuspend_delay(&client->dev,
1131*4882a593Smuzhiyun MMA9551_AUTO_SUSPEND_DELAY_MS);
1132*4882a593Smuzhiyun pm_runtime_use_autosuspend(&client->dev);
1133*4882a593Smuzhiyun
1134*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
1135*4882a593Smuzhiyun if (ret < 0) {
1136*4882a593Smuzhiyun dev_err(&client->dev, "unable to register iio device\n");
1137*4882a593Smuzhiyun goto err_pm_cleanup;
1138*4882a593Smuzhiyun }
1139*4882a593Smuzhiyun
1140*4882a593Smuzhiyun dev_dbg(&indio_dev->dev, "Registered device %s\n", name);
1141*4882a593Smuzhiyun return 0;
1142*4882a593Smuzhiyun
1143*4882a593Smuzhiyun err_pm_cleanup:
1144*4882a593Smuzhiyun pm_runtime_dont_use_autosuspend(&client->dev);
1145*4882a593Smuzhiyun pm_runtime_disable(&client->dev);
1146*4882a593Smuzhiyun out_poweroff:
1147*4882a593Smuzhiyun mma9551_set_device_state(client, false);
1148*4882a593Smuzhiyun return ret;
1149*4882a593Smuzhiyun }
1150*4882a593Smuzhiyun
mma9553_remove(struct i2c_client * client)1151*4882a593Smuzhiyun static int mma9553_remove(struct i2c_client *client)
1152*4882a593Smuzhiyun {
1153*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(client);
1154*4882a593Smuzhiyun struct mma9553_data *data = iio_priv(indio_dev);
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun iio_device_unregister(indio_dev);
1157*4882a593Smuzhiyun
1158*4882a593Smuzhiyun pm_runtime_disable(&client->dev);
1159*4882a593Smuzhiyun pm_runtime_set_suspended(&client->dev);
1160*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
1161*4882a593Smuzhiyun
1162*4882a593Smuzhiyun mutex_lock(&data->mutex);
1163*4882a593Smuzhiyun mma9551_set_device_state(data->client, false);
1164*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun return 0;
1167*4882a593Smuzhiyun }
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun #ifdef CONFIG_PM
mma9553_runtime_suspend(struct device * dev)1170*4882a593Smuzhiyun static int mma9553_runtime_suspend(struct device *dev)
1171*4882a593Smuzhiyun {
1172*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1173*4882a593Smuzhiyun struct mma9553_data *data = iio_priv(indio_dev);
1174*4882a593Smuzhiyun int ret;
1175*4882a593Smuzhiyun
1176*4882a593Smuzhiyun mutex_lock(&data->mutex);
1177*4882a593Smuzhiyun ret = mma9551_set_device_state(data->client, false);
1178*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1179*4882a593Smuzhiyun if (ret < 0) {
1180*4882a593Smuzhiyun dev_err(&data->client->dev, "powering off device failed\n");
1181*4882a593Smuzhiyun return -EAGAIN;
1182*4882a593Smuzhiyun }
1183*4882a593Smuzhiyun
1184*4882a593Smuzhiyun return 0;
1185*4882a593Smuzhiyun }
1186*4882a593Smuzhiyun
mma9553_runtime_resume(struct device * dev)1187*4882a593Smuzhiyun static int mma9553_runtime_resume(struct device *dev)
1188*4882a593Smuzhiyun {
1189*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1190*4882a593Smuzhiyun struct mma9553_data *data = iio_priv(indio_dev);
1191*4882a593Smuzhiyun int ret;
1192*4882a593Smuzhiyun
1193*4882a593Smuzhiyun ret = mma9551_set_device_state(data->client, true);
1194*4882a593Smuzhiyun if (ret < 0)
1195*4882a593Smuzhiyun return ret;
1196*4882a593Smuzhiyun
1197*4882a593Smuzhiyun mma9551_sleep(MMA9553_DEFAULT_SAMPLE_RATE);
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun return 0;
1200*4882a593Smuzhiyun }
1201*4882a593Smuzhiyun #endif
1202*4882a593Smuzhiyun
1203*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
mma9553_suspend(struct device * dev)1204*4882a593Smuzhiyun static int mma9553_suspend(struct device *dev)
1205*4882a593Smuzhiyun {
1206*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1207*4882a593Smuzhiyun struct mma9553_data *data = iio_priv(indio_dev);
1208*4882a593Smuzhiyun int ret;
1209*4882a593Smuzhiyun
1210*4882a593Smuzhiyun mutex_lock(&data->mutex);
1211*4882a593Smuzhiyun ret = mma9551_set_device_state(data->client, false);
1212*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1213*4882a593Smuzhiyun
1214*4882a593Smuzhiyun return ret;
1215*4882a593Smuzhiyun }
1216*4882a593Smuzhiyun
mma9553_resume(struct device * dev)1217*4882a593Smuzhiyun static int mma9553_resume(struct device *dev)
1218*4882a593Smuzhiyun {
1219*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1220*4882a593Smuzhiyun struct mma9553_data *data = iio_priv(indio_dev);
1221*4882a593Smuzhiyun int ret;
1222*4882a593Smuzhiyun
1223*4882a593Smuzhiyun mutex_lock(&data->mutex);
1224*4882a593Smuzhiyun ret = mma9551_set_device_state(data->client, true);
1225*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1226*4882a593Smuzhiyun
1227*4882a593Smuzhiyun return ret;
1228*4882a593Smuzhiyun }
1229*4882a593Smuzhiyun #endif
1230*4882a593Smuzhiyun
1231*4882a593Smuzhiyun static const struct dev_pm_ops mma9553_pm_ops = {
1232*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(mma9553_suspend, mma9553_resume)
1233*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(mma9553_runtime_suspend,
1234*4882a593Smuzhiyun mma9553_runtime_resume, NULL)
1235*4882a593Smuzhiyun };
1236*4882a593Smuzhiyun
1237*4882a593Smuzhiyun static const struct acpi_device_id mma9553_acpi_match[] = {
1238*4882a593Smuzhiyun {"MMA9553", 0},
1239*4882a593Smuzhiyun {},
1240*4882a593Smuzhiyun };
1241*4882a593Smuzhiyun
1242*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, mma9553_acpi_match);
1243*4882a593Smuzhiyun
1244*4882a593Smuzhiyun static const struct i2c_device_id mma9553_id[] = {
1245*4882a593Smuzhiyun {"mma9553", 0},
1246*4882a593Smuzhiyun {},
1247*4882a593Smuzhiyun };
1248*4882a593Smuzhiyun
1249*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, mma9553_id);
1250*4882a593Smuzhiyun
1251*4882a593Smuzhiyun static struct i2c_driver mma9553_driver = {
1252*4882a593Smuzhiyun .driver = {
1253*4882a593Smuzhiyun .name = MMA9553_DRV_NAME,
1254*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(mma9553_acpi_match),
1255*4882a593Smuzhiyun .pm = &mma9553_pm_ops,
1256*4882a593Smuzhiyun },
1257*4882a593Smuzhiyun .probe = mma9553_probe,
1258*4882a593Smuzhiyun .remove = mma9553_remove,
1259*4882a593Smuzhiyun .id_table = mma9553_id,
1260*4882a593Smuzhiyun };
1261*4882a593Smuzhiyun
1262*4882a593Smuzhiyun module_i2c_driver(mma9553_driver);
1263*4882a593Smuzhiyun
1264*4882a593Smuzhiyun MODULE_AUTHOR("Irina Tirdea <irina.tirdea@intel.com>");
1265*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1266*4882a593Smuzhiyun MODULE_DESCRIPTION("MMA9553L pedometer platform driver");
1267