xref: /OK3568_Linux_fs/kernel/drivers/iio/accel/mma9551.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Freescale MMA9551L Intelligent Motion-Sensing Platform driver
4*4882a593Smuzhiyun  * Copyright (c) 2014, Intel Corporation.
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/i2c.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun #include <linux/acpi.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
14*4882a593Smuzhiyun #include <linux/iio/iio.h>
15*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
16*4882a593Smuzhiyun #include <linux/iio/events.h>
17*4882a593Smuzhiyun #include <linux/pm_runtime.h>
18*4882a593Smuzhiyun #include "mma9551_core.h"
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define MMA9551_DRV_NAME		"mma9551"
21*4882a593Smuzhiyun #define MMA9551_IRQ_NAME		"mma9551_event"
22*4882a593Smuzhiyun #define MMA9551_GPIO_COUNT		4
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun /* Tilt application (inclination in IIO terms). */
25*4882a593Smuzhiyun #define MMA9551_TILT_XZ_ANG_REG		0x00
26*4882a593Smuzhiyun #define MMA9551_TILT_YZ_ANG_REG		0x01
27*4882a593Smuzhiyun #define MMA9551_TILT_XY_ANG_REG		0x02
28*4882a593Smuzhiyun #define MMA9551_TILT_ANGFLG		BIT(7)
29*4882a593Smuzhiyun #define MMA9551_TILT_QUAD_REG		0x03
30*4882a593Smuzhiyun #define MMA9551_TILT_XY_QUAD_SHIFT	0
31*4882a593Smuzhiyun #define MMA9551_TILT_YZ_QUAD_SHIFT	2
32*4882a593Smuzhiyun #define MMA9551_TILT_XZ_QUAD_SHIFT	4
33*4882a593Smuzhiyun #define MMA9551_TILT_CFG_REG		0x01
34*4882a593Smuzhiyun #define MMA9551_TILT_ANG_THRESH_MASK	GENMASK(3, 0)
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define MMA9551_DEFAULT_SAMPLE_RATE	122	/* Hz */
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /* Tilt events are mapped to the first three GPIO pins. */
39*4882a593Smuzhiyun enum mma9551_tilt_axis {
40*4882a593Smuzhiyun 	mma9551_x = 0,
41*4882a593Smuzhiyun 	mma9551_y,
42*4882a593Smuzhiyun 	mma9551_z,
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun struct mma9551_data {
46*4882a593Smuzhiyun 	struct i2c_client *client;
47*4882a593Smuzhiyun 	struct mutex mutex;
48*4882a593Smuzhiyun 	int event_enabled[3];
49*4882a593Smuzhiyun 	int irqs[MMA9551_GPIO_COUNT];
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun 
mma9551_read_incli_chan(struct i2c_client * client,const struct iio_chan_spec * chan,int * val)52*4882a593Smuzhiyun static int mma9551_read_incli_chan(struct i2c_client *client,
53*4882a593Smuzhiyun 				   const struct iio_chan_spec *chan,
54*4882a593Smuzhiyun 				   int *val)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun 	u8 quad_shift, angle, quadrant;
57*4882a593Smuzhiyun 	u16 reg_addr;
58*4882a593Smuzhiyun 	int ret;
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	switch (chan->channel2) {
61*4882a593Smuzhiyun 	case IIO_MOD_X:
62*4882a593Smuzhiyun 		reg_addr = MMA9551_TILT_YZ_ANG_REG;
63*4882a593Smuzhiyun 		quad_shift = MMA9551_TILT_YZ_QUAD_SHIFT;
64*4882a593Smuzhiyun 		break;
65*4882a593Smuzhiyun 	case IIO_MOD_Y:
66*4882a593Smuzhiyun 		reg_addr = MMA9551_TILT_XZ_ANG_REG;
67*4882a593Smuzhiyun 		quad_shift = MMA9551_TILT_XZ_QUAD_SHIFT;
68*4882a593Smuzhiyun 		break;
69*4882a593Smuzhiyun 	case IIO_MOD_Z:
70*4882a593Smuzhiyun 		reg_addr = MMA9551_TILT_XY_ANG_REG;
71*4882a593Smuzhiyun 		quad_shift = MMA9551_TILT_XY_QUAD_SHIFT;
72*4882a593Smuzhiyun 		break;
73*4882a593Smuzhiyun 	default:
74*4882a593Smuzhiyun 		return -EINVAL;
75*4882a593Smuzhiyun 	}
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun 	ret = mma9551_set_power_state(client, true);
78*4882a593Smuzhiyun 	if (ret < 0)
79*4882a593Smuzhiyun 		return ret;
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 	ret = mma9551_read_status_byte(client, MMA9551_APPID_TILT,
82*4882a593Smuzhiyun 				       reg_addr, &angle);
83*4882a593Smuzhiyun 	if (ret < 0)
84*4882a593Smuzhiyun 		goto out_poweroff;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	ret = mma9551_read_status_byte(client, MMA9551_APPID_TILT,
87*4882a593Smuzhiyun 				       MMA9551_TILT_QUAD_REG, &quadrant);
88*4882a593Smuzhiyun 	if (ret < 0)
89*4882a593Smuzhiyun 		goto out_poweroff;
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	angle &= ~MMA9551_TILT_ANGFLG;
92*4882a593Smuzhiyun 	quadrant = (quadrant >> quad_shift) & 0x03;
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun 	if (quadrant == 1 || quadrant == 3)
95*4882a593Smuzhiyun 		*val = 90 * (quadrant + 1) - angle;
96*4882a593Smuzhiyun 	else
97*4882a593Smuzhiyun 		*val = angle + 90 * quadrant;
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	ret = IIO_VAL_INT;
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun out_poweroff:
102*4882a593Smuzhiyun 	mma9551_set_power_state(client, false);
103*4882a593Smuzhiyun 	return ret;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun 
mma9551_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)106*4882a593Smuzhiyun static int mma9551_read_raw(struct iio_dev *indio_dev,
107*4882a593Smuzhiyun 			    struct iio_chan_spec const *chan,
108*4882a593Smuzhiyun 			    int *val, int *val2, long mask)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun 	struct mma9551_data *data = iio_priv(indio_dev);
111*4882a593Smuzhiyun 	int ret;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	switch (mask) {
114*4882a593Smuzhiyun 	case IIO_CHAN_INFO_PROCESSED:
115*4882a593Smuzhiyun 		switch (chan->type) {
116*4882a593Smuzhiyun 		case IIO_INCLI:
117*4882a593Smuzhiyun 			mutex_lock(&data->mutex);
118*4882a593Smuzhiyun 			ret = mma9551_read_incli_chan(data->client, chan, val);
119*4882a593Smuzhiyun 			mutex_unlock(&data->mutex);
120*4882a593Smuzhiyun 			return ret;
121*4882a593Smuzhiyun 		default:
122*4882a593Smuzhiyun 			return -EINVAL;
123*4882a593Smuzhiyun 		}
124*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
125*4882a593Smuzhiyun 		switch (chan->type) {
126*4882a593Smuzhiyun 		case IIO_ACCEL:
127*4882a593Smuzhiyun 			mutex_lock(&data->mutex);
128*4882a593Smuzhiyun 			ret = mma9551_read_accel_chan(data->client,
129*4882a593Smuzhiyun 						      chan, val, val2);
130*4882a593Smuzhiyun 			mutex_unlock(&data->mutex);
131*4882a593Smuzhiyun 			return ret;
132*4882a593Smuzhiyun 		default:
133*4882a593Smuzhiyun 			return -EINVAL;
134*4882a593Smuzhiyun 		}
135*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
136*4882a593Smuzhiyun 		switch (chan->type) {
137*4882a593Smuzhiyun 		case IIO_ACCEL:
138*4882a593Smuzhiyun 			return mma9551_read_accel_scale(val, val2);
139*4882a593Smuzhiyun 		default:
140*4882a593Smuzhiyun 			return -EINVAL;
141*4882a593Smuzhiyun 		}
142*4882a593Smuzhiyun 	default:
143*4882a593Smuzhiyun 		return -EINVAL;
144*4882a593Smuzhiyun 	}
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun 
mma9551_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)147*4882a593Smuzhiyun static int mma9551_read_event_config(struct iio_dev *indio_dev,
148*4882a593Smuzhiyun 				     const struct iio_chan_spec *chan,
149*4882a593Smuzhiyun 				     enum iio_event_type type,
150*4882a593Smuzhiyun 				     enum iio_event_direction dir)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun 	struct mma9551_data *data = iio_priv(indio_dev);
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	switch (chan->type) {
155*4882a593Smuzhiyun 	case IIO_INCLI:
156*4882a593Smuzhiyun 		/* IIO counts axes from 1, because IIO_NO_MOD is 0. */
157*4882a593Smuzhiyun 		return data->event_enabled[chan->channel2 - 1];
158*4882a593Smuzhiyun 	default:
159*4882a593Smuzhiyun 		return -EINVAL;
160*4882a593Smuzhiyun 	}
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun 
mma9551_config_incli_event(struct iio_dev * indio_dev,enum iio_modifier axis,int state)163*4882a593Smuzhiyun static int mma9551_config_incli_event(struct iio_dev *indio_dev,
164*4882a593Smuzhiyun 				      enum iio_modifier axis,
165*4882a593Smuzhiyun 				      int state)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun 	struct mma9551_data *data = iio_priv(indio_dev);
168*4882a593Smuzhiyun 	enum mma9551_tilt_axis mma_axis;
169*4882a593Smuzhiyun 	int ret;
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	/* IIO counts axes from 1, because IIO_NO_MOD is 0. */
172*4882a593Smuzhiyun 	mma_axis = axis - 1;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	if (data->event_enabled[mma_axis] == state)
175*4882a593Smuzhiyun 		return 0;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	if (state == 0) {
178*4882a593Smuzhiyun 		ret = mma9551_gpio_config(data->client,
179*4882a593Smuzhiyun 					  (enum mma9551_gpio_pin)mma_axis,
180*4882a593Smuzhiyun 					  MMA9551_APPID_NONE, 0, 0);
181*4882a593Smuzhiyun 		if (ret < 0)
182*4882a593Smuzhiyun 			return ret;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 		ret = mma9551_set_power_state(data->client, false);
185*4882a593Smuzhiyun 		if (ret < 0)
186*4882a593Smuzhiyun 			return ret;
187*4882a593Smuzhiyun 	} else {
188*4882a593Smuzhiyun 		int bitnum;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 		/* Bit 7 of each angle register holds the angle flag. */
191*4882a593Smuzhiyun 		switch (axis) {
192*4882a593Smuzhiyun 		case IIO_MOD_X:
193*4882a593Smuzhiyun 			bitnum = 7 + 8 * MMA9551_TILT_YZ_ANG_REG;
194*4882a593Smuzhiyun 			break;
195*4882a593Smuzhiyun 		case IIO_MOD_Y:
196*4882a593Smuzhiyun 			bitnum = 7 + 8 * MMA9551_TILT_XZ_ANG_REG;
197*4882a593Smuzhiyun 			break;
198*4882a593Smuzhiyun 		case IIO_MOD_Z:
199*4882a593Smuzhiyun 			bitnum = 7 + 8 * MMA9551_TILT_XY_ANG_REG;
200*4882a593Smuzhiyun 			break;
201*4882a593Smuzhiyun 		default:
202*4882a593Smuzhiyun 			return -EINVAL;
203*4882a593Smuzhiyun 		}
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun 		ret = mma9551_set_power_state(data->client, true);
207*4882a593Smuzhiyun 		if (ret < 0)
208*4882a593Smuzhiyun 			return ret;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 		ret = mma9551_gpio_config(data->client,
211*4882a593Smuzhiyun 					  (enum mma9551_gpio_pin)mma_axis,
212*4882a593Smuzhiyun 					  MMA9551_APPID_TILT, bitnum, 0);
213*4882a593Smuzhiyun 		if (ret < 0) {
214*4882a593Smuzhiyun 			mma9551_set_power_state(data->client, false);
215*4882a593Smuzhiyun 			return ret;
216*4882a593Smuzhiyun 		}
217*4882a593Smuzhiyun 	}
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	data->event_enabled[mma_axis] = state;
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	return ret;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun 
mma9551_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)224*4882a593Smuzhiyun static int mma9551_write_event_config(struct iio_dev *indio_dev,
225*4882a593Smuzhiyun 				      const struct iio_chan_spec *chan,
226*4882a593Smuzhiyun 				      enum iio_event_type type,
227*4882a593Smuzhiyun 				      enum iio_event_direction dir,
228*4882a593Smuzhiyun 				      int state)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun 	struct mma9551_data *data = iio_priv(indio_dev);
231*4882a593Smuzhiyun 	int ret;
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun 	switch (chan->type) {
234*4882a593Smuzhiyun 	case IIO_INCLI:
235*4882a593Smuzhiyun 		mutex_lock(&data->mutex);
236*4882a593Smuzhiyun 		ret = mma9551_config_incli_event(indio_dev,
237*4882a593Smuzhiyun 						 chan->channel2, state);
238*4882a593Smuzhiyun 		mutex_unlock(&data->mutex);
239*4882a593Smuzhiyun 		return ret;
240*4882a593Smuzhiyun 	default:
241*4882a593Smuzhiyun 		return -EINVAL;
242*4882a593Smuzhiyun 	}
243*4882a593Smuzhiyun }
244*4882a593Smuzhiyun 
mma9551_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)245*4882a593Smuzhiyun static int mma9551_write_event_value(struct iio_dev *indio_dev,
246*4882a593Smuzhiyun 				     const struct iio_chan_spec *chan,
247*4882a593Smuzhiyun 				     enum iio_event_type type,
248*4882a593Smuzhiyun 				     enum iio_event_direction dir,
249*4882a593Smuzhiyun 				     enum iio_event_info info,
250*4882a593Smuzhiyun 				     int val, int val2)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun 	struct mma9551_data *data = iio_priv(indio_dev);
253*4882a593Smuzhiyun 	int ret;
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	switch (chan->type) {
256*4882a593Smuzhiyun 	case IIO_INCLI:
257*4882a593Smuzhiyun 		if (val2 != 0 || val < 1 || val > 10)
258*4882a593Smuzhiyun 			return -EINVAL;
259*4882a593Smuzhiyun 		mutex_lock(&data->mutex);
260*4882a593Smuzhiyun 		ret = mma9551_update_config_bits(data->client,
261*4882a593Smuzhiyun 						 MMA9551_APPID_TILT,
262*4882a593Smuzhiyun 						 MMA9551_TILT_CFG_REG,
263*4882a593Smuzhiyun 						 MMA9551_TILT_ANG_THRESH_MASK,
264*4882a593Smuzhiyun 						 val);
265*4882a593Smuzhiyun 		mutex_unlock(&data->mutex);
266*4882a593Smuzhiyun 		return ret;
267*4882a593Smuzhiyun 	default:
268*4882a593Smuzhiyun 		return -EINVAL;
269*4882a593Smuzhiyun 	}
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun 
mma9551_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)272*4882a593Smuzhiyun static int mma9551_read_event_value(struct iio_dev *indio_dev,
273*4882a593Smuzhiyun 				    const struct iio_chan_spec *chan,
274*4882a593Smuzhiyun 				    enum iio_event_type type,
275*4882a593Smuzhiyun 				    enum iio_event_direction dir,
276*4882a593Smuzhiyun 				    enum iio_event_info info,
277*4882a593Smuzhiyun 				    int *val, int *val2)
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun 	struct mma9551_data *data = iio_priv(indio_dev);
280*4882a593Smuzhiyun 	int ret;
281*4882a593Smuzhiyun 	u8 tmp;
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	switch (chan->type) {
284*4882a593Smuzhiyun 	case IIO_INCLI:
285*4882a593Smuzhiyun 		mutex_lock(&data->mutex);
286*4882a593Smuzhiyun 		ret = mma9551_read_config_byte(data->client,
287*4882a593Smuzhiyun 					       MMA9551_APPID_TILT,
288*4882a593Smuzhiyun 					       MMA9551_TILT_CFG_REG, &tmp);
289*4882a593Smuzhiyun 		mutex_unlock(&data->mutex);
290*4882a593Smuzhiyun 		if (ret < 0)
291*4882a593Smuzhiyun 			return ret;
292*4882a593Smuzhiyun 		*val = tmp & MMA9551_TILT_ANG_THRESH_MASK;
293*4882a593Smuzhiyun 		*val2 = 0;
294*4882a593Smuzhiyun 		return IIO_VAL_INT;
295*4882a593Smuzhiyun 	default:
296*4882a593Smuzhiyun 		return -EINVAL;
297*4882a593Smuzhiyun 	}
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun static const struct iio_event_spec mma9551_incli_event = {
301*4882a593Smuzhiyun 	.type = IIO_EV_TYPE_ROC,
302*4882a593Smuzhiyun 	.dir = IIO_EV_DIR_RISING,
303*4882a593Smuzhiyun 	.mask_separate = BIT(IIO_EV_INFO_ENABLE),
304*4882a593Smuzhiyun 	.mask_shared_by_type = BIT(IIO_EV_INFO_VALUE),
305*4882a593Smuzhiyun };
306*4882a593Smuzhiyun 
307*4882a593Smuzhiyun #define MMA9551_INCLI_CHANNEL(axis) {				\
308*4882a593Smuzhiyun 	.type = IIO_INCLI,					\
309*4882a593Smuzhiyun 	.modified = 1,						\
310*4882a593Smuzhiyun 	.channel2 = axis,					\
311*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),	\
312*4882a593Smuzhiyun 	.event_spec = &mma9551_incli_event,			\
313*4882a593Smuzhiyun 	.num_event_specs = 1,					\
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun static const struct iio_chan_spec mma9551_channels[] = {
317*4882a593Smuzhiyun 	MMA9551_ACCEL_CHANNEL(IIO_MOD_X),
318*4882a593Smuzhiyun 	MMA9551_ACCEL_CHANNEL(IIO_MOD_Y),
319*4882a593Smuzhiyun 	MMA9551_ACCEL_CHANNEL(IIO_MOD_Z),
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	MMA9551_INCLI_CHANNEL(IIO_MOD_X),
322*4882a593Smuzhiyun 	MMA9551_INCLI_CHANNEL(IIO_MOD_Y),
323*4882a593Smuzhiyun 	MMA9551_INCLI_CHANNEL(IIO_MOD_Z),
324*4882a593Smuzhiyun };
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun static const struct iio_info mma9551_info = {
327*4882a593Smuzhiyun 	.read_raw = mma9551_read_raw,
328*4882a593Smuzhiyun 	.read_event_config = mma9551_read_event_config,
329*4882a593Smuzhiyun 	.write_event_config = mma9551_write_event_config,
330*4882a593Smuzhiyun 	.read_event_value = mma9551_read_event_value,
331*4882a593Smuzhiyun 	.write_event_value = mma9551_write_event_value,
332*4882a593Smuzhiyun };
333*4882a593Smuzhiyun 
mma9551_event_handler(int irq,void * private)334*4882a593Smuzhiyun static irqreturn_t mma9551_event_handler(int irq, void *private)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun 	struct iio_dev *indio_dev = private;
337*4882a593Smuzhiyun 	struct mma9551_data *data = iio_priv(indio_dev);
338*4882a593Smuzhiyun 	int i, ret, mma_axis = -1;
339*4882a593Smuzhiyun 	u16 reg;
340*4882a593Smuzhiyun 	u8 val;
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	for (i = 0; i < 3; i++)
345*4882a593Smuzhiyun 		if (irq == data->irqs[i]) {
346*4882a593Smuzhiyun 			mma_axis = i;
347*4882a593Smuzhiyun 			break;
348*4882a593Smuzhiyun 		}
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	if (mma_axis == -1) {
351*4882a593Smuzhiyun 		/* IRQ was triggered on 4th line, which we don't use. */
352*4882a593Smuzhiyun 		dev_warn(&data->client->dev,
353*4882a593Smuzhiyun 			 "irq triggered on unused line %d\n", data->irqs[3]);
354*4882a593Smuzhiyun 		goto out;
355*4882a593Smuzhiyun 	}
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun 	switch (mma_axis) {
358*4882a593Smuzhiyun 	case mma9551_x:
359*4882a593Smuzhiyun 		reg = MMA9551_TILT_YZ_ANG_REG;
360*4882a593Smuzhiyun 		break;
361*4882a593Smuzhiyun 	case mma9551_y:
362*4882a593Smuzhiyun 		reg = MMA9551_TILT_XZ_ANG_REG;
363*4882a593Smuzhiyun 		break;
364*4882a593Smuzhiyun 	case mma9551_z:
365*4882a593Smuzhiyun 		reg = MMA9551_TILT_XY_ANG_REG;
366*4882a593Smuzhiyun 		break;
367*4882a593Smuzhiyun 	}
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	/*
370*4882a593Smuzhiyun 	 * Read the angle even though we don't use it, otherwise we
371*4882a593Smuzhiyun 	 * won't get any further interrupts.
372*4882a593Smuzhiyun 	 */
373*4882a593Smuzhiyun 	ret = mma9551_read_status_byte(data->client, MMA9551_APPID_TILT,
374*4882a593Smuzhiyun 				       reg, &val);
375*4882a593Smuzhiyun 	if (ret < 0) {
376*4882a593Smuzhiyun 		dev_err(&data->client->dev,
377*4882a593Smuzhiyun 			"error %d reading tilt register in IRQ\n", ret);
378*4882a593Smuzhiyun 		goto out;
379*4882a593Smuzhiyun 	}
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	iio_push_event(indio_dev,
382*4882a593Smuzhiyun 		       IIO_MOD_EVENT_CODE(IIO_INCLI, 0, (mma_axis + 1),
383*4882a593Smuzhiyun 					  IIO_EV_TYPE_ROC, IIO_EV_DIR_RISING),
384*4882a593Smuzhiyun 		       iio_get_time_ns(indio_dev));
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun out:
387*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun 	return IRQ_HANDLED;
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun 
mma9551_init(struct mma9551_data * data)392*4882a593Smuzhiyun static int mma9551_init(struct mma9551_data *data)
393*4882a593Smuzhiyun {
394*4882a593Smuzhiyun 	int ret;
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	ret = mma9551_read_version(data->client);
397*4882a593Smuzhiyun 	if (ret)
398*4882a593Smuzhiyun 		return ret;
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	return mma9551_set_device_state(data->client, true);
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun 
mma9551_gpio_probe(struct iio_dev * indio_dev)403*4882a593Smuzhiyun static int mma9551_gpio_probe(struct iio_dev *indio_dev)
404*4882a593Smuzhiyun {
405*4882a593Smuzhiyun 	struct gpio_desc *gpio;
406*4882a593Smuzhiyun 	int i, ret;
407*4882a593Smuzhiyun 	struct mma9551_data *data = iio_priv(indio_dev);
408*4882a593Smuzhiyun 	struct device *dev = &data->client->dev;
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	for (i = 0; i < MMA9551_GPIO_COUNT; i++) {
411*4882a593Smuzhiyun 		gpio = devm_gpiod_get_index(dev, NULL, i, GPIOD_IN);
412*4882a593Smuzhiyun 		if (IS_ERR(gpio)) {
413*4882a593Smuzhiyun 			dev_err(dev, "acpi gpio get index failed\n");
414*4882a593Smuzhiyun 			return PTR_ERR(gpio);
415*4882a593Smuzhiyun 		}
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 		ret = gpiod_to_irq(gpio);
418*4882a593Smuzhiyun 		if (ret < 0)
419*4882a593Smuzhiyun 			return ret;
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 		data->irqs[i] = ret;
422*4882a593Smuzhiyun 		ret = devm_request_threaded_irq(dev, data->irqs[i],
423*4882a593Smuzhiyun 				NULL, mma9551_event_handler,
424*4882a593Smuzhiyun 				IRQF_TRIGGER_RISING | IRQF_ONESHOT,
425*4882a593Smuzhiyun 				MMA9551_IRQ_NAME, indio_dev);
426*4882a593Smuzhiyun 		if (ret < 0) {
427*4882a593Smuzhiyun 			dev_err(dev, "request irq %d failed\n", data->irqs[i]);
428*4882a593Smuzhiyun 			return ret;
429*4882a593Smuzhiyun 		}
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 		dev_dbg(dev, "gpio resource, no:%d irq:%d\n",
432*4882a593Smuzhiyun 			desc_to_gpio(gpio), data->irqs[i]);
433*4882a593Smuzhiyun 	}
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun 	return 0;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun 
mma9551_match_acpi_device(struct device * dev)438*4882a593Smuzhiyun static const char *mma9551_match_acpi_device(struct device *dev)
439*4882a593Smuzhiyun {
440*4882a593Smuzhiyun 	const struct acpi_device_id *id;
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun 	id = acpi_match_device(dev->driver->acpi_match_table, dev);
443*4882a593Smuzhiyun 	if (!id)
444*4882a593Smuzhiyun 		return NULL;
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun 	return dev_name(dev);
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun 
mma9551_probe(struct i2c_client * client,const struct i2c_device_id * id)449*4882a593Smuzhiyun static int mma9551_probe(struct i2c_client *client,
450*4882a593Smuzhiyun 			 const struct i2c_device_id *id)
451*4882a593Smuzhiyun {
452*4882a593Smuzhiyun 	struct mma9551_data *data;
453*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
454*4882a593Smuzhiyun 	const char *name = NULL;
455*4882a593Smuzhiyun 	int ret;
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
458*4882a593Smuzhiyun 	if (!indio_dev)
459*4882a593Smuzhiyun 		return -ENOMEM;
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun 	data = iio_priv(indio_dev);
462*4882a593Smuzhiyun 	i2c_set_clientdata(client, indio_dev);
463*4882a593Smuzhiyun 	data->client = client;
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun 	if (id)
466*4882a593Smuzhiyun 		name = id->name;
467*4882a593Smuzhiyun 	else if (ACPI_HANDLE(&client->dev))
468*4882a593Smuzhiyun 		name = mma9551_match_acpi_device(&client->dev);
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	ret = mma9551_init(data);
471*4882a593Smuzhiyun 	if (ret < 0)
472*4882a593Smuzhiyun 		return ret;
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 	mutex_init(&data->mutex);
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	indio_dev->channels = mma9551_channels;
477*4882a593Smuzhiyun 	indio_dev->num_channels = ARRAY_SIZE(mma9551_channels);
478*4882a593Smuzhiyun 	indio_dev->name = name;
479*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
480*4882a593Smuzhiyun 	indio_dev->info = &mma9551_info;
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	ret = mma9551_gpio_probe(indio_dev);
483*4882a593Smuzhiyun 	if (ret < 0)
484*4882a593Smuzhiyun 		goto out_poweroff;
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 	ret = pm_runtime_set_active(&client->dev);
487*4882a593Smuzhiyun 	if (ret < 0)
488*4882a593Smuzhiyun 		goto out_poweroff;
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	pm_runtime_enable(&client->dev);
491*4882a593Smuzhiyun 	pm_runtime_set_autosuspend_delay(&client->dev,
492*4882a593Smuzhiyun 					 MMA9551_AUTO_SUSPEND_DELAY_MS);
493*4882a593Smuzhiyun 	pm_runtime_use_autosuspend(&client->dev);
494*4882a593Smuzhiyun 
495*4882a593Smuzhiyun 	ret = iio_device_register(indio_dev);
496*4882a593Smuzhiyun 	if (ret < 0) {
497*4882a593Smuzhiyun 		dev_err(&client->dev, "unable to register iio device\n");
498*4882a593Smuzhiyun 		goto err_pm_cleanup;
499*4882a593Smuzhiyun 	}
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun 	return 0;
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun err_pm_cleanup:
504*4882a593Smuzhiyun 	pm_runtime_dont_use_autosuspend(&client->dev);
505*4882a593Smuzhiyun 	pm_runtime_disable(&client->dev);
506*4882a593Smuzhiyun out_poweroff:
507*4882a593Smuzhiyun 	mma9551_set_device_state(client, false);
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 	return ret;
510*4882a593Smuzhiyun }
511*4882a593Smuzhiyun 
mma9551_remove(struct i2c_client * client)512*4882a593Smuzhiyun static int mma9551_remove(struct i2c_client *client)
513*4882a593Smuzhiyun {
514*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
515*4882a593Smuzhiyun 	struct mma9551_data *data = iio_priv(indio_dev);
516*4882a593Smuzhiyun 
517*4882a593Smuzhiyun 	iio_device_unregister(indio_dev);
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 	pm_runtime_disable(&client->dev);
520*4882a593Smuzhiyun 	pm_runtime_set_suspended(&client->dev);
521*4882a593Smuzhiyun 	pm_runtime_put_noidle(&client->dev);
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
524*4882a593Smuzhiyun 	mma9551_set_device_state(data->client, false);
525*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun 	return 0;
528*4882a593Smuzhiyun }
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun #ifdef CONFIG_PM
mma9551_runtime_suspend(struct device * dev)531*4882a593Smuzhiyun static int mma9551_runtime_suspend(struct device *dev)
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
534*4882a593Smuzhiyun 	struct mma9551_data *data = iio_priv(indio_dev);
535*4882a593Smuzhiyun 	int ret;
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
538*4882a593Smuzhiyun 	ret = mma9551_set_device_state(data->client, false);
539*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
540*4882a593Smuzhiyun 	if (ret < 0) {
541*4882a593Smuzhiyun 		dev_err(&data->client->dev, "powering off device failed\n");
542*4882a593Smuzhiyun 		return -EAGAIN;
543*4882a593Smuzhiyun 	}
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun 	return 0;
546*4882a593Smuzhiyun }
547*4882a593Smuzhiyun 
mma9551_runtime_resume(struct device * dev)548*4882a593Smuzhiyun static int mma9551_runtime_resume(struct device *dev)
549*4882a593Smuzhiyun {
550*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
551*4882a593Smuzhiyun 	struct mma9551_data *data = iio_priv(indio_dev);
552*4882a593Smuzhiyun 	int ret;
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun 	ret = mma9551_set_device_state(data->client, true);
555*4882a593Smuzhiyun 	if (ret < 0)
556*4882a593Smuzhiyun 		return ret;
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	mma9551_sleep(MMA9551_DEFAULT_SAMPLE_RATE);
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun 	return 0;
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun #endif
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
mma9551_suspend(struct device * dev)565*4882a593Smuzhiyun static int mma9551_suspend(struct device *dev)
566*4882a593Smuzhiyun {
567*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
568*4882a593Smuzhiyun 	struct mma9551_data *data = iio_priv(indio_dev);
569*4882a593Smuzhiyun 	int ret;
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
572*4882a593Smuzhiyun 	ret = mma9551_set_device_state(data->client, false);
573*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	return ret;
576*4882a593Smuzhiyun }
577*4882a593Smuzhiyun 
mma9551_resume(struct device * dev)578*4882a593Smuzhiyun static int mma9551_resume(struct device *dev)
579*4882a593Smuzhiyun {
580*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
581*4882a593Smuzhiyun 	struct mma9551_data *data = iio_priv(indio_dev);
582*4882a593Smuzhiyun 	int ret;
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
585*4882a593Smuzhiyun 	ret = mma9551_set_device_state(data->client, true);
586*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
587*4882a593Smuzhiyun 
588*4882a593Smuzhiyun 	return ret;
589*4882a593Smuzhiyun }
590*4882a593Smuzhiyun #endif
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun static const struct dev_pm_ops mma9551_pm_ops = {
593*4882a593Smuzhiyun 	SET_SYSTEM_SLEEP_PM_OPS(mma9551_suspend, mma9551_resume)
594*4882a593Smuzhiyun 	SET_RUNTIME_PM_OPS(mma9551_runtime_suspend,
595*4882a593Smuzhiyun 			   mma9551_runtime_resume, NULL)
596*4882a593Smuzhiyun };
597*4882a593Smuzhiyun 
598*4882a593Smuzhiyun static const struct acpi_device_id mma9551_acpi_match[] = {
599*4882a593Smuzhiyun 	{"MMA9551", 0},
600*4882a593Smuzhiyun 	{},
601*4882a593Smuzhiyun };
602*4882a593Smuzhiyun 
603*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, mma9551_acpi_match);
604*4882a593Smuzhiyun 
605*4882a593Smuzhiyun static const struct i2c_device_id mma9551_id[] = {
606*4882a593Smuzhiyun 	{"mma9551", 0},
607*4882a593Smuzhiyun 	{}
608*4882a593Smuzhiyun };
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, mma9551_id);
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun static struct i2c_driver mma9551_driver = {
613*4882a593Smuzhiyun 	.driver = {
614*4882a593Smuzhiyun 		   .name = MMA9551_DRV_NAME,
615*4882a593Smuzhiyun 		   .acpi_match_table = ACPI_PTR(mma9551_acpi_match),
616*4882a593Smuzhiyun 		   .pm = &mma9551_pm_ops,
617*4882a593Smuzhiyun 		   },
618*4882a593Smuzhiyun 	.probe = mma9551_probe,
619*4882a593Smuzhiyun 	.remove = mma9551_remove,
620*4882a593Smuzhiyun 	.id_table = mma9551_id,
621*4882a593Smuzhiyun };
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun module_i2c_driver(mma9551_driver);
624*4882a593Smuzhiyun 
625*4882a593Smuzhiyun MODULE_AUTHOR("Irina Tirdea <irina.tirdea@intel.com>");
626*4882a593Smuzhiyun MODULE_AUTHOR("Vlad Dogaru <vlad.dogaru@intel.com>");
627*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
628*4882a593Smuzhiyun MODULE_DESCRIPTION("MMA9551L motion-sensing platform driver");
629