1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * kxsd9.c simple support for the Kionix KXSD9 3D
4*4882a593Smuzhiyun * accelerometer.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (c) 2008-2009 Jonathan Cameron <jic23@kernel.org>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * The i2c interface is very similar, so shouldn't be a problem once
9*4882a593Smuzhiyun * I have a suitable wire made up.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * TODO: Support the motion detector
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/device.h>
15*4882a593Smuzhiyun #include <linux/kernel.h>
16*4882a593Smuzhiyun #include <linux/sysfs.h>
17*4882a593Smuzhiyun #include <linux/slab.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/regmap.h>
20*4882a593Smuzhiyun #include <linux/bitops.h>
21*4882a593Smuzhiyun #include <linux/delay.h>
22*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
23*4882a593Smuzhiyun #include <linux/pm_runtime.h>
24*4882a593Smuzhiyun #include <linux/iio/iio.h>
25*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
26*4882a593Smuzhiyun #include <linux/iio/buffer.h>
27*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
28*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include "kxsd9.h"
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define KXSD9_REG_X 0x00
33*4882a593Smuzhiyun #define KXSD9_REG_Y 0x02
34*4882a593Smuzhiyun #define KXSD9_REG_Z 0x04
35*4882a593Smuzhiyun #define KXSD9_REG_AUX 0x06
36*4882a593Smuzhiyun #define KXSD9_REG_RESET 0x0a
37*4882a593Smuzhiyun #define KXSD9_REG_CTRL_C 0x0c
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define KXSD9_CTRL_C_FS_MASK 0x03
40*4882a593Smuzhiyun #define KXSD9_CTRL_C_FS_8G 0x00
41*4882a593Smuzhiyun #define KXSD9_CTRL_C_FS_6G 0x01
42*4882a593Smuzhiyun #define KXSD9_CTRL_C_FS_4G 0x02
43*4882a593Smuzhiyun #define KXSD9_CTRL_C_FS_2G 0x03
44*4882a593Smuzhiyun #define KXSD9_CTRL_C_MOT_LAT BIT(3)
45*4882a593Smuzhiyun #define KXSD9_CTRL_C_MOT_LEV BIT(4)
46*4882a593Smuzhiyun #define KXSD9_CTRL_C_LP_MASK 0xe0
47*4882a593Smuzhiyun #define KXSD9_CTRL_C_LP_NONE 0x00
48*4882a593Smuzhiyun #define KXSD9_CTRL_C_LP_2000HZC BIT(5)
49*4882a593Smuzhiyun #define KXSD9_CTRL_C_LP_2000HZB BIT(6)
50*4882a593Smuzhiyun #define KXSD9_CTRL_C_LP_2000HZA (BIT(5)|BIT(6))
51*4882a593Smuzhiyun #define KXSD9_CTRL_C_LP_1000HZ BIT(7)
52*4882a593Smuzhiyun #define KXSD9_CTRL_C_LP_500HZ (BIT(7)|BIT(5))
53*4882a593Smuzhiyun #define KXSD9_CTRL_C_LP_100HZ (BIT(7)|BIT(6))
54*4882a593Smuzhiyun #define KXSD9_CTRL_C_LP_50HZ (BIT(7)|BIT(6)|BIT(5))
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define KXSD9_REG_CTRL_B 0x0d
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define KXSD9_CTRL_B_CLK_HLD BIT(7)
59*4882a593Smuzhiyun #define KXSD9_CTRL_B_ENABLE BIT(6)
60*4882a593Smuzhiyun #define KXSD9_CTRL_B_ST BIT(5) /* Self-test */
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #define KXSD9_REG_CTRL_A 0x0e
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /**
65*4882a593Smuzhiyun * struct kxsd9_state - device related storage
66*4882a593Smuzhiyun * @dev: pointer to the parent device
67*4882a593Smuzhiyun * @map: regmap to the device
68*4882a593Smuzhiyun * @orientation: mounting matrix, flipped axis etc
69*4882a593Smuzhiyun * @regs: regulators for this device, VDD and IOVDD
70*4882a593Smuzhiyun * @scale: the current scaling setting
71*4882a593Smuzhiyun */
72*4882a593Smuzhiyun struct kxsd9_state {
73*4882a593Smuzhiyun struct device *dev;
74*4882a593Smuzhiyun struct regmap *map;
75*4882a593Smuzhiyun struct iio_mount_matrix orientation;
76*4882a593Smuzhiyun struct regulator_bulk_data regs[2];
77*4882a593Smuzhiyun u8 scale;
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun #define KXSD9_SCALE_2G "0.011978"
81*4882a593Smuzhiyun #define KXSD9_SCALE_4G "0.023927"
82*4882a593Smuzhiyun #define KXSD9_SCALE_6G "0.035934"
83*4882a593Smuzhiyun #define KXSD9_SCALE_8G "0.047853"
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /* reverse order */
86*4882a593Smuzhiyun static const int kxsd9_micro_scales[4] = { 47853, 35934, 23927, 11978 };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #define KXSD9_ZERO_G_OFFSET -2048
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /*
91*4882a593Smuzhiyun * Regulator names
92*4882a593Smuzhiyun */
93*4882a593Smuzhiyun static const char kxsd9_reg_vdd[] = "vdd";
94*4882a593Smuzhiyun static const char kxsd9_reg_iovdd[] = "iovdd";
95*4882a593Smuzhiyun
kxsd9_write_scale(struct iio_dev * indio_dev,int micro)96*4882a593Smuzhiyun static int kxsd9_write_scale(struct iio_dev *indio_dev, int micro)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun int ret, i;
99*4882a593Smuzhiyun struct kxsd9_state *st = iio_priv(indio_dev);
100*4882a593Smuzhiyun bool foundit = false;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun for (i = 0; i < 4; i++)
103*4882a593Smuzhiyun if (micro == kxsd9_micro_scales[i]) {
104*4882a593Smuzhiyun foundit = true;
105*4882a593Smuzhiyun break;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun if (!foundit)
108*4882a593Smuzhiyun return -EINVAL;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun ret = regmap_update_bits(st->map,
111*4882a593Smuzhiyun KXSD9_REG_CTRL_C,
112*4882a593Smuzhiyun KXSD9_CTRL_C_FS_MASK,
113*4882a593Smuzhiyun i);
114*4882a593Smuzhiyun if (ret < 0)
115*4882a593Smuzhiyun goto error_ret;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* Cached scale when the sensor is powered down */
118*4882a593Smuzhiyun st->scale = i;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun error_ret:
121*4882a593Smuzhiyun return ret;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun static IIO_CONST_ATTR(accel_scale_available,
125*4882a593Smuzhiyun KXSD9_SCALE_2G " "
126*4882a593Smuzhiyun KXSD9_SCALE_4G " "
127*4882a593Smuzhiyun KXSD9_SCALE_6G " "
128*4882a593Smuzhiyun KXSD9_SCALE_8G);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun static struct attribute *kxsd9_attributes[] = {
131*4882a593Smuzhiyun &iio_const_attr_accel_scale_available.dev_attr.attr,
132*4882a593Smuzhiyun NULL,
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun
kxsd9_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)135*4882a593Smuzhiyun static int kxsd9_write_raw(struct iio_dev *indio_dev,
136*4882a593Smuzhiyun struct iio_chan_spec const *chan,
137*4882a593Smuzhiyun int val,
138*4882a593Smuzhiyun int val2,
139*4882a593Smuzhiyun long mask)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun int ret = -EINVAL;
142*4882a593Smuzhiyun struct kxsd9_state *st = iio_priv(indio_dev);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun pm_runtime_get_sync(st->dev);
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun if (mask == IIO_CHAN_INFO_SCALE) {
147*4882a593Smuzhiyun /* Check no integer component */
148*4882a593Smuzhiyun if (val)
149*4882a593Smuzhiyun return -EINVAL;
150*4882a593Smuzhiyun ret = kxsd9_write_scale(indio_dev, val2);
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun pm_runtime_mark_last_busy(st->dev);
154*4882a593Smuzhiyun pm_runtime_put_autosuspend(st->dev);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun return ret;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
kxsd9_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)159*4882a593Smuzhiyun static int kxsd9_read_raw(struct iio_dev *indio_dev,
160*4882a593Smuzhiyun struct iio_chan_spec const *chan,
161*4882a593Smuzhiyun int *val, int *val2, long mask)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun int ret = -EINVAL;
164*4882a593Smuzhiyun struct kxsd9_state *st = iio_priv(indio_dev);
165*4882a593Smuzhiyun unsigned int regval;
166*4882a593Smuzhiyun __be16 raw_val;
167*4882a593Smuzhiyun u16 nval;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun pm_runtime_get_sync(st->dev);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun switch (mask) {
172*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
173*4882a593Smuzhiyun ret = regmap_bulk_read(st->map, chan->address, &raw_val,
174*4882a593Smuzhiyun sizeof(raw_val));
175*4882a593Smuzhiyun if (ret)
176*4882a593Smuzhiyun goto error_ret;
177*4882a593Smuzhiyun nval = be16_to_cpu(raw_val);
178*4882a593Smuzhiyun /* Only 12 bits are valid */
179*4882a593Smuzhiyun nval >>= 4;
180*4882a593Smuzhiyun *val = nval;
181*4882a593Smuzhiyun ret = IIO_VAL_INT;
182*4882a593Smuzhiyun break;
183*4882a593Smuzhiyun case IIO_CHAN_INFO_OFFSET:
184*4882a593Smuzhiyun /* This has a bias of -2048 */
185*4882a593Smuzhiyun *val = KXSD9_ZERO_G_OFFSET;
186*4882a593Smuzhiyun ret = IIO_VAL_INT;
187*4882a593Smuzhiyun break;
188*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
189*4882a593Smuzhiyun ret = regmap_read(st->map,
190*4882a593Smuzhiyun KXSD9_REG_CTRL_C,
191*4882a593Smuzhiyun ®val);
192*4882a593Smuzhiyun if (ret < 0)
193*4882a593Smuzhiyun goto error_ret;
194*4882a593Smuzhiyun *val = 0;
195*4882a593Smuzhiyun *val2 = kxsd9_micro_scales[regval & KXSD9_CTRL_C_FS_MASK];
196*4882a593Smuzhiyun ret = IIO_VAL_INT_PLUS_MICRO;
197*4882a593Smuzhiyun break;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun error_ret:
201*4882a593Smuzhiyun pm_runtime_mark_last_busy(st->dev);
202*4882a593Smuzhiyun pm_runtime_put_autosuspend(st->dev);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun return ret;
205*4882a593Smuzhiyun };
206*4882a593Smuzhiyun
kxsd9_trigger_handler(int irq,void * p)207*4882a593Smuzhiyun static irqreturn_t kxsd9_trigger_handler(int irq, void *p)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun const struct iio_poll_func *pf = p;
210*4882a593Smuzhiyun struct iio_dev *indio_dev = pf->indio_dev;
211*4882a593Smuzhiyun struct kxsd9_state *st = iio_priv(indio_dev);
212*4882a593Smuzhiyun /*
213*4882a593Smuzhiyun * Ensure correct positioning and alignment of timestamp.
214*4882a593Smuzhiyun * No need to zero initialize as all elements written.
215*4882a593Smuzhiyun */
216*4882a593Smuzhiyun struct {
217*4882a593Smuzhiyun __be16 chan[4];
218*4882a593Smuzhiyun s64 ts __aligned(8);
219*4882a593Smuzhiyun } hw_values;
220*4882a593Smuzhiyun int ret;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun ret = regmap_bulk_read(st->map,
223*4882a593Smuzhiyun KXSD9_REG_X,
224*4882a593Smuzhiyun hw_values.chan,
225*4882a593Smuzhiyun sizeof(hw_values.chan));
226*4882a593Smuzhiyun if (ret) {
227*4882a593Smuzhiyun dev_err(st->dev, "error reading data: %d\n", ret);
228*4882a593Smuzhiyun goto out;
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun iio_push_to_buffers_with_timestamp(indio_dev,
232*4882a593Smuzhiyun &hw_values,
233*4882a593Smuzhiyun iio_get_time_ns(indio_dev));
234*4882a593Smuzhiyun out:
235*4882a593Smuzhiyun iio_trigger_notify_done(indio_dev->trig);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun return IRQ_HANDLED;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun
kxsd9_buffer_preenable(struct iio_dev * indio_dev)240*4882a593Smuzhiyun static int kxsd9_buffer_preenable(struct iio_dev *indio_dev)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun struct kxsd9_state *st = iio_priv(indio_dev);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun pm_runtime_get_sync(st->dev);
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun return 0;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
kxsd9_buffer_postdisable(struct iio_dev * indio_dev)249*4882a593Smuzhiyun static int kxsd9_buffer_postdisable(struct iio_dev *indio_dev)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun struct kxsd9_state *st = iio_priv(indio_dev);
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun pm_runtime_mark_last_busy(st->dev);
254*4882a593Smuzhiyun pm_runtime_put_autosuspend(st->dev);
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun return 0;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun static const struct iio_buffer_setup_ops kxsd9_buffer_setup_ops = {
260*4882a593Smuzhiyun .preenable = kxsd9_buffer_preenable,
261*4882a593Smuzhiyun .postdisable = kxsd9_buffer_postdisable,
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun static const struct iio_mount_matrix *
kxsd9_get_mount_matrix(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)265*4882a593Smuzhiyun kxsd9_get_mount_matrix(const struct iio_dev *indio_dev,
266*4882a593Smuzhiyun const struct iio_chan_spec *chan)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun struct kxsd9_state *st = iio_priv(indio_dev);
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun return &st->orientation;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun static const struct iio_chan_spec_ext_info kxsd9_ext_info[] = {
274*4882a593Smuzhiyun IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, kxsd9_get_mount_matrix),
275*4882a593Smuzhiyun { },
276*4882a593Smuzhiyun };
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun #define KXSD9_ACCEL_CHAN(axis, index) \
279*4882a593Smuzhiyun { \
280*4882a593Smuzhiyun .type = IIO_ACCEL, \
281*4882a593Smuzhiyun .modified = 1, \
282*4882a593Smuzhiyun .channel2 = IIO_MOD_##axis, \
283*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
284*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
285*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_OFFSET), \
286*4882a593Smuzhiyun .ext_info = kxsd9_ext_info, \
287*4882a593Smuzhiyun .address = KXSD9_REG_##axis, \
288*4882a593Smuzhiyun .scan_index = index, \
289*4882a593Smuzhiyun .scan_type = { \
290*4882a593Smuzhiyun .sign = 'u', \
291*4882a593Smuzhiyun .realbits = 12, \
292*4882a593Smuzhiyun .storagebits = 16, \
293*4882a593Smuzhiyun .shift = 4, \
294*4882a593Smuzhiyun .endianness = IIO_BE, \
295*4882a593Smuzhiyun }, \
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun static const struct iio_chan_spec kxsd9_channels[] = {
299*4882a593Smuzhiyun KXSD9_ACCEL_CHAN(X, 0),
300*4882a593Smuzhiyun KXSD9_ACCEL_CHAN(Y, 1),
301*4882a593Smuzhiyun KXSD9_ACCEL_CHAN(Z, 2),
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun .type = IIO_VOLTAGE,
304*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
305*4882a593Smuzhiyun .indexed = 1,
306*4882a593Smuzhiyun .address = KXSD9_REG_AUX,
307*4882a593Smuzhiyun .scan_index = 3,
308*4882a593Smuzhiyun .scan_type = {
309*4882a593Smuzhiyun .sign = 'u',
310*4882a593Smuzhiyun .realbits = 12,
311*4882a593Smuzhiyun .storagebits = 16,
312*4882a593Smuzhiyun .shift = 4,
313*4882a593Smuzhiyun .endianness = IIO_BE,
314*4882a593Smuzhiyun },
315*4882a593Smuzhiyun },
316*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(4),
317*4882a593Smuzhiyun };
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun static const struct attribute_group kxsd9_attribute_group = {
320*4882a593Smuzhiyun .attrs = kxsd9_attributes,
321*4882a593Smuzhiyun };
322*4882a593Smuzhiyun
kxsd9_power_up(struct kxsd9_state * st)323*4882a593Smuzhiyun static int kxsd9_power_up(struct kxsd9_state *st)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun int ret;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun /* Enable the regulators */
328*4882a593Smuzhiyun ret = regulator_bulk_enable(ARRAY_SIZE(st->regs), st->regs);
329*4882a593Smuzhiyun if (ret) {
330*4882a593Smuzhiyun dev_err(st->dev, "Cannot enable regulators\n");
331*4882a593Smuzhiyun return ret;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun /* Power up */
335*4882a593Smuzhiyun ret = regmap_write(st->map,
336*4882a593Smuzhiyun KXSD9_REG_CTRL_B,
337*4882a593Smuzhiyun KXSD9_CTRL_B_ENABLE);
338*4882a593Smuzhiyun if (ret)
339*4882a593Smuzhiyun return ret;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun /*
342*4882a593Smuzhiyun * Set 1000Hz LPF, 2g fullscale, motion wakeup threshold 1g,
343*4882a593Smuzhiyun * latched wakeup
344*4882a593Smuzhiyun */
345*4882a593Smuzhiyun ret = regmap_write(st->map,
346*4882a593Smuzhiyun KXSD9_REG_CTRL_C,
347*4882a593Smuzhiyun KXSD9_CTRL_C_LP_1000HZ |
348*4882a593Smuzhiyun KXSD9_CTRL_C_MOT_LEV |
349*4882a593Smuzhiyun KXSD9_CTRL_C_MOT_LAT |
350*4882a593Smuzhiyun st->scale);
351*4882a593Smuzhiyun if (ret)
352*4882a593Smuzhiyun return ret;
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun /*
355*4882a593Smuzhiyun * Power-up time depends on the LPF setting, but typ 15.9 ms, let's
356*4882a593Smuzhiyun * set 20 ms to allow for some slack.
357*4882a593Smuzhiyun */
358*4882a593Smuzhiyun msleep(20);
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun return 0;
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun
kxsd9_power_down(struct kxsd9_state * st)363*4882a593Smuzhiyun static int kxsd9_power_down(struct kxsd9_state *st)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun int ret;
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun /*
368*4882a593Smuzhiyun * Set into low power mode - since there may be more users of the
369*4882a593Smuzhiyun * regulators this is the first step of the power saving: it will
370*4882a593Smuzhiyun * make sure we conserve power even if there are others users on the
371*4882a593Smuzhiyun * regulators.
372*4882a593Smuzhiyun */
373*4882a593Smuzhiyun ret = regmap_update_bits(st->map,
374*4882a593Smuzhiyun KXSD9_REG_CTRL_B,
375*4882a593Smuzhiyun KXSD9_CTRL_B_ENABLE,
376*4882a593Smuzhiyun 0);
377*4882a593Smuzhiyun if (ret)
378*4882a593Smuzhiyun return ret;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun /* Disable the regulators */
381*4882a593Smuzhiyun ret = regulator_bulk_disable(ARRAY_SIZE(st->regs), st->regs);
382*4882a593Smuzhiyun if (ret) {
383*4882a593Smuzhiyun dev_err(st->dev, "Cannot disable regulators\n");
384*4882a593Smuzhiyun return ret;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun return 0;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun static const struct iio_info kxsd9_info = {
391*4882a593Smuzhiyun .read_raw = &kxsd9_read_raw,
392*4882a593Smuzhiyun .write_raw = &kxsd9_write_raw,
393*4882a593Smuzhiyun .attrs = &kxsd9_attribute_group,
394*4882a593Smuzhiyun };
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun /* Four channels apart from timestamp, scan mask = 0x0f */
397*4882a593Smuzhiyun static const unsigned long kxsd9_scan_masks[] = { 0xf, 0 };
398*4882a593Smuzhiyun
kxsd9_common_probe(struct device * dev,struct regmap * map,const char * name)399*4882a593Smuzhiyun int kxsd9_common_probe(struct device *dev,
400*4882a593Smuzhiyun struct regmap *map,
401*4882a593Smuzhiyun const char *name)
402*4882a593Smuzhiyun {
403*4882a593Smuzhiyun struct iio_dev *indio_dev;
404*4882a593Smuzhiyun struct kxsd9_state *st;
405*4882a593Smuzhiyun int ret;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
408*4882a593Smuzhiyun if (!indio_dev)
409*4882a593Smuzhiyun return -ENOMEM;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun st = iio_priv(indio_dev);
412*4882a593Smuzhiyun st->dev = dev;
413*4882a593Smuzhiyun st->map = map;
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun indio_dev->channels = kxsd9_channels;
416*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(kxsd9_channels);
417*4882a593Smuzhiyun indio_dev->name = name;
418*4882a593Smuzhiyun indio_dev->info = &kxsd9_info;
419*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
420*4882a593Smuzhiyun indio_dev->available_scan_masks = kxsd9_scan_masks;
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun /* Read the mounting matrix, if present */
423*4882a593Smuzhiyun ret = iio_read_mount_matrix(dev, "mount-matrix", &st->orientation);
424*4882a593Smuzhiyun if (ret)
425*4882a593Smuzhiyun return ret;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun /* Fetch and turn on regulators */
428*4882a593Smuzhiyun st->regs[0].supply = kxsd9_reg_vdd;
429*4882a593Smuzhiyun st->regs[1].supply = kxsd9_reg_iovdd;
430*4882a593Smuzhiyun ret = devm_regulator_bulk_get(dev,
431*4882a593Smuzhiyun ARRAY_SIZE(st->regs),
432*4882a593Smuzhiyun st->regs);
433*4882a593Smuzhiyun if (ret) {
434*4882a593Smuzhiyun dev_err(dev, "Cannot get regulators\n");
435*4882a593Smuzhiyun return ret;
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun /* Default scaling */
438*4882a593Smuzhiyun st->scale = KXSD9_CTRL_C_FS_2G;
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun kxsd9_power_up(st);
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun ret = iio_triggered_buffer_setup(indio_dev,
443*4882a593Smuzhiyun iio_pollfunc_store_time,
444*4882a593Smuzhiyun kxsd9_trigger_handler,
445*4882a593Smuzhiyun &kxsd9_buffer_setup_ops);
446*4882a593Smuzhiyun if (ret) {
447*4882a593Smuzhiyun dev_err(dev, "triggered buffer setup failed\n");
448*4882a593Smuzhiyun goto err_power_down;
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
452*4882a593Smuzhiyun if (ret)
453*4882a593Smuzhiyun goto err_cleanup_buffer;
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun dev_set_drvdata(dev, indio_dev);
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun /* Enable runtime PM */
458*4882a593Smuzhiyun pm_runtime_get_noresume(dev);
459*4882a593Smuzhiyun pm_runtime_set_active(dev);
460*4882a593Smuzhiyun pm_runtime_enable(dev);
461*4882a593Smuzhiyun /*
462*4882a593Smuzhiyun * Set autosuspend to two orders of magnitude larger than the
463*4882a593Smuzhiyun * start-up time. 20ms start-up time means 2000ms autosuspend,
464*4882a593Smuzhiyun * i.e. 2 seconds.
465*4882a593Smuzhiyun */
466*4882a593Smuzhiyun pm_runtime_set_autosuspend_delay(dev, 2000);
467*4882a593Smuzhiyun pm_runtime_use_autosuspend(dev);
468*4882a593Smuzhiyun pm_runtime_put(dev);
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun return 0;
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun err_cleanup_buffer:
473*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
474*4882a593Smuzhiyun err_power_down:
475*4882a593Smuzhiyun kxsd9_power_down(st);
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun return ret;
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun EXPORT_SYMBOL(kxsd9_common_probe);
480*4882a593Smuzhiyun
kxsd9_common_remove(struct device * dev)481*4882a593Smuzhiyun int kxsd9_common_remove(struct device *dev)
482*4882a593Smuzhiyun {
483*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_get_drvdata(dev);
484*4882a593Smuzhiyun struct kxsd9_state *st = iio_priv(indio_dev);
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
487*4882a593Smuzhiyun iio_device_unregister(indio_dev);
488*4882a593Smuzhiyun pm_runtime_get_sync(dev);
489*4882a593Smuzhiyun pm_runtime_put_noidle(dev);
490*4882a593Smuzhiyun pm_runtime_disable(dev);
491*4882a593Smuzhiyun kxsd9_power_down(st);
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun return 0;
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun EXPORT_SYMBOL(kxsd9_common_remove);
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun #ifdef CONFIG_PM
kxsd9_runtime_suspend(struct device * dev)498*4882a593Smuzhiyun static int kxsd9_runtime_suspend(struct device *dev)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_get_drvdata(dev);
501*4882a593Smuzhiyun struct kxsd9_state *st = iio_priv(indio_dev);
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun return kxsd9_power_down(st);
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun
kxsd9_runtime_resume(struct device * dev)506*4882a593Smuzhiyun static int kxsd9_runtime_resume(struct device *dev)
507*4882a593Smuzhiyun {
508*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_get_drvdata(dev);
509*4882a593Smuzhiyun struct kxsd9_state *st = iio_priv(indio_dev);
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun return kxsd9_power_up(st);
512*4882a593Smuzhiyun }
513*4882a593Smuzhiyun #endif /* CONFIG_PM */
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun const struct dev_pm_ops kxsd9_dev_pm_ops = {
516*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
517*4882a593Smuzhiyun pm_runtime_force_resume)
518*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(kxsd9_runtime_suspend,
519*4882a593Smuzhiyun kxsd9_runtime_resume, NULL)
520*4882a593Smuzhiyun };
521*4882a593Smuzhiyun EXPORT_SYMBOL(kxsd9_dev_pm_ops);
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
524*4882a593Smuzhiyun MODULE_DESCRIPTION("Kionix KXSD9 driver");
525*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
526