1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * KXCJK-1013 3-axis accelerometer driver
4*4882a593Smuzhiyun * Copyright (c) 2014, Intel Corporation.
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/module.h>
8*4882a593Smuzhiyun #include <linux/i2c.h>
9*4882a593Smuzhiyun #include <linux/interrupt.h>
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/bitops.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun #include <linux/string.h>
14*4882a593Smuzhiyun #include <linux/acpi.h>
15*4882a593Smuzhiyun #include <linux/pm.h>
16*4882a593Smuzhiyun #include <linux/pm_runtime.h>
17*4882a593Smuzhiyun #include <linux/iio/iio.h>
18*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
19*4882a593Smuzhiyun #include <linux/iio/buffer.h>
20*4882a593Smuzhiyun #include <linux/iio/trigger.h>
21*4882a593Smuzhiyun #include <linux/iio/events.h>
22*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
23*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
24*4882a593Smuzhiyun #include <linux/iio/accel/kxcjk_1013.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define KXCJK1013_DRV_NAME "kxcjk1013"
27*4882a593Smuzhiyun #define KXCJK1013_IRQ_NAME "kxcjk1013_event"
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define KXTF9_REG_HP_XOUT_L 0x00
30*4882a593Smuzhiyun #define KXTF9_REG_HP_XOUT_H 0x01
31*4882a593Smuzhiyun #define KXTF9_REG_HP_YOUT_L 0x02
32*4882a593Smuzhiyun #define KXTF9_REG_HP_YOUT_H 0x03
33*4882a593Smuzhiyun #define KXTF9_REG_HP_ZOUT_L 0x04
34*4882a593Smuzhiyun #define KXTF9_REG_HP_ZOUT_H 0x05
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define KXCJK1013_REG_XOUT_L 0x06
37*4882a593Smuzhiyun /*
38*4882a593Smuzhiyun * From low byte X axis register, all the other addresses of Y and Z can be
39*4882a593Smuzhiyun * obtained by just applying axis offset. The following axis defines are just
40*4882a593Smuzhiyun * provide clarity, but not used.
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun #define KXCJK1013_REG_XOUT_H 0x07
43*4882a593Smuzhiyun #define KXCJK1013_REG_YOUT_L 0x08
44*4882a593Smuzhiyun #define KXCJK1013_REG_YOUT_H 0x09
45*4882a593Smuzhiyun #define KXCJK1013_REG_ZOUT_L 0x0A
46*4882a593Smuzhiyun #define KXCJK1013_REG_ZOUT_H 0x0B
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define KXCJK1013_REG_DCST_RESP 0x0C
49*4882a593Smuzhiyun #define KXCJK1013_REG_WHO_AM_I 0x0F
50*4882a593Smuzhiyun #define KXTF9_REG_TILT_POS_CUR 0x10
51*4882a593Smuzhiyun #define KXTF9_REG_TILT_POS_PREV 0x11
52*4882a593Smuzhiyun #define KXTF9_REG_INT_SRC1 0x15
53*4882a593Smuzhiyun #define KXCJK1013_REG_INT_SRC1 0x16 /* compatible, but called INT_SRC2 in KXTF9 ds */
54*4882a593Smuzhiyun #define KXCJK1013_REG_INT_SRC2 0x17
55*4882a593Smuzhiyun #define KXCJK1013_REG_STATUS_REG 0x18
56*4882a593Smuzhiyun #define KXCJK1013_REG_INT_REL 0x1A
57*4882a593Smuzhiyun #define KXCJK1013_REG_CTRL1 0x1B
58*4882a593Smuzhiyun #define KXTF9_REG_CTRL2 0x1C
59*4882a593Smuzhiyun #define KXCJK1013_REG_CTRL2 0x1D /* mostly compatible, CTRL_REG3 in KTXF9 ds */
60*4882a593Smuzhiyun #define KXCJK1013_REG_INT_CTRL1 0x1E
61*4882a593Smuzhiyun #define KXCJK1013_REG_INT_CTRL2 0x1F
62*4882a593Smuzhiyun #define KXTF9_REG_INT_CTRL3 0x20
63*4882a593Smuzhiyun #define KXCJK1013_REG_DATA_CTRL 0x21
64*4882a593Smuzhiyun #define KXTF9_REG_TILT_TIMER 0x28
65*4882a593Smuzhiyun #define KXCJK1013_REG_WAKE_TIMER 0x29
66*4882a593Smuzhiyun #define KXTF9_REG_TDT_TIMER 0x2B
67*4882a593Smuzhiyun #define KXTF9_REG_TDT_THRESH_H 0x2C
68*4882a593Smuzhiyun #define KXTF9_REG_TDT_THRESH_L 0x2D
69*4882a593Smuzhiyun #define KXTF9_REG_TDT_TAP_TIMER 0x2E
70*4882a593Smuzhiyun #define KXTF9_REG_TDT_TOTAL_TIMER 0x2F
71*4882a593Smuzhiyun #define KXTF9_REG_TDT_LATENCY_TIMER 0x30
72*4882a593Smuzhiyun #define KXTF9_REG_TDT_WINDOW_TIMER 0x31
73*4882a593Smuzhiyun #define KXCJK1013_REG_SELF_TEST 0x3A
74*4882a593Smuzhiyun #define KXTF9_REG_WAKE_THRESH 0x5A
75*4882a593Smuzhiyun #define KXTF9_REG_TILT_ANGLE 0x5C
76*4882a593Smuzhiyun #define KXTF9_REG_HYST_SET 0x5F
77*4882a593Smuzhiyun #define KXCJK1013_REG_WAKE_THRES 0x6A
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #define KXCJK1013_REG_CTRL1_BIT_PC1 BIT(7)
80*4882a593Smuzhiyun #define KXCJK1013_REG_CTRL1_BIT_RES BIT(6)
81*4882a593Smuzhiyun #define KXCJK1013_REG_CTRL1_BIT_DRDY BIT(5)
82*4882a593Smuzhiyun #define KXCJK1013_REG_CTRL1_BIT_GSEL1 BIT(4)
83*4882a593Smuzhiyun #define KXCJK1013_REG_CTRL1_BIT_GSEL0 BIT(3)
84*4882a593Smuzhiyun #define KXCJK1013_REG_CTRL1_BIT_WUFE BIT(1)
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #define KXCJK1013_REG_INT_CTRL1_BIT_IEU BIT(2) /* KXTF9 */
87*4882a593Smuzhiyun #define KXCJK1013_REG_INT_CTRL1_BIT_IEL BIT(3)
88*4882a593Smuzhiyun #define KXCJK1013_REG_INT_CTRL1_BIT_IEA BIT(4)
89*4882a593Smuzhiyun #define KXCJK1013_REG_INT_CTRL1_BIT_IEN BIT(5)
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun #define KXTF9_REG_TILT_BIT_LEFT_EDGE BIT(5)
92*4882a593Smuzhiyun #define KXTF9_REG_TILT_BIT_RIGHT_EDGE BIT(4)
93*4882a593Smuzhiyun #define KXTF9_REG_TILT_BIT_LOWER_EDGE BIT(3)
94*4882a593Smuzhiyun #define KXTF9_REG_TILT_BIT_UPPER_EDGE BIT(2)
95*4882a593Smuzhiyun #define KXTF9_REG_TILT_BIT_FACE_DOWN BIT(1)
96*4882a593Smuzhiyun #define KXTF9_REG_TILT_BIT_FACE_UP BIT(0)
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun #define KXCJK1013_DATA_MASK_12_BIT 0x0FFF
99*4882a593Smuzhiyun #define KXCJK1013_MAX_STARTUP_TIME_US 100000
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun #define KXCJK1013_SLEEP_DELAY_MS 2000
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #define KXCJK1013_REG_INT_SRC1_BIT_TPS BIT(0) /* KXTF9 */
104*4882a593Smuzhiyun #define KXCJK1013_REG_INT_SRC1_BIT_WUFS BIT(1)
105*4882a593Smuzhiyun #define KXCJK1013_REG_INT_SRC1_MASK_TDTS (BIT(2) | BIT(3)) /* KXTF9 */
106*4882a593Smuzhiyun #define KXCJK1013_REG_INT_SRC1_TAP_NONE 0
107*4882a593Smuzhiyun #define KXCJK1013_REG_INT_SRC1_TAP_SINGLE BIT(2)
108*4882a593Smuzhiyun #define KXCJK1013_REG_INT_SRC1_TAP_DOUBLE BIT(3)
109*4882a593Smuzhiyun #define KXCJK1013_REG_INT_SRC1_BIT_DRDY BIT(4)
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* KXCJK: INT_SOURCE2: motion detect, KXTF9: INT_SRC_REG1: tap detect */
112*4882a593Smuzhiyun #define KXCJK1013_REG_INT_SRC2_BIT_ZP BIT(0)
113*4882a593Smuzhiyun #define KXCJK1013_REG_INT_SRC2_BIT_ZN BIT(1)
114*4882a593Smuzhiyun #define KXCJK1013_REG_INT_SRC2_BIT_YP BIT(2)
115*4882a593Smuzhiyun #define KXCJK1013_REG_INT_SRC2_BIT_YN BIT(3)
116*4882a593Smuzhiyun #define KXCJK1013_REG_INT_SRC2_BIT_XP BIT(4)
117*4882a593Smuzhiyun #define KXCJK1013_REG_INT_SRC2_BIT_XN BIT(5)
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun #define KXCJK1013_DEFAULT_WAKE_THRES 1
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun enum kx_chipset {
122*4882a593Smuzhiyun KXCJK1013,
123*4882a593Smuzhiyun KXCJ91008,
124*4882a593Smuzhiyun KXTJ21009,
125*4882a593Smuzhiyun KXTF9,
126*4882a593Smuzhiyun KX_MAX_CHIPS /* this must be last */
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun enum kx_acpi_type {
130*4882a593Smuzhiyun ACPI_GENERIC,
131*4882a593Smuzhiyun ACPI_SMO8500,
132*4882a593Smuzhiyun ACPI_KIOX010A,
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun enum kxcjk1013_axis {
136*4882a593Smuzhiyun AXIS_X,
137*4882a593Smuzhiyun AXIS_Y,
138*4882a593Smuzhiyun AXIS_Z,
139*4882a593Smuzhiyun AXIS_MAX
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun struct kxcjk1013_data {
143*4882a593Smuzhiyun struct i2c_client *client;
144*4882a593Smuzhiyun struct iio_trigger *dready_trig;
145*4882a593Smuzhiyun struct iio_trigger *motion_trig;
146*4882a593Smuzhiyun struct iio_mount_matrix orientation;
147*4882a593Smuzhiyun struct mutex mutex;
148*4882a593Smuzhiyun /* Ensure timestamp naturally aligned */
149*4882a593Smuzhiyun struct {
150*4882a593Smuzhiyun s16 chans[AXIS_MAX];
151*4882a593Smuzhiyun s64 timestamp __aligned(8);
152*4882a593Smuzhiyun } scan;
153*4882a593Smuzhiyun u8 odr_bits;
154*4882a593Smuzhiyun u8 range;
155*4882a593Smuzhiyun int wake_thres;
156*4882a593Smuzhiyun int wake_dur;
157*4882a593Smuzhiyun bool active_high_intr;
158*4882a593Smuzhiyun bool dready_trigger_on;
159*4882a593Smuzhiyun int ev_enable_state;
160*4882a593Smuzhiyun bool motion_trigger_on;
161*4882a593Smuzhiyun int64_t timestamp;
162*4882a593Smuzhiyun enum kx_chipset chipset;
163*4882a593Smuzhiyun enum kx_acpi_type acpi_type;
164*4882a593Smuzhiyun };
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun enum kxcjk1013_mode {
167*4882a593Smuzhiyun STANDBY,
168*4882a593Smuzhiyun OPERATION,
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun enum kxcjk1013_range {
172*4882a593Smuzhiyun KXCJK1013_RANGE_2G,
173*4882a593Smuzhiyun KXCJK1013_RANGE_4G,
174*4882a593Smuzhiyun KXCJK1013_RANGE_8G,
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun struct kx_odr_map {
178*4882a593Smuzhiyun int val;
179*4882a593Smuzhiyun int val2;
180*4882a593Smuzhiyun int odr_bits;
181*4882a593Smuzhiyun int wuf_bits;
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun static const struct kx_odr_map samp_freq_table[] = {
185*4882a593Smuzhiyun { 0, 781000, 0x08, 0x00 },
186*4882a593Smuzhiyun { 1, 563000, 0x09, 0x01 },
187*4882a593Smuzhiyun { 3, 125000, 0x0A, 0x02 },
188*4882a593Smuzhiyun { 6, 250000, 0x0B, 0x03 },
189*4882a593Smuzhiyun { 12, 500000, 0x00, 0x04 },
190*4882a593Smuzhiyun { 25, 0, 0x01, 0x05 },
191*4882a593Smuzhiyun { 50, 0, 0x02, 0x06 },
192*4882a593Smuzhiyun { 100, 0, 0x03, 0x06 },
193*4882a593Smuzhiyun { 200, 0, 0x04, 0x06 },
194*4882a593Smuzhiyun { 400, 0, 0x05, 0x06 },
195*4882a593Smuzhiyun { 800, 0, 0x06, 0x06 },
196*4882a593Smuzhiyun { 1600, 0, 0x07, 0x06 },
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun static const char *const kxcjk1013_samp_freq_avail =
200*4882a593Smuzhiyun "0.781000 1.563000 3.125000 6.250000 12.500000 25 50 100 200 400 800 1600";
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun static const struct kx_odr_map kxtf9_samp_freq_table[] = {
203*4882a593Smuzhiyun { 25, 0, 0x01, 0x00 },
204*4882a593Smuzhiyun { 50, 0, 0x02, 0x01 },
205*4882a593Smuzhiyun { 100, 0, 0x03, 0x01 },
206*4882a593Smuzhiyun { 200, 0, 0x04, 0x01 },
207*4882a593Smuzhiyun { 400, 0, 0x05, 0x01 },
208*4882a593Smuzhiyun { 800, 0, 0x06, 0x01 },
209*4882a593Smuzhiyun };
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun static const char *const kxtf9_samp_freq_avail =
212*4882a593Smuzhiyun "25 50 100 200 400 800";
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun /* Refer to section 4 of the specification */
215*4882a593Smuzhiyun static const struct {
216*4882a593Smuzhiyun int odr_bits;
217*4882a593Smuzhiyun int usec;
218*4882a593Smuzhiyun } odr_start_up_times[KX_MAX_CHIPS][12] = {
219*4882a593Smuzhiyun /* KXCJK-1013 */
220*4882a593Smuzhiyun {
221*4882a593Smuzhiyun {0x08, 100000},
222*4882a593Smuzhiyun {0x09, 100000},
223*4882a593Smuzhiyun {0x0A, 100000},
224*4882a593Smuzhiyun {0x0B, 100000},
225*4882a593Smuzhiyun {0, 80000},
226*4882a593Smuzhiyun {0x01, 41000},
227*4882a593Smuzhiyun {0x02, 21000},
228*4882a593Smuzhiyun {0x03, 11000},
229*4882a593Smuzhiyun {0x04, 6400},
230*4882a593Smuzhiyun {0x05, 3900},
231*4882a593Smuzhiyun {0x06, 2700},
232*4882a593Smuzhiyun {0x07, 2100},
233*4882a593Smuzhiyun },
234*4882a593Smuzhiyun /* KXCJ9-1008 */
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun {0x08, 100000},
237*4882a593Smuzhiyun {0x09, 100000},
238*4882a593Smuzhiyun {0x0A, 100000},
239*4882a593Smuzhiyun {0x0B, 100000},
240*4882a593Smuzhiyun {0, 80000},
241*4882a593Smuzhiyun {0x01, 41000},
242*4882a593Smuzhiyun {0x02, 21000},
243*4882a593Smuzhiyun {0x03, 11000},
244*4882a593Smuzhiyun {0x04, 6400},
245*4882a593Smuzhiyun {0x05, 3900},
246*4882a593Smuzhiyun {0x06, 2700},
247*4882a593Smuzhiyun {0x07, 2100},
248*4882a593Smuzhiyun },
249*4882a593Smuzhiyun /* KXCTJ2-1009 */
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun {0x08, 1240000},
252*4882a593Smuzhiyun {0x09, 621000},
253*4882a593Smuzhiyun {0x0A, 309000},
254*4882a593Smuzhiyun {0x0B, 151000},
255*4882a593Smuzhiyun {0, 80000},
256*4882a593Smuzhiyun {0x01, 41000},
257*4882a593Smuzhiyun {0x02, 21000},
258*4882a593Smuzhiyun {0x03, 11000},
259*4882a593Smuzhiyun {0x04, 6000},
260*4882a593Smuzhiyun {0x05, 4000},
261*4882a593Smuzhiyun {0x06, 3000},
262*4882a593Smuzhiyun {0x07, 2000},
263*4882a593Smuzhiyun },
264*4882a593Smuzhiyun /* KXTF9 */
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun {0x01, 81000},
267*4882a593Smuzhiyun {0x02, 41000},
268*4882a593Smuzhiyun {0x03, 21000},
269*4882a593Smuzhiyun {0x04, 11000},
270*4882a593Smuzhiyun {0x05, 5100},
271*4882a593Smuzhiyun {0x06, 2700},
272*4882a593Smuzhiyun },
273*4882a593Smuzhiyun };
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun static const struct {
276*4882a593Smuzhiyun u16 scale;
277*4882a593Smuzhiyun u8 gsel_0;
278*4882a593Smuzhiyun u8 gsel_1;
279*4882a593Smuzhiyun } KXCJK1013_scale_table[] = { {9582, 0, 0},
280*4882a593Smuzhiyun {19163, 1, 0},
281*4882a593Smuzhiyun {38326, 0, 1} };
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun #ifdef CONFIG_ACPI
284*4882a593Smuzhiyun enum kiox010a_fn_index {
285*4882a593Smuzhiyun KIOX010A_SET_LAPTOP_MODE = 1,
286*4882a593Smuzhiyun KIOX010A_SET_TABLET_MODE = 2,
287*4882a593Smuzhiyun };
288*4882a593Smuzhiyun
kiox010a_dsm(struct device * dev,int fn_index)289*4882a593Smuzhiyun static int kiox010a_dsm(struct device *dev, int fn_index)
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun acpi_handle handle = ACPI_HANDLE(dev);
292*4882a593Smuzhiyun guid_t kiox010a_dsm_guid;
293*4882a593Smuzhiyun union acpi_object *obj;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun if (!handle)
296*4882a593Smuzhiyun return -ENODEV;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun guid_parse("1f339696-d475-4e26-8cad-2e9f8e6d7a91", &kiox010a_dsm_guid);
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun obj = acpi_evaluate_dsm(handle, &kiox010a_dsm_guid, 1, fn_index, NULL);
301*4882a593Smuzhiyun if (!obj)
302*4882a593Smuzhiyun return -EIO;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun ACPI_FREE(obj);
305*4882a593Smuzhiyun return 0;
306*4882a593Smuzhiyun }
307*4882a593Smuzhiyun #endif
308*4882a593Smuzhiyun
kxcjk1013_set_mode(struct kxcjk1013_data * data,enum kxcjk1013_mode mode)309*4882a593Smuzhiyun static int kxcjk1013_set_mode(struct kxcjk1013_data *data,
310*4882a593Smuzhiyun enum kxcjk1013_mode mode)
311*4882a593Smuzhiyun {
312*4882a593Smuzhiyun int ret;
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
315*4882a593Smuzhiyun if (ret < 0) {
316*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
317*4882a593Smuzhiyun return ret;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun if (mode == STANDBY)
321*4882a593Smuzhiyun ret &= ~KXCJK1013_REG_CTRL1_BIT_PC1;
322*4882a593Smuzhiyun else
323*4882a593Smuzhiyun ret |= KXCJK1013_REG_CTRL1_BIT_PC1;
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client,
326*4882a593Smuzhiyun KXCJK1013_REG_CTRL1, ret);
327*4882a593Smuzhiyun if (ret < 0) {
328*4882a593Smuzhiyun dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
329*4882a593Smuzhiyun return ret;
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun return 0;
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
kxcjk1013_get_mode(struct kxcjk1013_data * data,enum kxcjk1013_mode * mode)335*4882a593Smuzhiyun static int kxcjk1013_get_mode(struct kxcjk1013_data *data,
336*4882a593Smuzhiyun enum kxcjk1013_mode *mode)
337*4882a593Smuzhiyun {
338*4882a593Smuzhiyun int ret;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
341*4882a593Smuzhiyun if (ret < 0) {
342*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
343*4882a593Smuzhiyun return ret;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun if (ret & KXCJK1013_REG_CTRL1_BIT_PC1)
347*4882a593Smuzhiyun *mode = OPERATION;
348*4882a593Smuzhiyun else
349*4882a593Smuzhiyun *mode = STANDBY;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun return 0;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun
kxcjk1013_set_range(struct kxcjk1013_data * data,int range_index)354*4882a593Smuzhiyun static int kxcjk1013_set_range(struct kxcjk1013_data *data, int range_index)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun int ret;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
359*4882a593Smuzhiyun if (ret < 0) {
360*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
361*4882a593Smuzhiyun return ret;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun ret &= ~(KXCJK1013_REG_CTRL1_BIT_GSEL0 |
365*4882a593Smuzhiyun KXCJK1013_REG_CTRL1_BIT_GSEL1);
366*4882a593Smuzhiyun ret |= (KXCJK1013_scale_table[range_index].gsel_0 << 3);
367*4882a593Smuzhiyun ret |= (KXCJK1013_scale_table[range_index].gsel_1 << 4);
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client,
370*4882a593Smuzhiyun KXCJK1013_REG_CTRL1,
371*4882a593Smuzhiyun ret);
372*4882a593Smuzhiyun if (ret < 0) {
373*4882a593Smuzhiyun dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
374*4882a593Smuzhiyun return ret;
375*4882a593Smuzhiyun }
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun data->range = range_index;
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun return 0;
380*4882a593Smuzhiyun }
381*4882a593Smuzhiyun
kxcjk1013_chip_init(struct kxcjk1013_data * data)382*4882a593Smuzhiyun static int kxcjk1013_chip_init(struct kxcjk1013_data *data)
383*4882a593Smuzhiyun {
384*4882a593Smuzhiyun int ret;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun #ifdef CONFIG_ACPI
387*4882a593Smuzhiyun if (data->acpi_type == ACPI_KIOX010A) {
388*4882a593Smuzhiyun /* Make sure the kbd and touchpad on 2-in-1s using 2 KXCJ91008-s work */
389*4882a593Smuzhiyun kiox010a_dsm(&data->client->dev, KIOX010A_SET_LAPTOP_MODE);
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun #endif
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_WHO_AM_I);
394*4882a593Smuzhiyun if (ret < 0) {
395*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading who_am_i\n");
396*4882a593Smuzhiyun return ret;
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun dev_dbg(&data->client->dev, "KXCJK1013 Chip Id %x\n", ret);
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun ret = kxcjk1013_set_mode(data, STANDBY);
402*4882a593Smuzhiyun if (ret < 0)
403*4882a593Smuzhiyun return ret;
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
406*4882a593Smuzhiyun if (ret < 0) {
407*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
408*4882a593Smuzhiyun return ret;
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun /* Set 12 bit mode */
412*4882a593Smuzhiyun ret |= KXCJK1013_REG_CTRL1_BIT_RES;
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_CTRL1,
415*4882a593Smuzhiyun ret);
416*4882a593Smuzhiyun if (ret < 0) {
417*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading reg_ctrl\n");
418*4882a593Smuzhiyun return ret;
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun /* Setting range to 4G */
422*4882a593Smuzhiyun ret = kxcjk1013_set_range(data, KXCJK1013_RANGE_4G);
423*4882a593Smuzhiyun if (ret < 0)
424*4882a593Smuzhiyun return ret;
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_DATA_CTRL);
427*4882a593Smuzhiyun if (ret < 0) {
428*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading reg_data_ctrl\n");
429*4882a593Smuzhiyun return ret;
430*4882a593Smuzhiyun }
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun data->odr_bits = ret;
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun /* Set up INT polarity */
435*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_CTRL1);
436*4882a593Smuzhiyun if (ret < 0) {
437*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
438*4882a593Smuzhiyun return ret;
439*4882a593Smuzhiyun }
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun if (data->active_high_intr)
442*4882a593Smuzhiyun ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEA;
443*4882a593Smuzhiyun else
444*4882a593Smuzhiyun ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEA;
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
447*4882a593Smuzhiyun ret);
448*4882a593Smuzhiyun if (ret < 0) {
449*4882a593Smuzhiyun dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
450*4882a593Smuzhiyun return ret;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun ret = kxcjk1013_set_mode(data, OPERATION);
454*4882a593Smuzhiyun if (ret < 0)
455*4882a593Smuzhiyun return ret;
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun data->wake_thres = KXCJK1013_DEFAULT_WAKE_THRES;
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun return 0;
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun #ifdef CONFIG_PM
kxcjk1013_get_startup_times(struct kxcjk1013_data * data)463*4882a593Smuzhiyun static int kxcjk1013_get_startup_times(struct kxcjk1013_data *data)
464*4882a593Smuzhiyun {
465*4882a593Smuzhiyun int i;
466*4882a593Smuzhiyun int idx = data->chipset;
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(odr_start_up_times[idx]); ++i) {
469*4882a593Smuzhiyun if (odr_start_up_times[idx][i].odr_bits == data->odr_bits)
470*4882a593Smuzhiyun return odr_start_up_times[idx][i].usec;
471*4882a593Smuzhiyun }
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun return KXCJK1013_MAX_STARTUP_TIME_US;
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun #endif
476*4882a593Smuzhiyun
kxcjk1013_set_power_state(struct kxcjk1013_data * data,bool on)477*4882a593Smuzhiyun static int kxcjk1013_set_power_state(struct kxcjk1013_data *data, bool on)
478*4882a593Smuzhiyun {
479*4882a593Smuzhiyun #ifdef CONFIG_PM
480*4882a593Smuzhiyun int ret;
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun if (on)
483*4882a593Smuzhiyun ret = pm_runtime_get_sync(&data->client->dev);
484*4882a593Smuzhiyun else {
485*4882a593Smuzhiyun pm_runtime_mark_last_busy(&data->client->dev);
486*4882a593Smuzhiyun ret = pm_runtime_put_autosuspend(&data->client->dev);
487*4882a593Smuzhiyun }
488*4882a593Smuzhiyun if (ret < 0) {
489*4882a593Smuzhiyun dev_err(&data->client->dev,
490*4882a593Smuzhiyun "Failed: %s for %d\n", __func__, on);
491*4882a593Smuzhiyun if (on)
492*4882a593Smuzhiyun pm_runtime_put_noidle(&data->client->dev);
493*4882a593Smuzhiyun return ret;
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun #endif
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun return 0;
498*4882a593Smuzhiyun }
499*4882a593Smuzhiyun
kxcjk1013_chip_update_thresholds(struct kxcjk1013_data * data)500*4882a593Smuzhiyun static int kxcjk1013_chip_update_thresholds(struct kxcjk1013_data *data)
501*4882a593Smuzhiyun {
502*4882a593Smuzhiyun int waketh_reg, ret;
503*4882a593Smuzhiyun
504*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client,
505*4882a593Smuzhiyun KXCJK1013_REG_WAKE_TIMER,
506*4882a593Smuzhiyun data->wake_dur);
507*4882a593Smuzhiyun if (ret < 0) {
508*4882a593Smuzhiyun dev_err(&data->client->dev,
509*4882a593Smuzhiyun "Error writing reg_wake_timer\n");
510*4882a593Smuzhiyun return ret;
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun waketh_reg = data->chipset == KXTF9 ?
514*4882a593Smuzhiyun KXTF9_REG_WAKE_THRESH : KXCJK1013_REG_WAKE_THRES;
515*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client, waketh_reg,
516*4882a593Smuzhiyun data->wake_thres);
517*4882a593Smuzhiyun if (ret < 0) {
518*4882a593Smuzhiyun dev_err(&data->client->dev, "Error writing reg_wake_thres\n");
519*4882a593Smuzhiyun return ret;
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun return 0;
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun
kxcjk1013_setup_any_motion_interrupt(struct kxcjk1013_data * data,bool status)525*4882a593Smuzhiyun static int kxcjk1013_setup_any_motion_interrupt(struct kxcjk1013_data *data,
526*4882a593Smuzhiyun bool status)
527*4882a593Smuzhiyun {
528*4882a593Smuzhiyun int ret;
529*4882a593Smuzhiyun enum kxcjk1013_mode store_mode;
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun ret = kxcjk1013_get_mode(data, &store_mode);
532*4882a593Smuzhiyun if (ret < 0)
533*4882a593Smuzhiyun return ret;
534*4882a593Smuzhiyun
535*4882a593Smuzhiyun /* This is requirement by spec to change state to STANDBY */
536*4882a593Smuzhiyun ret = kxcjk1013_set_mode(data, STANDBY);
537*4882a593Smuzhiyun if (ret < 0)
538*4882a593Smuzhiyun return ret;
539*4882a593Smuzhiyun
540*4882a593Smuzhiyun ret = kxcjk1013_chip_update_thresholds(data);
541*4882a593Smuzhiyun if (ret < 0)
542*4882a593Smuzhiyun return ret;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_CTRL1);
545*4882a593Smuzhiyun if (ret < 0) {
546*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
547*4882a593Smuzhiyun return ret;
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun if (status)
551*4882a593Smuzhiyun ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEN;
552*4882a593Smuzhiyun else
553*4882a593Smuzhiyun ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEN;
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
556*4882a593Smuzhiyun ret);
557*4882a593Smuzhiyun if (ret < 0) {
558*4882a593Smuzhiyun dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
559*4882a593Smuzhiyun return ret;
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
563*4882a593Smuzhiyun if (ret < 0) {
564*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
565*4882a593Smuzhiyun return ret;
566*4882a593Smuzhiyun }
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun if (status)
569*4882a593Smuzhiyun ret |= KXCJK1013_REG_CTRL1_BIT_WUFE;
570*4882a593Smuzhiyun else
571*4882a593Smuzhiyun ret &= ~KXCJK1013_REG_CTRL1_BIT_WUFE;
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client,
574*4882a593Smuzhiyun KXCJK1013_REG_CTRL1, ret);
575*4882a593Smuzhiyun if (ret < 0) {
576*4882a593Smuzhiyun dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
577*4882a593Smuzhiyun return ret;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun if (store_mode == OPERATION) {
581*4882a593Smuzhiyun ret = kxcjk1013_set_mode(data, OPERATION);
582*4882a593Smuzhiyun if (ret < 0)
583*4882a593Smuzhiyun return ret;
584*4882a593Smuzhiyun }
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun return 0;
587*4882a593Smuzhiyun }
588*4882a593Smuzhiyun
kxcjk1013_setup_new_data_interrupt(struct kxcjk1013_data * data,bool status)589*4882a593Smuzhiyun static int kxcjk1013_setup_new_data_interrupt(struct kxcjk1013_data *data,
590*4882a593Smuzhiyun bool status)
591*4882a593Smuzhiyun {
592*4882a593Smuzhiyun int ret;
593*4882a593Smuzhiyun enum kxcjk1013_mode store_mode;
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun ret = kxcjk1013_get_mode(data, &store_mode);
596*4882a593Smuzhiyun if (ret < 0)
597*4882a593Smuzhiyun return ret;
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun /* This is requirement by spec to change state to STANDBY */
600*4882a593Smuzhiyun ret = kxcjk1013_set_mode(data, STANDBY);
601*4882a593Smuzhiyun if (ret < 0)
602*4882a593Smuzhiyun return ret;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_CTRL1);
605*4882a593Smuzhiyun if (ret < 0) {
606*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading reg_int_ctrl1\n");
607*4882a593Smuzhiyun return ret;
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun if (status)
611*4882a593Smuzhiyun ret |= KXCJK1013_REG_INT_CTRL1_BIT_IEN;
612*4882a593Smuzhiyun else
613*4882a593Smuzhiyun ret &= ~KXCJK1013_REG_INT_CTRL1_BIT_IEN;
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_INT_CTRL1,
616*4882a593Smuzhiyun ret);
617*4882a593Smuzhiyun if (ret < 0) {
618*4882a593Smuzhiyun dev_err(&data->client->dev, "Error writing reg_int_ctrl1\n");
619*4882a593Smuzhiyun return ret;
620*4882a593Smuzhiyun }
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_CTRL1);
623*4882a593Smuzhiyun if (ret < 0) {
624*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading reg_ctrl1\n");
625*4882a593Smuzhiyun return ret;
626*4882a593Smuzhiyun }
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun if (status)
629*4882a593Smuzhiyun ret |= KXCJK1013_REG_CTRL1_BIT_DRDY;
630*4882a593Smuzhiyun else
631*4882a593Smuzhiyun ret &= ~KXCJK1013_REG_CTRL1_BIT_DRDY;
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client,
634*4882a593Smuzhiyun KXCJK1013_REG_CTRL1, ret);
635*4882a593Smuzhiyun if (ret < 0) {
636*4882a593Smuzhiyun dev_err(&data->client->dev, "Error writing reg_ctrl1\n");
637*4882a593Smuzhiyun return ret;
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun
640*4882a593Smuzhiyun if (store_mode == OPERATION) {
641*4882a593Smuzhiyun ret = kxcjk1013_set_mode(data, OPERATION);
642*4882a593Smuzhiyun if (ret < 0)
643*4882a593Smuzhiyun return ret;
644*4882a593Smuzhiyun }
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun return 0;
647*4882a593Smuzhiyun }
648*4882a593Smuzhiyun
kxcjk1013_find_odr_value(const struct kx_odr_map * map,size_t map_size,int val,int val2)649*4882a593Smuzhiyun static const struct kx_odr_map *kxcjk1013_find_odr_value(
650*4882a593Smuzhiyun const struct kx_odr_map *map, size_t map_size, int val, int val2)
651*4882a593Smuzhiyun {
652*4882a593Smuzhiyun int i;
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun for (i = 0; i < map_size; ++i) {
655*4882a593Smuzhiyun if (map[i].val == val && map[i].val2 == val2)
656*4882a593Smuzhiyun return &map[i];
657*4882a593Smuzhiyun }
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
660*4882a593Smuzhiyun }
661*4882a593Smuzhiyun
kxcjk1013_convert_odr_value(const struct kx_odr_map * map,size_t map_size,int odr_bits,int * val,int * val2)662*4882a593Smuzhiyun static int kxcjk1013_convert_odr_value(const struct kx_odr_map *map,
663*4882a593Smuzhiyun size_t map_size, int odr_bits,
664*4882a593Smuzhiyun int *val, int *val2)
665*4882a593Smuzhiyun {
666*4882a593Smuzhiyun int i;
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun for (i = 0; i < map_size; ++i) {
669*4882a593Smuzhiyun if (map[i].odr_bits == odr_bits) {
670*4882a593Smuzhiyun *val = map[i].val;
671*4882a593Smuzhiyun *val2 = map[i].val2;
672*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
673*4882a593Smuzhiyun }
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun return -EINVAL;
677*4882a593Smuzhiyun }
678*4882a593Smuzhiyun
kxcjk1013_set_odr(struct kxcjk1013_data * data,int val,int val2)679*4882a593Smuzhiyun static int kxcjk1013_set_odr(struct kxcjk1013_data *data, int val, int val2)
680*4882a593Smuzhiyun {
681*4882a593Smuzhiyun int ret;
682*4882a593Smuzhiyun enum kxcjk1013_mode store_mode;
683*4882a593Smuzhiyun const struct kx_odr_map *odr_setting;
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun ret = kxcjk1013_get_mode(data, &store_mode);
686*4882a593Smuzhiyun if (ret < 0)
687*4882a593Smuzhiyun return ret;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun if (data->chipset == KXTF9)
690*4882a593Smuzhiyun odr_setting = kxcjk1013_find_odr_value(kxtf9_samp_freq_table,
691*4882a593Smuzhiyun ARRAY_SIZE(kxtf9_samp_freq_table),
692*4882a593Smuzhiyun val, val2);
693*4882a593Smuzhiyun else
694*4882a593Smuzhiyun odr_setting = kxcjk1013_find_odr_value(samp_freq_table,
695*4882a593Smuzhiyun ARRAY_SIZE(samp_freq_table),
696*4882a593Smuzhiyun val, val2);
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun if (IS_ERR(odr_setting))
699*4882a593Smuzhiyun return PTR_ERR(odr_setting);
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun /* To change ODR, the chip must be set to STANDBY as per spec */
702*4882a593Smuzhiyun ret = kxcjk1013_set_mode(data, STANDBY);
703*4882a593Smuzhiyun if (ret < 0)
704*4882a593Smuzhiyun return ret;
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_DATA_CTRL,
707*4882a593Smuzhiyun odr_setting->odr_bits);
708*4882a593Smuzhiyun if (ret < 0) {
709*4882a593Smuzhiyun dev_err(&data->client->dev, "Error writing data_ctrl\n");
710*4882a593Smuzhiyun return ret;
711*4882a593Smuzhiyun }
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun data->odr_bits = odr_setting->odr_bits;
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client, KXCJK1013_REG_CTRL2,
716*4882a593Smuzhiyun odr_setting->wuf_bits);
717*4882a593Smuzhiyun if (ret < 0) {
718*4882a593Smuzhiyun dev_err(&data->client->dev, "Error writing reg_ctrl2\n");
719*4882a593Smuzhiyun return ret;
720*4882a593Smuzhiyun }
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun if (store_mode == OPERATION) {
723*4882a593Smuzhiyun ret = kxcjk1013_set_mode(data, OPERATION);
724*4882a593Smuzhiyun if (ret < 0)
725*4882a593Smuzhiyun return ret;
726*4882a593Smuzhiyun }
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun return 0;
729*4882a593Smuzhiyun }
730*4882a593Smuzhiyun
kxcjk1013_get_odr(struct kxcjk1013_data * data,int * val,int * val2)731*4882a593Smuzhiyun static int kxcjk1013_get_odr(struct kxcjk1013_data *data, int *val, int *val2)
732*4882a593Smuzhiyun {
733*4882a593Smuzhiyun if (data->chipset == KXTF9)
734*4882a593Smuzhiyun return kxcjk1013_convert_odr_value(kxtf9_samp_freq_table,
735*4882a593Smuzhiyun ARRAY_SIZE(kxtf9_samp_freq_table),
736*4882a593Smuzhiyun data->odr_bits, val, val2);
737*4882a593Smuzhiyun else
738*4882a593Smuzhiyun return kxcjk1013_convert_odr_value(samp_freq_table,
739*4882a593Smuzhiyun ARRAY_SIZE(samp_freq_table),
740*4882a593Smuzhiyun data->odr_bits, val, val2);
741*4882a593Smuzhiyun }
742*4882a593Smuzhiyun
kxcjk1013_get_acc_reg(struct kxcjk1013_data * data,int axis)743*4882a593Smuzhiyun static int kxcjk1013_get_acc_reg(struct kxcjk1013_data *data, int axis)
744*4882a593Smuzhiyun {
745*4882a593Smuzhiyun u8 reg = KXCJK1013_REG_XOUT_L + axis * 2;
746*4882a593Smuzhiyun int ret;
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun ret = i2c_smbus_read_word_data(data->client, reg);
749*4882a593Smuzhiyun if (ret < 0) {
750*4882a593Smuzhiyun dev_err(&data->client->dev,
751*4882a593Smuzhiyun "failed to read accel_%c registers\n", 'x' + axis);
752*4882a593Smuzhiyun return ret;
753*4882a593Smuzhiyun }
754*4882a593Smuzhiyun
755*4882a593Smuzhiyun return ret;
756*4882a593Smuzhiyun }
757*4882a593Smuzhiyun
kxcjk1013_set_scale(struct kxcjk1013_data * data,int val)758*4882a593Smuzhiyun static int kxcjk1013_set_scale(struct kxcjk1013_data *data, int val)
759*4882a593Smuzhiyun {
760*4882a593Smuzhiyun int ret, i;
761*4882a593Smuzhiyun enum kxcjk1013_mode store_mode;
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(KXCJK1013_scale_table); ++i) {
764*4882a593Smuzhiyun if (KXCJK1013_scale_table[i].scale == val) {
765*4882a593Smuzhiyun ret = kxcjk1013_get_mode(data, &store_mode);
766*4882a593Smuzhiyun if (ret < 0)
767*4882a593Smuzhiyun return ret;
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun ret = kxcjk1013_set_mode(data, STANDBY);
770*4882a593Smuzhiyun if (ret < 0)
771*4882a593Smuzhiyun return ret;
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun ret = kxcjk1013_set_range(data, i);
774*4882a593Smuzhiyun if (ret < 0)
775*4882a593Smuzhiyun return ret;
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun if (store_mode == OPERATION) {
778*4882a593Smuzhiyun ret = kxcjk1013_set_mode(data, OPERATION);
779*4882a593Smuzhiyun if (ret)
780*4882a593Smuzhiyun return ret;
781*4882a593Smuzhiyun }
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun return 0;
784*4882a593Smuzhiyun }
785*4882a593Smuzhiyun }
786*4882a593Smuzhiyun
787*4882a593Smuzhiyun return -EINVAL;
788*4882a593Smuzhiyun }
789*4882a593Smuzhiyun
kxcjk1013_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)790*4882a593Smuzhiyun static int kxcjk1013_read_raw(struct iio_dev *indio_dev,
791*4882a593Smuzhiyun struct iio_chan_spec const *chan, int *val,
792*4882a593Smuzhiyun int *val2, long mask)
793*4882a593Smuzhiyun {
794*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
795*4882a593Smuzhiyun int ret;
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun switch (mask) {
798*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
799*4882a593Smuzhiyun mutex_lock(&data->mutex);
800*4882a593Smuzhiyun if (iio_buffer_enabled(indio_dev))
801*4882a593Smuzhiyun ret = -EBUSY;
802*4882a593Smuzhiyun else {
803*4882a593Smuzhiyun ret = kxcjk1013_set_power_state(data, true);
804*4882a593Smuzhiyun if (ret < 0) {
805*4882a593Smuzhiyun mutex_unlock(&data->mutex);
806*4882a593Smuzhiyun return ret;
807*4882a593Smuzhiyun }
808*4882a593Smuzhiyun ret = kxcjk1013_get_acc_reg(data, chan->scan_index);
809*4882a593Smuzhiyun if (ret < 0) {
810*4882a593Smuzhiyun kxcjk1013_set_power_state(data, false);
811*4882a593Smuzhiyun mutex_unlock(&data->mutex);
812*4882a593Smuzhiyun return ret;
813*4882a593Smuzhiyun }
814*4882a593Smuzhiyun *val = sign_extend32(ret >> 4, 11);
815*4882a593Smuzhiyun ret = kxcjk1013_set_power_state(data, false);
816*4882a593Smuzhiyun }
817*4882a593Smuzhiyun mutex_unlock(&data->mutex);
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun if (ret < 0)
820*4882a593Smuzhiyun return ret;
821*4882a593Smuzhiyun
822*4882a593Smuzhiyun return IIO_VAL_INT;
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
825*4882a593Smuzhiyun *val = 0;
826*4882a593Smuzhiyun *val2 = KXCJK1013_scale_table[data->range].scale;
827*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun case IIO_CHAN_INFO_SAMP_FREQ:
830*4882a593Smuzhiyun mutex_lock(&data->mutex);
831*4882a593Smuzhiyun ret = kxcjk1013_get_odr(data, val, val2);
832*4882a593Smuzhiyun mutex_unlock(&data->mutex);
833*4882a593Smuzhiyun return ret;
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun default:
836*4882a593Smuzhiyun return -EINVAL;
837*4882a593Smuzhiyun }
838*4882a593Smuzhiyun }
839*4882a593Smuzhiyun
kxcjk1013_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)840*4882a593Smuzhiyun static int kxcjk1013_write_raw(struct iio_dev *indio_dev,
841*4882a593Smuzhiyun struct iio_chan_spec const *chan, int val,
842*4882a593Smuzhiyun int val2, long mask)
843*4882a593Smuzhiyun {
844*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
845*4882a593Smuzhiyun int ret;
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun switch (mask) {
848*4882a593Smuzhiyun case IIO_CHAN_INFO_SAMP_FREQ:
849*4882a593Smuzhiyun mutex_lock(&data->mutex);
850*4882a593Smuzhiyun ret = kxcjk1013_set_odr(data, val, val2);
851*4882a593Smuzhiyun mutex_unlock(&data->mutex);
852*4882a593Smuzhiyun break;
853*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
854*4882a593Smuzhiyun if (val)
855*4882a593Smuzhiyun return -EINVAL;
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun mutex_lock(&data->mutex);
858*4882a593Smuzhiyun ret = kxcjk1013_set_scale(data, val2);
859*4882a593Smuzhiyun mutex_unlock(&data->mutex);
860*4882a593Smuzhiyun break;
861*4882a593Smuzhiyun default:
862*4882a593Smuzhiyun ret = -EINVAL;
863*4882a593Smuzhiyun }
864*4882a593Smuzhiyun
865*4882a593Smuzhiyun return ret;
866*4882a593Smuzhiyun }
867*4882a593Smuzhiyun
kxcjk1013_read_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)868*4882a593Smuzhiyun static int kxcjk1013_read_event(struct iio_dev *indio_dev,
869*4882a593Smuzhiyun const struct iio_chan_spec *chan,
870*4882a593Smuzhiyun enum iio_event_type type,
871*4882a593Smuzhiyun enum iio_event_direction dir,
872*4882a593Smuzhiyun enum iio_event_info info,
873*4882a593Smuzhiyun int *val, int *val2)
874*4882a593Smuzhiyun {
875*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
876*4882a593Smuzhiyun
877*4882a593Smuzhiyun *val2 = 0;
878*4882a593Smuzhiyun switch (info) {
879*4882a593Smuzhiyun case IIO_EV_INFO_VALUE:
880*4882a593Smuzhiyun *val = data->wake_thres;
881*4882a593Smuzhiyun break;
882*4882a593Smuzhiyun case IIO_EV_INFO_PERIOD:
883*4882a593Smuzhiyun *val = data->wake_dur;
884*4882a593Smuzhiyun break;
885*4882a593Smuzhiyun default:
886*4882a593Smuzhiyun return -EINVAL;
887*4882a593Smuzhiyun }
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun return IIO_VAL_INT;
890*4882a593Smuzhiyun }
891*4882a593Smuzhiyun
kxcjk1013_write_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)892*4882a593Smuzhiyun static int kxcjk1013_write_event(struct iio_dev *indio_dev,
893*4882a593Smuzhiyun const struct iio_chan_spec *chan,
894*4882a593Smuzhiyun enum iio_event_type type,
895*4882a593Smuzhiyun enum iio_event_direction dir,
896*4882a593Smuzhiyun enum iio_event_info info,
897*4882a593Smuzhiyun int val, int val2)
898*4882a593Smuzhiyun {
899*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun if (data->ev_enable_state)
902*4882a593Smuzhiyun return -EBUSY;
903*4882a593Smuzhiyun
904*4882a593Smuzhiyun switch (info) {
905*4882a593Smuzhiyun case IIO_EV_INFO_VALUE:
906*4882a593Smuzhiyun data->wake_thres = val;
907*4882a593Smuzhiyun break;
908*4882a593Smuzhiyun case IIO_EV_INFO_PERIOD:
909*4882a593Smuzhiyun data->wake_dur = val;
910*4882a593Smuzhiyun break;
911*4882a593Smuzhiyun default:
912*4882a593Smuzhiyun return -EINVAL;
913*4882a593Smuzhiyun }
914*4882a593Smuzhiyun
915*4882a593Smuzhiyun return 0;
916*4882a593Smuzhiyun }
917*4882a593Smuzhiyun
kxcjk1013_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)918*4882a593Smuzhiyun static int kxcjk1013_read_event_config(struct iio_dev *indio_dev,
919*4882a593Smuzhiyun const struct iio_chan_spec *chan,
920*4882a593Smuzhiyun enum iio_event_type type,
921*4882a593Smuzhiyun enum iio_event_direction dir)
922*4882a593Smuzhiyun {
923*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun return data->ev_enable_state;
926*4882a593Smuzhiyun }
927*4882a593Smuzhiyun
kxcjk1013_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)928*4882a593Smuzhiyun static int kxcjk1013_write_event_config(struct iio_dev *indio_dev,
929*4882a593Smuzhiyun const struct iio_chan_spec *chan,
930*4882a593Smuzhiyun enum iio_event_type type,
931*4882a593Smuzhiyun enum iio_event_direction dir,
932*4882a593Smuzhiyun int state)
933*4882a593Smuzhiyun {
934*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
935*4882a593Smuzhiyun int ret;
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun if (state && data->ev_enable_state)
938*4882a593Smuzhiyun return 0;
939*4882a593Smuzhiyun
940*4882a593Smuzhiyun mutex_lock(&data->mutex);
941*4882a593Smuzhiyun
942*4882a593Smuzhiyun if (!state && data->motion_trigger_on) {
943*4882a593Smuzhiyun data->ev_enable_state = 0;
944*4882a593Smuzhiyun mutex_unlock(&data->mutex);
945*4882a593Smuzhiyun return 0;
946*4882a593Smuzhiyun }
947*4882a593Smuzhiyun
948*4882a593Smuzhiyun /*
949*4882a593Smuzhiyun * We will expect the enable and disable to do operation in
950*4882a593Smuzhiyun * in reverse order. This will happen here anyway as our
951*4882a593Smuzhiyun * resume operation uses sync mode runtime pm calls, the
952*4882a593Smuzhiyun * suspend operation will be delayed by autosuspend delay
953*4882a593Smuzhiyun * So the disable operation will still happen in reverse of
954*4882a593Smuzhiyun * enable operation. When runtime pm is disabled the mode
955*4882a593Smuzhiyun * is always on so sequence doesn't matter
956*4882a593Smuzhiyun */
957*4882a593Smuzhiyun ret = kxcjk1013_set_power_state(data, state);
958*4882a593Smuzhiyun if (ret < 0) {
959*4882a593Smuzhiyun mutex_unlock(&data->mutex);
960*4882a593Smuzhiyun return ret;
961*4882a593Smuzhiyun }
962*4882a593Smuzhiyun
963*4882a593Smuzhiyun ret = kxcjk1013_setup_any_motion_interrupt(data, state);
964*4882a593Smuzhiyun if (ret < 0) {
965*4882a593Smuzhiyun kxcjk1013_set_power_state(data, false);
966*4882a593Smuzhiyun data->ev_enable_state = 0;
967*4882a593Smuzhiyun mutex_unlock(&data->mutex);
968*4882a593Smuzhiyun return ret;
969*4882a593Smuzhiyun }
970*4882a593Smuzhiyun
971*4882a593Smuzhiyun data->ev_enable_state = state;
972*4882a593Smuzhiyun mutex_unlock(&data->mutex);
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun return 0;
975*4882a593Smuzhiyun }
976*4882a593Smuzhiyun
kxcjk1013_buffer_preenable(struct iio_dev * indio_dev)977*4882a593Smuzhiyun static int kxcjk1013_buffer_preenable(struct iio_dev *indio_dev)
978*4882a593Smuzhiyun {
979*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
980*4882a593Smuzhiyun
981*4882a593Smuzhiyun return kxcjk1013_set_power_state(data, true);
982*4882a593Smuzhiyun }
983*4882a593Smuzhiyun
kxcjk1013_buffer_postdisable(struct iio_dev * indio_dev)984*4882a593Smuzhiyun static int kxcjk1013_buffer_postdisable(struct iio_dev *indio_dev)
985*4882a593Smuzhiyun {
986*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
987*4882a593Smuzhiyun
988*4882a593Smuzhiyun return kxcjk1013_set_power_state(data, false);
989*4882a593Smuzhiyun }
990*4882a593Smuzhiyun
kxcjk1013_get_samp_freq_avail(struct device * dev,struct device_attribute * attr,char * buf)991*4882a593Smuzhiyun static ssize_t kxcjk1013_get_samp_freq_avail(struct device *dev,
992*4882a593Smuzhiyun struct device_attribute *attr,
993*4882a593Smuzhiyun char *buf)
994*4882a593Smuzhiyun {
995*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_to_iio_dev(dev);
996*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
997*4882a593Smuzhiyun const char *str;
998*4882a593Smuzhiyun
999*4882a593Smuzhiyun if (data->chipset == KXTF9)
1000*4882a593Smuzhiyun str = kxtf9_samp_freq_avail;
1001*4882a593Smuzhiyun else
1002*4882a593Smuzhiyun str = kxcjk1013_samp_freq_avail;
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun return sprintf(buf, "%s\n", str);
1005*4882a593Smuzhiyun }
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun static IIO_DEVICE_ATTR(in_accel_sampling_frequency_available, S_IRUGO,
1008*4882a593Smuzhiyun kxcjk1013_get_samp_freq_avail, NULL, 0);
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019163 0.038326");
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun static struct attribute *kxcjk1013_attributes[] = {
1013*4882a593Smuzhiyun &iio_dev_attr_in_accel_sampling_frequency_available.dev_attr.attr,
1014*4882a593Smuzhiyun &iio_const_attr_in_accel_scale_available.dev_attr.attr,
1015*4882a593Smuzhiyun NULL,
1016*4882a593Smuzhiyun };
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun static const struct attribute_group kxcjk1013_attrs_group = {
1019*4882a593Smuzhiyun .attrs = kxcjk1013_attributes,
1020*4882a593Smuzhiyun };
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun static const struct iio_event_spec kxcjk1013_event = {
1023*4882a593Smuzhiyun .type = IIO_EV_TYPE_THRESH,
1024*4882a593Smuzhiyun .dir = IIO_EV_DIR_EITHER,
1025*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_VALUE) |
1026*4882a593Smuzhiyun BIT(IIO_EV_INFO_ENABLE) |
1027*4882a593Smuzhiyun BIT(IIO_EV_INFO_PERIOD)
1028*4882a593Smuzhiyun };
1029*4882a593Smuzhiyun
1030*4882a593Smuzhiyun static const struct iio_mount_matrix *
kxcjk1013_get_mount_matrix(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)1031*4882a593Smuzhiyun kxcjk1013_get_mount_matrix(const struct iio_dev *indio_dev,
1032*4882a593Smuzhiyun const struct iio_chan_spec *chan)
1033*4882a593Smuzhiyun {
1034*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
1035*4882a593Smuzhiyun
1036*4882a593Smuzhiyun return &data->orientation;
1037*4882a593Smuzhiyun }
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun static const struct iio_chan_spec_ext_info kxcjk1013_ext_info[] = {
1040*4882a593Smuzhiyun IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, kxcjk1013_get_mount_matrix),
1041*4882a593Smuzhiyun { }
1042*4882a593Smuzhiyun };
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun #define KXCJK1013_CHANNEL(_axis) { \
1045*4882a593Smuzhiyun .type = IIO_ACCEL, \
1046*4882a593Smuzhiyun .modified = 1, \
1047*4882a593Smuzhiyun .channel2 = IIO_MOD_##_axis, \
1048*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
1049*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
1050*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1051*4882a593Smuzhiyun .scan_index = AXIS_##_axis, \
1052*4882a593Smuzhiyun .scan_type = { \
1053*4882a593Smuzhiyun .sign = 's', \
1054*4882a593Smuzhiyun .realbits = 12, \
1055*4882a593Smuzhiyun .storagebits = 16, \
1056*4882a593Smuzhiyun .shift = 4, \
1057*4882a593Smuzhiyun .endianness = IIO_LE, \
1058*4882a593Smuzhiyun }, \
1059*4882a593Smuzhiyun .event_spec = &kxcjk1013_event, \
1060*4882a593Smuzhiyun .ext_info = kxcjk1013_ext_info, \
1061*4882a593Smuzhiyun .num_event_specs = 1 \
1062*4882a593Smuzhiyun }
1063*4882a593Smuzhiyun
1064*4882a593Smuzhiyun static const struct iio_chan_spec kxcjk1013_channels[] = {
1065*4882a593Smuzhiyun KXCJK1013_CHANNEL(X),
1066*4882a593Smuzhiyun KXCJK1013_CHANNEL(Y),
1067*4882a593Smuzhiyun KXCJK1013_CHANNEL(Z),
1068*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(3),
1069*4882a593Smuzhiyun };
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun static const struct iio_buffer_setup_ops kxcjk1013_buffer_setup_ops = {
1072*4882a593Smuzhiyun .preenable = kxcjk1013_buffer_preenable,
1073*4882a593Smuzhiyun .postdisable = kxcjk1013_buffer_postdisable,
1074*4882a593Smuzhiyun };
1075*4882a593Smuzhiyun
1076*4882a593Smuzhiyun static const struct iio_info kxcjk1013_info = {
1077*4882a593Smuzhiyun .attrs = &kxcjk1013_attrs_group,
1078*4882a593Smuzhiyun .read_raw = kxcjk1013_read_raw,
1079*4882a593Smuzhiyun .write_raw = kxcjk1013_write_raw,
1080*4882a593Smuzhiyun .read_event_value = kxcjk1013_read_event,
1081*4882a593Smuzhiyun .write_event_value = kxcjk1013_write_event,
1082*4882a593Smuzhiyun .write_event_config = kxcjk1013_write_event_config,
1083*4882a593Smuzhiyun .read_event_config = kxcjk1013_read_event_config,
1084*4882a593Smuzhiyun };
1085*4882a593Smuzhiyun
1086*4882a593Smuzhiyun static const unsigned long kxcjk1013_scan_masks[] = {0x7, 0};
1087*4882a593Smuzhiyun
kxcjk1013_trigger_handler(int irq,void * p)1088*4882a593Smuzhiyun static irqreturn_t kxcjk1013_trigger_handler(int irq, void *p)
1089*4882a593Smuzhiyun {
1090*4882a593Smuzhiyun struct iio_poll_func *pf = p;
1091*4882a593Smuzhiyun struct iio_dev *indio_dev = pf->indio_dev;
1092*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
1093*4882a593Smuzhiyun int ret;
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun mutex_lock(&data->mutex);
1096*4882a593Smuzhiyun ret = i2c_smbus_read_i2c_block_data_or_emulated(data->client,
1097*4882a593Smuzhiyun KXCJK1013_REG_XOUT_L,
1098*4882a593Smuzhiyun AXIS_MAX * 2,
1099*4882a593Smuzhiyun (u8 *)data->scan.chans);
1100*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1101*4882a593Smuzhiyun if (ret < 0)
1102*4882a593Smuzhiyun goto err;
1103*4882a593Smuzhiyun
1104*4882a593Smuzhiyun iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
1105*4882a593Smuzhiyun data->timestamp);
1106*4882a593Smuzhiyun err:
1107*4882a593Smuzhiyun iio_trigger_notify_done(indio_dev->trig);
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun return IRQ_HANDLED;
1110*4882a593Smuzhiyun }
1111*4882a593Smuzhiyun
kxcjk1013_trig_try_reen(struct iio_trigger * trig)1112*4882a593Smuzhiyun static int kxcjk1013_trig_try_reen(struct iio_trigger *trig)
1113*4882a593Smuzhiyun {
1114*4882a593Smuzhiyun struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1115*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
1116*4882a593Smuzhiyun int ret;
1117*4882a593Smuzhiyun
1118*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_REL);
1119*4882a593Smuzhiyun if (ret < 0) {
1120*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading reg_int_rel\n");
1121*4882a593Smuzhiyun return ret;
1122*4882a593Smuzhiyun }
1123*4882a593Smuzhiyun
1124*4882a593Smuzhiyun return 0;
1125*4882a593Smuzhiyun }
1126*4882a593Smuzhiyun
kxcjk1013_data_rdy_trigger_set_state(struct iio_trigger * trig,bool state)1127*4882a593Smuzhiyun static int kxcjk1013_data_rdy_trigger_set_state(struct iio_trigger *trig,
1128*4882a593Smuzhiyun bool state)
1129*4882a593Smuzhiyun {
1130*4882a593Smuzhiyun struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1131*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
1132*4882a593Smuzhiyun int ret;
1133*4882a593Smuzhiyun
1134*4882a593Smuzhiyun mutex_lock(&data->mutex);
1135*4882a593Smuzhiyun
1136*4882a593Smuzhiyun if (!state && data->ev_enable_state && data->motion_trigger_on) {
1137*4882a593Smuzhiyun data->motion_trigger_on = false;
1138*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1139*4882a593Smuzhiyun return 0;
1140*4882a593Smuzhiyun }
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun ret = kxcjk1013_set_power_state(data, state);
1143*4882a593Smuzhiyun if (ret < 0) {
1144*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1145*4882a593Smuzhiyun return ret;
1146*4882a593Smuzhiyun }
1147*4882a593Smuzhiyun if (data->motion_trig == trig)
1148*4882a593Smuzhiyun ret = kxcjk1013_setup_any_motion_interrupt(data, state);
1149*4882a593Smuzhiyun else
1150*4882a593Smuzhiyun ret = kxcjk1013_setup_new_data_interrupt(data, state);
1151*4882a593Smuzhiyun if (ret < 0) {
1152*4882a593Smuzhiyun kxcjk1013_set_power_state(data, false);
1153*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1154*4882a593Smuzhiyun return ret;
1155*4882a593Smuzhiyun }
1156*4882a593Smuzhiyun if (data->motion_trig == trig)
1157*4882a593Smuzhiyun data->motion_trigger_on = state;
1158*4882a593Smuzhiyun else
1159*4882a593Smuzhiyun data->dready_trigger_on = state;
1160*4882a593Smuzhiyun
1161*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun return 0;
1164*4882a593Smuzhiyun }
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun static const struct iio_trigger_ops kxcjk1013_trigger_ops = {
1167*4882a593Smuzhiyun .set_trigger_state = kxcjk1013_data_rdy_trigger_set_state,
1168*4882a593Smuzhiyun .try_reenable = kxcjk1013_trig_try_reen,
1169*4882a593Smuzhiyun };
1170*4882a593Smuzhiyun
kxcjk1013_report_motion_event(struct iio_dev * indio_dev)1171*4882a593Smuzhiyun static void kxcjk1013_report_motion_event(struct iio_dev *indio_dev)
1172*4882a593Smuzhiyun {
1173*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
1174*4882a593Smuzhiyun
1175*4882a593Smuzhiyun int ret = i2c_smbus_read_byte_data(data->client,
1176*4882a593Smuzhiyun KXCJK1013_REG_INT_SRC2);
1177*4882a593Smuzhiyun if (ret < 0) {
1178*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading reg_int_src2\n");
1179*4882a593Smuzhiyun return;
1180*4882a593Smuzhiyun }
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun if (ret & KXCJK1013_REG_INT_SRC2_BIT_XN)
1183*4882a593Smuzhiyun iio_push_event(indio_dev,
1184*4882a593Smuzhiyun IIO_MOD_EVENT_CODE(IIO_ACCEL,
1185*4882a593Smuzhiyun 0,
1186*4882a593Smuzhiyun IIO_MOD_X,
1187*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
1188*4882a593Smuzhiyun IIO_EV_DIR_FALLING),
1189*4882a593Smuzhiyun data->timestamp);
1190*4882a593Smuzhiyun
1191*4882a593Smuzhiyun if (ret & KXCJK1013_REG_INT_SRC2_BIT_XP)
1192*4882a593Smuzhiyun iio_push_event(indio_dev,
1193*4882a593Smuzhiyun IIO_MOD_EVENT_CODE(IIO_ACCEL,
1194*4882a593Smuzhiyun 0,
1195*4882a593Smuzhiyun IIO_MOD_X,
1196*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
1197*4882a593Smuzhiyun IIO_EV_DIR_RISING),
1198*4882a593Smuzhiyun data->timestamp);
1199*4882a593Smuzhiyun
1200*4882a593Smuzhiyun if (ret & KXCJK1013_REG_INT_SRC2_BIT_YN)
1201*4882a593Smuzhiyun iio_push_event(indio_dev,
1202*4882a593Smuzhiyun IIO_MOD_EVENT_CODE(IIO_ACCEL,
1203*4882a593Smuzhiyun 0,
1204*4882a593Smuzhiyun IIO_MOD_Y,
1205*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
1206*4882a593Smuzhiyun IIO_EV_DIR_FALLING),
1207*4882a593Smuzhiyun data->timestamp);
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun if (ret & KXCJK1013_REG_INT_SRC2_BIT_YP)
1210*4882a593Smuzhiyun iio_push_event(indio_dev,
1211*4882a593Smuzhiyun IIO_MOD_EVENT_CODE(IIO_ACCEL,
1212*4882a593Smuzhiyun 0,
1213*4882a593Smuzhiyun IIO_MOD_Y,
1214*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
1215*4882a593Smuzhiyun IIO_EV_DIR_RISING),
1216*4882a593Smuzhiyun data->timestamp);
1217*4882a593Smuzhiyun
1218*4882a593Smuzhiyun if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZN)
1219*4882a593Smuzhiyun iio_push_event(indio_dev,
1220*4882a593Smuzhiyun IIO_MOD_EVENT_CODE(IIO_ACCEL,
1221*4882a593Smuzhiyun 0,
1222*4882a593Smuzhiyun IIO_MOD_Z,
1223*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
1224*4882a593Smuzhiyun IIO_EV_DIR_FALLING),
1225*4882a593Smuzhiyun data->timestamp);
1226*4882a593Smuzhiyun
1227*4882a593Smuzhiyun if (ret & KXCJK1013_REG_INT_SRC2_BIT_ZP)
1228*4882a593Smuzhiyun iio_push_event(indio_dev,
1229*4882a593Smuzhiyun IIO_MOD_EVENT_CODE(IIO_ACCEL,
1230*4882a593Smuzhiyun 0,
1231*4882a593Smuzhiyun IIO_MOD_Z,
1232*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
1233*4882a593Smuzhiyun IIO_EV_DIR_RISING),
1234*4882a593Smuzhiyun data->timestamp);
1235*4882a593Smuzhiyun }
1236*4882a593Smuzhiyun
kxcjk1013_event_handler(int irq,void * private)1237*4882a593Smuzhiyun static irqreturn_t kxcjk1013_event_handler(int irq, void *private)
1238*4882a593Smuzhiyun {
1239*4882a593Smuzhiyun struct iio_dev *indio_dev = private;
1240*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
1241*4882a593Smuzhiyun int ret;
1242*4882a593Smuzhiyun
1243*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_SRC1);
1244*4882a593Smuzhiyun if (ret < 0) {
1245*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading reg_int_src1\n");
1246*4882a593Smuzhiyun goto ack_intr;
1247*4882a593Smuzhiyun }
1248*4882a593Smuzhiyun
1249*4882a593Smuzhiyun if (ret & KXCJK1013_REG_INT_SRC1_BIT_WUFS) {
1250*4882a593Smuzhiyun if (data->chipset == KXTF9)
1251*4882a593Smuzhiyun iio_push_event(indio_dev,
1252*4882a593Smuzhiyun IIO_MOD_EVENT_CODE(IIO_ACCEL,
1253*4882a593Smuzhiyun 0,
1254*4882a593Smuzhiyun IIO_MOD_X_AND_Y_AND_Z,
1255*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
1256*4882a593Smuzhiyun IIO_EV_DIR_RISING),
1257*4882a593Smuzhiyun data->timestamp);
1258*4882a593Smuzhiyun else
1259*4882a593Smuzhiyun kxcjk1013_report_motion_event(indio_dev);
1260*4882a593Smuzhiyun }
1261*4882a593Smuzhiyun
1262*4882a593Smuzhiyun ack_intr:
1263*4882a593Smuzhiyun if (data->dready_trigger_on)
1264*4882a593Smuzhiyun return IRQ_HANDLED;
1265*4882a593Smuzhiyun
1266*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(data->client, KXCJK1013_REG_INT_REL);
1267*4882a593Smuzhiyun if (ret < 0)
1268*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading reg_int_rel\n");
1269*4882a593Smuzhiyun
1270*4882a593Smuzhiyun return IRQ_HANDLED;
1271*4882a593Smuzhiyun }
1272*4882a593Smuzhiyun
kxcjk1013_data_rdy_trig_poll(int irq,void * private)1273*4882a593Smuzhiyun static irqreturn_t kxcjk1013_data_rdy_trig_poll(int irq, void *private)
1274*4882a593Smuzhiyun {
1275*4882a593Smuzhiyun struct iio_dev *indio_dev = private;
1276*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
1277*4882a593Smuzhiyun
1278*4882a593Smuzhiyun data->timestamp = iio_get_time_ns(indio_dev);
1279*4882a593Smuzhiyun
1280*4882a593Smuzhiyun if (data->dready_trigger_on)
1281*4882a593Smuzhiyun iio_trigger_poll(data->dready_trig);
1282*4882a593Smuzhiyun else if (data->motion_trigger_on)
1283*4882a593Smuzhiyun iio_trigger_poll(data->motion_trig);
1284*4882a593Smuzhiyun
1285*4882a593Smuzhiyun if (data->ev_enable_state)
1286*4882a593Smuzhiyun return IRQ_WAKE_THREAD;
1287*4882a593Smuzhiyun else
1288*4882a593Smuzhiyun return IRQ_HANDLED;
1289*4882a593Smuzhiyun }
1290*4882a593Smuzhiyun
kxcjk1013_match_acpi_device(struct device * dev,enum kx_chipset * chipset,enum kx_acpi_type * acpi_type)1291*4882a593Smuzhiyun static const char *kxcjk1013_match_acpi_device(struct device *dev,
1292*4882a593Smuzhiyun enum kx_chipset *chipset,
1293*4882a593Smuzhiyun enum kx_acpi_type *acpi_type)
1294*4882a593Smuzhiyun {
1295*4882a593Smuzhiyun const struct acpi_device_id *id;
1296*4882a593Smuzhiyun
1297*4882a593Smuzhiyun id = acpi_match_device(dev->driver->acpi_match_table, dev);
1298*4882a593Smuzhiyun if (!id)
1299*4882a593Smuzhiyun return NULL;
1300*4882a593Smuzhiyun
1301*4882a593Smuzhiyun if (strcmp(id->id, "SMO8500") == 0)
1302*4882a593Smuzhiyun *acpi_type = ACPI_SMO8500;
1303*4882a593Smuzhiyun else if (strcmp(id->id, "KIOX010A") == 0)
1304*4882a593Smuzhiyun *acpi_type = ACPI_KIOX010A;
1305*4882a593Smuzhiyun
1306*4882a593Smuzhiyun *chipset = (enum kx_chipset)id->driver_data;
1307*4882a593Smuzhiyun
1308*4882a593Smuzhiyun return dev_name(dev);
1309*4882a593Smuzhiyun }
1310*4882a593Smuzhiyun
kxcjk1013_probe(struct i2c_client * client,const struct i2c_device_id * id)1311*4882a593Smuzhiyun static int kxcjk1013_probe(struct i2c_client *client,
1312*4882a593Smuzhiyun const struct i2c_device_id *id)
1313*4882a593Smuzhiyun {
1314*4882a593Smuzhiyun struct kxcjk1013_data *data;
1315*4882a593Smuzhiyun struct iio_dev *indio_dev;
1316*4882a593Smuzhiyun struct kxcjk_1013_platform_data *pdata;
1317*4882a593Smuzhiyun const char *name;
1318*4882a593Smuzhiyun int ret;
1319*4882a593Smuzhiyun
1320*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1321*4882a593Smuzhiyun if (!indio_dev)
1322*4882a593Smuzhiyun return -ENOMEM;
1323*4882a593Smuzhiyun
1324*4882a593Smuzhiyun data = iio_priv(indio_dev);
1325*4882a593Smuzhiyun i2c_set_clientdata(client, indio_dev);
1326*4882a593Smuzhiyun data->client = client;
1327*4882a593Smuzhiyun
1328*4882a593Smuzhiyun pdata = dev_get_platdata(&client->dev);
1329*4882a593Smuzhiyun if (pdata) {
1330*4882a593Smuzhiyun data->active_high_intr = pdata->active_high_intr;
1331*4882a593Smuzhiyun data->orientation = pdata->orientation;
1332*4882a593Smuzhiyun } else {
1333*4882a593Smuzhiyun data->active_high_intr = true; /* default polarity */
1334*4882a593Smuzhiyun
1335*4882a593Smuzhiyun ret = iio_read_mount_matrix(&client->dev, "mount-matrix",
1336*4882a593Smuzhiyun &data->orientation);
1337*4882a593Smuzhiyun if (ret)
1338*4882a593Smuzhiyun return ret;
1339*4882a593Smuzhiyun }
1340*4882a593Smuzhiyun
1341*4882a593Smuzhiyun if (id) {
1342*4882a593Smuzhiyun data->chipset = (enum kx_chipset)(id->driver_data);
1343*4882a593Smuzhiyun name = id->name;
1344*4882a593Smuzhiyun } else if (ACPI_HANDLE(&client->dev)) {
1345*4882a593Smuzhiyun name = kxcjk1013_match_acpi_device(&client->dev,
1346*4882a593Smuzhiyun &data->chipset,
1347*4882a593Smuzhiyun &data->acpi_type);
1348*4882a593Smuzhiyun } else
1349*4882a593Smuzhiyun return -ENODEV;
1350*4882a593Smuzhiyun
1351*4882a593Smuzhiyun ret = kxcjk1013_chip_init(data);
1352*4882a593Smuzhiyun if (ret < 0)
1353*4882a593Smuzhiyun return ret;
1354*4882a593Smuzhiyun
1355*4882a593Smuzhiyun mutex_init(&data->mutex);
1356*4882a593Smuzhiyun
1357*4882a593Smuzhiyun indio_dev->channels = kxcjk1013_channels;
1358*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(kxcjk1013_channels);
1359*4882a593Smuzhiyun indio_dev->available_scan_masks = kxcjk1013_scan_masks;
1360*4882a593Smuzhiyun indio_dev->name = name;
1361*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
1362*4882a593Smuzhiyun indio_dev->info = &kxcjk1013_info;
1363*4882a593Smuzhiyun
1364*4882a593Smuzhiyun if (client->irq > 0 && data->acpi_type != ACPI_SMO8500) {
1365*4882a593Smuzhiyun ret = devm_request_threaded_irq(&client->dev, client->irq,
1366*4882a593Smuzhiyun kxcjk1013_data_rdy_trig_poll,
1367*4882a593Smuzhiyun kxcjk1013_event_handler,
1368*4882a593Smuzhiyun IRQF_TRIGGER_RISING,
1369*4882a593Smuzhiyun KXCJK1013_IRQ_NAME,
1370*4882a593Smuzhiyun indio_dev);
1371*4882a593Smuzhiyun if (ret)
1372*4882a593Smuzhiyun goto err_poweroff;
1373*4882a593Smuzhiyun
1374*4882a593Smuzhiyun data->dready_trig = devm_iio_trigger_alloc(&client->dev,
1375*4882a593Smuzhiyun "%s-dev%d",
1376*4882a593Smuzhiyun indio_dev->name,
1377*4882a593Smuzhiyun indio_dev->id);
1378*4882a593Smuzhiyun if (!data->dready_trig) {
1379*4882a593Smuzhiyun ret = -ENOMEM;
1380*4882a593Smuzhiyun goto err_poweroff;
1381*4882a593Smuzhiyun }
1382*4882a593Smuzhiyun
1383*4882a593Smuzhiyun data->motion_trig = devm_iio_trigger_alloc(&client->dev,
1384*4882a593Smuzhiyun "%s-any-motion-dev%d",
1385*4882a593Smuzhiyun indio_dev->name,
1386*4882a593Smuzhiyun indio_dev->id);
1387*4882a593Smuzhiyun if (!data->motion_trig) {
1388*4882a593Smuzhiyun ret = -ENOMEM;
1389*4882a593Smuzhiyun goto err_poweroff;
1390*4882a593Smuzhiyun }
1391*4882a593Smuzhiyun
1392*4882a593Smuzhiyun data->dready_trig->dev.parent = &client->dev;
1393*4882a593Smuzhiyun data->dready_trig->ops = &kxcjk1013_trigger_ops;
1394*4882a593Smuzhiyun iio_trigger_set_drvdata(data->dready_trig, indio_dev);
1395*4882a593Smuzhiyun indio_dev->trig = data->dready_trig;
1396*4882a593Smuzhiyun iio_trigger_get(indio_dev->trig);
1397*4882a593Smuzhiyun ret = iio_trigger_register(data->dready_trig);
1398*4882a593Smuzhiyun if (ret)
1399*4882a593Smuzhiyun goto err_poweroff;
1400*4882a593Smuzhiyun
1401*4882a593Smuzhiyun data->motion_trig->dev.parent = &client->dev;
1402*4882a593Smuzhiyun data->motion_trig->ops = &kxcjk1013_trigger_ops;
1403*4882a593Smuzhiyun iio_trigger_set_drvdata(data->motion_trig, indio_dev);
1404*4882a593Smuzhiyun ret = iio_trigger_register(data->motion_trig);
1405*4882a593Smuzhiyun if (ret) {
1406*4882a593Smuzhiyun data->motion_trig = NULL;
1407*4882a593Smuzhiyun goto err_trigger_unregister;
1408*4882a593Smuzhiyun }
1409*4882a593Smuzhiyun }
1410*4882a593Smuzhiyun
1411*4882a593Smuzhiyun ret = iio_triggered_buffer_setup(indio_dev,
1412*4882a593Smuzhiyun &iio_pollfunc_store_time,
1413*4882a593Smuzhiyun kxcjk1013_trigger_handler,
1414*4882a593Smuzhiyun &kxcjk1013_buffer_setup_ops);
1415*4882a593Smuzhiyun if (ret < 0) {
1416*4882a593Smuzhiyun dev_err(&client->dev, "iio triggered buffer setup failed\n");
1417*4882a593Smuzhiyun goto err_trigger_unregister;
1418*4882a593Smuzhiyun }
1419*4882a593Smuzhiyun
1420*4882a593Smuzhiyun ret = pm_runtime_set_active(&client->dev);
1421*4882a593Smuzhiyun if (ret)
1422*4882a593Smuzhiyun goto err_buffer_cleanup;
1423*4882a593Smuzhiyun
1424*4882a593Smuzhiyun pm_runtime_enable(&client->dev);
1425*4882a593Smuzhiyun pm_runtime_set_autosuspend_delay(&client->dev,
1426*4882a593Smuzhiyun KXCJK1013_SLEEP_DELAY_MS);
1427*4882a593Smuzhiyun pm_runtime_use_autosuspend(&client->dev);
1428*4882a593Smuzhiyun
1429*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
1430*4882a593Smuzhiyun if (ret < 0) {
1431*4882a593Smuzhiyun dev_err(&client->dev, "unable to register iio device\n");
1432*4882a593Smuzhiyun goto err_pm_cleanup;
1433*4882a593Smuzhiyun }
1434*4882a593Smuzhiyun
1435*4882a593Smuzhiyun return 0;
1436*4882a593Smuzhiyun
1437*4882a593Smuzhiyun err_pm_cleanup:
1438*4882a593Smuzhiyun pm_runtime_dont_use_autosuspend(&client->dev);
1439*4882a593Smuzhiyun pm_runtime_disable(&client->dev);
1440*4882a593Smuzhiyun err_buffer_cleanup:
1441*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
1442*4882a593Smuzhiyun err_trigger_unregister:
1443*4882a593Smuzhiyun if (data->dready_trig)
1444*4882a593Smuzhiyun iio_trigger_unregister(data->dready_trig);
1445*4882a593Smuzhiyun if (data->motion_trig)
1446*4882a593Smuzhiyun iio_trigger_unregister(data->motion_trig);
1447*4882a593Smuzhiyun err_poweroff:
1448*4882a593Smuzhiyun kxcjk1013_set_mode(data, STANDBY);
1449*4882a593Smuzhiyun
1450*4882a593Smuzhiyun return ret;
1451*4882a593Smuzhiyun }
1452*4882a593Smuzhiyun
kxcjk1013_remove(struct i2c_client * client)1453*4882a593Smuzhiyun static int kxcjk1013_remove(struct i2c_client *client)
1454*4882a593Smuzhiyun {
1455*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(client);
1456*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
1457*4882a593Smuzhiyun
1458*4882a593Smuzhiyun iio_device_unregister(indio_dev);
1459*4882a593Smuzhiyun
1460*4882a593Smuzhiyun pm_runtime_disable(&client->dev);
1461*4882a593Smuzhiyun pm_runtime_set_suspended(&client->dev);
1462*4882a593Smuzhiyun pm_runtime_put_noidle(&client->dev);
1463*4882a593Smuzhiyun
1464*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
1465*4882a593Smuzhiyun if (data->dready_trig) {
1466*4882a593Smuzhiyun iio_trigger_unregister(data->dready_trig);
1467*4882a593Smuzhiyun iio_trigger_unregister(data->motion_trig);
1468*4882a593Smuzhiyun }
1469*4882a593Smuzhiyun
1470*4882a593Smuzhiyun mutex_lock(&data->mutex);
1471*4882a593Smuzhiyun kxcjk1013_set_mode(data, STANDBY);
1472*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1473*4882a593Smuzhiyun
1474*4882a593Smuzhiyun return 0;
1475*4882a593Smuzhiyun }
1476*4882a593Smuzhiyun
1477*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
kxcjk1013_suspend(struct device * dev)1478*4882a593Smuzhiyun static int kxcjk1013_suspend(struct device *dev)
1479*4882a593Smuzhiyun {
1480*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1481*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
1482*4882a593Smuzhiyun int ret;
1483*4882a593Smuzhiyun
1484*4882a593Smuzhiyun mutex_lock(&data->mutex);
1485*4882a593Smuzhiyun ret = kxcjk1013_set_mode(data, STANDBY);
1486*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1487*4882a593Smuzhiyun
1488*4882a593Smuzhiyun return ret;
1489*4882a593Smuzhiyun }
1490*4882a593Smuzhiyun
kxcjk1013_resume(struct device * dev)1491*4882a593Smuzhiyun static int kxcjk1013_resume(struct device *dev)
1492*4882a593Smuzhiyun {
1493*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1494*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
1495*4882a593Smuzhiyun int ret = 0;
1496*4882a593Smuzhiyun
1497*4882a593Smuzhiyun mutex_lock(&data->mutex);
1498*4882a593Smuzhiyun ret = kxcjk1013_set_mode(data, OPERATION);
1499*4882a593Smuzhiyun if (ret == 0)
1500*4882a593Smuzhiyun ret = kxcjk1013_set_range(data, data->range);
1501*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1502*4882a593Smuzhiyun
1503*4882a593Smuzhiyun return ret;
1504*4882a593Smuzhiyun }
1505*4882a593Smuzhiyun #endif
1506*4882a593Smuzhiyun
1507*4882a593Smuzhiyun #ifdef CONFIG_PM
kxcjk1013_runtime_suspend(struct device * dev)1508*4882a593Smuzhiyun static int kxcjk1013_runtime_suspend(struct device *dev)
1509*4882a593Smuzhiyun {
1510*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1511*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
1512*4882a593Smuzhiyun int ret;
1513*4882a593Smuzhiyun
1514*4882a593Smuzhiyun ret = kxcjk1013_set_mode(data, STANDBY);
1515*4882a593Smuzhiyun if (ret < 0) {
1516*4882a593Smuzhiyun dev_err(&data->client->dev, "powering off device failed\n");
1517*4882a593Smuzhiyun return -EAGAIN;
1518*4882a593Smuzhiyun }
1519*4882a593Smuzhiyun return 0;
1520*4882a593Smuzhiyun }
1521*4882a593Smuzhiyun
kxcjk1013_runtime_resume(struct device * dev)1522*4882a593Smuzhiyun static int kxcjk1013_runtime_resume(struct device *dev)
1523*4882a593Smuzhiyun {
1524*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1525*4882a593Smuzhiyun struct kxcjk1013_data *data = iio_priv(indio_dev);
1526*4882a593Smuzhiyun int ret;
1527*4882a593Smuzhiyun int sleep_val;
1528*4882a593Smuzhiyun
1529*4882a593Smuzhiyun ret = kxcjk1013_set_mode(data, OPERATION);
1530*4882a593Smuzhiyun if (ret < 0)
1531*4882a593Smuzhiyun return ret;
1532*4882a593Smuzhiyun
1533*4882a593Smuzhiyun sleep_val = kxcjk1013_get_startup_times(data);
1534*4882a593Smuzhiyun if (sleep_val < 20000)
1535*4882a593Smuzhiyun usleep_range(sleep_val, 20000);
1536*4882a593Smuzhiyun else
1537*4882a593Smuzhiyun msleep_interruptible(sleep_val/1000);
1538*4882a593Smuzhiyun
1539*4882a593Smuzhiyun return 0;
1540*4882a593Smuzhiyun }
1541*4882a593Smuzhiyun #endif
1542*4882a593Smuzhiyun
1543*4882a593Smuzhiyun static const struct dev_pm_ops kxcjk1013_pm_ops = {
1544*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(kxcjk1013_suspend, kxcjk1013_resume)
1545*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(kxcjk1013_runtime_suspend,
1546*4882a593Smuzhiyun kxcjk1013_runtime_resume, NULL)
1547*4882a593Smuzhiyun };
1548*4882a593Smuzhiyun
1549*4882a593Smuzhiyun static const struct acpi_device_id kx_acpi_match[] = {
1550*4882a593Smuzhiyun {"KXCJ1013", KXCJK1013},
1551*4882a593Smuzhiyun {"KXCJ1008", KXCJ91008},
1552*4882a593Smuzhiyun {"KXCJ9000", KXCJ91008},
1553*4882a593Smuzhiyun {"KIOX0008", KXCJ91008},
1554*4882a593Smuzhiyun {"KIOX0009", KXTJ21009},
1555*4882a593Smuzhiyun {"KIOX000A", KXCJ91008},
1556*4882a593Smuzhiyun {"KIOX010A", KXCJ91008}, /* KXCJ91008 in the display of a yoga 2-in-1 */
1557*4882a593Smuzhiyun {"KIOX020A", KXCJ91008}, /* KXCJ91008 in the base of a yoga 2-in-1 */
1558*4882a593Smuzhiyun {"KXTJ1009", KXTJ21009},
1559*4882a593Smuzhiyun {"KXJ2109", KXTJ21009},
1560*4882a593Smuzhiyun {"SMO8500", KXCJ91008},
1561*4882a593Smuzhiyun { },
1562*4882a593Smuzhiyun };
1563*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, kx_acpi_match);
1564*4882a593Smuzhiyun
1565*4882a593Smuzhiyun static const struct i2c_device_id kxcjk1013_id[] = {
1566*4882a593Smuzhiyun {"kxcjk1013", KXCJK1013},
1567*4882a593Smuzhiyun {"kxcj91008", KXCJ91008},
1568*4882a593Smuzhiyun {"kxtj21009", KXTJ21009},
1569*4882a593Smuzhiyun {"kxtf9", KXTF9},
1570*4882a593Smuzhiyun {"SMO8500", KXCJ91008},
1571*4882a593Smuzhiyun {}
1572*4882a593Smuzhiyun };
1573*4882a593Smuzhiyun
1574*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, kxcjk1013_id);
1575*4882a593Smuzhiyun
1576*4882a593Smuzhiyun static const struct of_device_id kxcjk1013_of_match[] = {
1577*4882a593Smuzhiyun { .compatible = "kionix,kxcjk1013", },
1578*4882a593Smuzhiyun { .compatible = "kionix,kxcj91008", },
1579*4882a593Smuzhiyun { .compatible = "kionix,kxtj21009", },
1580*4882a593Smuzhiyun { .compatible = "kionix,kxtf9", },
1581*4882a593Smuzhiyun { }
1582*4882a593Smuzhiyun };
1583*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, kxcjk1013_of_match);
1584*4882a593Smuzhiyun
1585*4882a593Smuzhiyun static struct i2c_driver kxcjk1013_driver = {
1586*4882a593Smuzhiyun .driver = {
1587*4882a593Smuzhiyun .name = KXCJK1013_DRV_NAME,
1588*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(kx_acpi_match),
1589*4882a593Smuzhiyun .of_match_table = kxcjk1013_of_match,
1590*4882a593Smuzhiyun .pm = &kxcjk1013_pm_ops,
1591*4882a593Smuzhiyun },
1592*4882a593Smuzhiyun .probe = kxcjk1013_probe,
1593*4882a593Smuzhiyun .remove = kxcjk1013_remove,
1594*4882a593Smuzhiyun .id_table = kxcjk1013_id,
1595*4882a593Smuzhiyun };
1596*4882a593Smuzhiyun module_i2c_driver(kxcjk1013_driver);
1597*4882a593Smuzhiyun
1598*4882a593Smuzhiyun MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1599*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1600*4882a593Smuzhiyun MODULE_DESCRIPTION("KXCJK1013 accelerometer driver");
1601