xref: /OK3568_Linux_fs/kernel/drivers/iio/accel/dmard10.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /**
3*4882a593Smuzhiyun  * IIO driver for the 3-axis accelerometer Domintech ARD10.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2016 Hans de Goede <hdegoede@redhat.com>
6*4882a593Smuzhiyun  * Copyright (c) 2012 Domintech Technology Co., Ltd
7*4882a593Smuzhiyun  */
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/i2c.h>
11*4882a593Smuzhiyun #include <linux/iio/iio.h>
12*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
13*4882a593Smuzhiyun #include <linux/byteorder/generic.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define DMARD10_REG_ACTR			0x00
16*4882a593Smuzhiyun #define DMARD10_REG_AFEM			0x0c
17*4882a593Smuzhiyun #define DMARD10_REG_STADR			0x12
18*4882a593Smuzhiyun #define DMARD10_REG_STAINT			0x1c
19*4882a593Smuzhiyun #define DMARD10_REG_MISC2			0x1f
20*4882a593Smuzhiyun #define DMARD10_REG_PD				0x21
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define DMARD10_MODE_OFF			0x00
23*4882a593Smuzhiyun #define DMARD10_MODE_STANDBY			0x02
24*4882a593Smuzhiyun #define DMARD10_MODE_ACTIVE			0x06
25*4882a593Smuzhiyun #define DMARD10_MODE_READ_OTP			0x12
26*4882a593Smuzhiyun #define DMARD10_MODE_RESET_DATA_PATH		0x82
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /* AFEN set 1, ATM[2:0]=b'000 (normal), EN_Z/Y/X/T=1 */
29*4882a593Smuzhiyun #define DMARD10_VALUE_AFEM_AFEN_NORMAL		0x8f
30*4882a593Smuzhiyun /* ODR[3:0]=b'0111 (100Hz), CCK[3:0]=b'0100 (204.8kHZ) */
31*4882a593Smuzhiyun #define DMARD10_VALUE_CKSEL_ODR_100_204		0x74
32*4882a593Smuzhiyun /* INTC[6:5]=b'00 */
33*4882a593Smuzhiyun #define DMARD10_VALUE_INTC			0x00
34*4882a593Smuzhiyun /* TAP1/TAP2 Average 2 */
35*4882a593Smuzhiyun #define DMARD10_VALUE_TAPNS_AVE_2		0x11
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun #define DMARD10_VALUE_STADR			0x55
38*4882a593Smuzhiyun #define DMARD10_VALUE_STAINT			0xaa
39*4882a593Smuzhiyun #define DMARD10_VALUE_MISC2_OSCA_EN		0x08
40*4882a593Smuzhiyun #define DMARD10_VALUE_PD_RST			0x52
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun /* Offsets into the buffer read in dmard10_read_raw() */
43*4882a593Smuzhiyun #define DMARD10_X_OFFSET			1
44*4882a593Smuzhiyun #define DMARD10_Y_OFFSET			2
45*4882a593Smuzhiyun #define DMARD10_Z_OFFSET			3
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /*
48*4882a593Smuzhiyun  * a value of + or -128 corresponds to + or - 1G
49*4882a593Smuzhiyun  * scale = 9.81 / 128 = 0.076640625
50*4882a593Smuzhiyun  */
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun static const int dmard10_nscale = 76640625;
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #define DMARD10_CHANNEL(reg, axis) {	\
55*4882a593Smuzhiyun 	.type = IIO_ACCEL,	\
56*4882a593Smuzhiyun 	.address = reg,	\
57*4882a593Smuzhiyun 	.modified = 1,	\
58*4882a593Smuzhiyun 	.channel2 = IIO_MOD_##axis,	\
59*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	\
60*4882a593Smuzhiyun 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun static const struct iio_chan_spec dmard10_channels[] = {
64*4882a593Smuzhiyun 	DMARD10_CHANNEL(DMARD10_X_OFFSET, X),
65*4882a593Smuzhiyun 	DMARD10_CHANNEL(DMARD10_Y_OFFSET, Y),
66*4882a593Smuzhiyun 	DMARD10_CHANNEL(DMARD10_Z_OFFSET, Z),
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun struct dmard10_data {
70*4882a593Smuzhiyun 	struct i2c_client *client;
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun /* Init sequence taken from the android driver */
dmard10_reset(struct i2c_client * client)74*4882a593Smuzhiyun static int dmard10_reset(struct i2c_client *client)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	unsigned char buffer[7];
77*4882a593Smuzhiyun 	int ret;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	/* 1. Powerdown reset */
80*4882a593Smuzhiyun 	ret = i2c_smbus_write_byte_data(client, DMARD10_REG_PD,
81*4882a593Smuzhiyun 						DMARD10_VALUE_PD_RST);
82*4882a593Smuzhiyun 	if (ret < 0)
83*4882a593Smuzhiyun 		return ret;
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	/*
86*4882a593Smuzhiyun 	 * 2. ACTR => Standby mode => Download OTP to parameter reg =>
87*4882a593Smuzhiyun 	 *    Standby mode => Reset data path => Standby mode
88*4882a593Smuzhiyun 	 */
89*4882a593Smuzhiyun 	buffer[0] = DMARD10_REG_ACTR;
90*4882a593Smuzhiyun 	buffer[1] = DMARD10_MODE_STANDBY;
91*4882a593Smuzhiyun 	buffer[2] = DMARD10_MODE_READ_OTP;
92*4882a593Smuzhiyun 	buffer[3] = DMARD10_MODE_STANDBY;
93*4882a593Smuzhiyun 	buffer[4] = DMARD10_MODE_RESET_DATA_PATH;
94*4882a593Smuzhiyun 	buffer[5] = DMARD10_MODE_STANDBY;
95*4882a593Smuzhiyun 	ret = i2c_master_send(client, buffer, 6);
96*4882a593Smuzhiyun 	if (ret < 0)
97*4882a593Smuzhiyun 		return ret;
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	/* 3. OSCA_EN = 1, TSTO = b'000 (INT1 = normal, TEST0 = normal) */
100*4882a593Smuzhiyun 	ret = i2c_smbus_write_byte_data(client, DMARD10_REG_MISC2,
101*4882a593Smuzhiyun 						DMARD10_VALUE_MISC2_OSCA_EN);
102*4882a593Smuzhiyun 	if (ret < 0)
103*4882a593Smuzhiyun 		return ret;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	/* 4. AFEN = 1 (AFE will powerdown after ADC) */
106*4882a593Smuzhiyun 	buffer[0] = DMARD10_REG_AFEM;
107*4882a593Smuzhiyun 	buffer[1] = DMARD10_VALUE_AFEM_AFEN_NORMAL;
108*4882a593Smuzhiyun 	buffer[2] = DMARD10_VALUE_CKSEL_ODR_100_204;
109*4882a593Smuzhiyun 	buffer[3] = DMARD10_VALUE_INTC;
110*4882a593Smuzhiyun 	buffer[4] = DMARD10_VALUE_TAPNS_AVE_2;
111*4882a593Smuzhiyun 	buffer[5] = 0x00; /* DLYC, no delay timing */
112*4882a593Smuzhiyun 	buffer[6] = 0x07; /* INTD=1 push-pull, INTA=1 active high, AUTOT=1 */
113*4882a593Smuzhiyun 	ret = i2c_master_send(client, buffer, 7);
114*4882a593Smuzhiyun 	if (ret < 0)
115*4882a593Smuzhiyun 		return ret;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	/* 5. Activation mode */
118*4882a593Smuzhiyun 	ret = i2c_smbus_write_byte_data(client, DMARD10_REG_ACTR,
119*4882a593Smuzhiyun 						DMARD10_MODE_ACTIVE);
120*4882a593Smuzhiyun 	if (ret < 0)
121*4882a593Smuzhiyun 		return ret;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	return 0;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /* Shutdown sequence taken from the android driver */
dmard10_shutdown(struct i2c_client * client)127*4882a593Smuzhiyun static int dmard10_shutdown(struct i2c_client *client)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun 	unsigned char buffer[3];
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	buffer[0] = DMARD10_REG_ACTR;
132*4882a593Smuzhiyun 	buffer[1] = DMARD10_MODE_STANDBY;
133*4882a593Smuzhiyun 	buffer[2] = DMARD10_MODE_OFF;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	return i2c_master_send(client, buffer, 3);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun 
dmard10_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)138*4882a593Smuzhiyun static int dmard10_read_raw(struct iio_dev *indio_dev,
139*4882a593Smuzhiyun 				struct iio_chan_spec const *chan,
140*4882a593Smuzhiyun 				int *val, int *val2, long mask)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun 	struct dmard10_data *data = iio_priv(indio_dev);
143*4882a593Smuzhiyun 	__le16 buf[4];
144*4882a593Smuzhiyun 	int ret;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	switch (mask) {
147*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
148*4882a593Smuzhiyun 		/*
149*4882a593Smuzhiyun 		 * Read 8 bytes starting at the REG_STADR register, trying to
150*4882a593Smuzhiyun 		 * read the individual X, Y, Z registers will always read 0.
151*4882a593Smuzhiyun 		 */
152*4882a593Smuzhiyun 		ret = i2c_smbus_read_i2c_block_data(data->client,
153*4882a593Smuzhiyun 						    DMARD10_REG_STADR,
154*4882a593Smuzhiyun 						    sizeof(buf), (u8 *)buf);
155*4882a593Smuzhiyun 		if (ret < 0)
156*4882a593Smuzhiyun 			return ret;
157*4882a593Smuzhiyun 		ret = le16_to_cpu(buf[chan->address]);
158*4882a593Smuzhiyun 		*val = sign_extend32(ret, 12);
159*4882a593Smuzhiyun 		return IIO_VAL_INT;
160*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
161*4882a593Smuzhiyun 		*val = 0;
162*4882a593Smuzhiyun 		*val2 = dmard10_nscale;
163*4882a593Smuzhiyun 		return IIO_VAL_INT_PLUS_NANO;
164*4882a593Smuzhiyun 	default:
165*4882a593Smuzhiyun 		return -EINVAL;
166*4882a593Smuzhiyun 	}
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun static const struct iio_info dmard10_info = {
170*4882a593Smuzhiyun 	.read_raw	= dmard10_read_raw,
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun 
dmard10_probe(struct i2c_client * client,const struct i2c_device_id * id)173*4882a593Smuzhiyun static int dmard10_probe(struct i2c_client *client,
174*4882a593Smuzhiyun 			const struct i2c_device_id *id)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	int ret;
177*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
178*4882a593Smuzhiyun 	struct dmard10_data *data;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	/* These 2 registers have special POR reset values used for id */
181*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(client, DMARD10_REG_STADR);
182*4882a593Smuzhiyun 	if (ret != DMARD10_VALUE_STADR)
183*4882a593Smuzhiyun 		return (ret < 0) ? ret : -ENODEV;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(client, DMARD10_REG_STAINT);
186*4882a593Smuzhiyun 	if (ret != DMARD10_VALUE_STAINT)
187*4882a593Smuzhiyun 		return (ret < 0) ? ret : -ENODEV;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
190*4882a593Smuzhiyun 	if (!indio_dev) {
191*4882a593Smuzhiyun 		dev_err(&client->dev, "iio allocation failed!\n");
192*4882a593Smuzhiyun 		return -ENOMEM;
193*4882a593Smuzhiyun 	}
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	data = iio_priv(indio_dev);
196*4882a593Smuzhiyun 	data->client = client;
197*4882a593Smuzhiyun 	i2c_set_clientdata(client, indio_dev);
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	indio_dev->info = &dmard10_info;
200*4882a593Smuzhiyun 	indio_dev->name = "dmard10";
201*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
202*4882a593Smuzhiyun 	indio_dev->channels = dmard10_channels;
203*4882a593Smuzhiyun 	indio_dev->num_channels = ARRAY_SIZE(dmard10_channels);
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun 	ret = dmard10_reset(client);
206*4882a593Smuzhiyun 	if (ret < 0)
207*4882a593Smuzhiyun 		return ret;
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	ret = iio_device_register(indio_dev);
210*4882a593Smuzhiyun 	if (ret < 0) {
211*4882a593Smuzhiyun 		dev_err(&client->dev, "device_register failed\n");
212*4882a593Smuzhiyun 		dmard10_shutdown(client);
213*4882a593Smuzhiyun 	}
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	return ret;
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun 
dmard10_remove(struct i2c_client * client)218*4882a593Smuzhiyun static int dmard10_remove(struct i2c_client *client)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	iio_device_unregister(indio_dev);
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	return dmard10_shutdown(client);
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
dmard10_suspend(struct device * dev)228*4882a593Smuzhiyun static int dmard10_suspend(struct device *dev)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun 	return dmard10_shutdown(to_i2c_client(dev));
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun 
dmard10_resume(struct device * dev)233*4882a593Smuzhiyun static int dmard10_resume(struct device *dev)
234*4882a593Smuzhiyun {
235*4882a593Smuzhiyun 	return dmard10_reset(to_i2c_client(dev));
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun #endif
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(dmard10_pm_ops, dmard10_suspend, dmard10_resume);
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun static const struct i2c_device_id dmard10_i2c_id[] = {
242*4882a593Smuzhiyun 	{"dmard10", 0},
243*4882a593Smuzhiyun 	{}
244*4882a593Smuzhiyun };
245*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, dmard10_i2c_id);
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun static struct i2c_driver dmard10_driver = {
248*4882a593Smuzhiyun 	.driver = {
249*4882a593Smuzhiyun 		.name = "dmard10",
250*4882a593Smuzhiyun 		.pm = &dmard10_pm_ops,
251*4882a593Smuzhiyun 	},
252*4882a593Smuzhiyun 	.probe		= dmard10_probe,
253*4882a593Smuzhiyun 	.remove		= dmard10_remove,
254*4882a593Smuzhiyun 	.id_table	= dmard10_i2c_id,
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun module_i2c_driver(dmard10_driver);
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
260*4882a593Smuzhiyun MODULE_DESCRIPTION("Domintech ARD10 3-Axis Accelerometer driver");
261*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
262