xref: /OK3568_Linux_fs/kernel/drivers/iio/accel/dmard09.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * IIO driver for the 3-axis accelerometer Domintech DMARD09.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2016, Jelle van der Waa <jelle@vdwaa.nl>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <asm/unaligned.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/i2c.h>
11*4882a593Smuzhiyun #include <linux/iio/iio.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define DMARD09_DRV_NAME	"dmard09"
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define DMARD09_REG_CHIPID      0x18
16*4882a593Smuzhiyun #define DMARD09_REG_STAT	0x0A
17*4882a593Smuzhiyun #define DMARD09_REG_X		0x0C
18*4882a593Smuzhiyun #define DMARD09_REG_Y		0x0E
19*4882a593Smuzhiyun #define DMARD09_REG_Z		0x10
20*4882a593Smuzhiyun #define DMARD09_CHIPID		0x95
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define DMARD09_BUF_LEN 8
23*4882a593Smuzhiyun #define DMARD09_AXIS_X 0
24*4882a593Smuzhiyun #define DMARD09_AXIS_Y 1
25*4882a593Smuzhiyun #define DMARD09_AXIS_Z 2
26*4882a593Smuzhiyun #define DMARD09_AXIS_X_OFFSET ((DMARD09_AXIS_X + 1) * 2)
27*4882a593Smuzhiyun #define DMARD09_AXIS_Y_OFFSET ((DMARD09_AXIS_Y + 1 )* 2)
28*4882a593Smuzhiyun #define DMARD09_AXIS_Z_OFFSET ((DMARD09_AXIS_Z + 1) * 2)
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun struct dmard09_data {
31*4882a593Smuzhiyun 	struct i2c_client *client;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define DMARD09_CHANNEL(_axis, offset) {			\
35*4882a593Smuzhiyun 	.type = IIO_ACCEL,					\
36*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
37*4882a593Smuzhiyun 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
38*4882a593Smuzhiyun 	.modified = 1,						\
39*4882a593Smuzhiyun 	.address = offset,					\
40*4882a593Smuzhiyun 	.channel2 = IIO_MOD_##_axis,				\
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun static const struct iio_chan_spec dmard09_channels[] = {
44*4882a593Smuzhiyun 	DMARD09_CHANNEL(X, DMARD09_AXIS_X_OFFSET),
45*4882a593Smuzhiyun 	DMARD09_CHANNEL(Y, DMARD09_AXIS_Y_OFFSET),
46*4882a593Smuzhiyun 	DMARD09_CHANNEL(Z, DMARD09_AXIS_Z_OFFSET),
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun 
dmard09_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)49*4882a593Smuzhiyun static int dmard09_read_raw(struct iio_dev *indio_dev,
50*4882a593Smuzhiyun 			    struct iio_chan_spec const *chan,
51*4882a593Smuzhiyun 			    int *val, int *val2, long mask)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun 	struct dmard09_data *data = iio_priv(indio_dev);
54*4882a593Smuzhiyun 	u8 buf[DMARD09_BUF_LEN];
55*4882a593Smuzhiyun 	int ret;
56*4882a593Smuzhiyun 	s16 accel;
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	switch (mask) {
59*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
60*4882a593Smuzhiyun 		/*
61*4882a593Smuzhiyun 		 * Read from the DMAR09_REG_STAT register, since the chip
62*4882a593Smuzhiyun 		 * caches reads from the individual X, Y, Z registers.
63*4882a593Smuzhiyun 		 */
64*4882a593Smuzhiyun 		ret = i2c_smbus_read_i2c_block_data(data->client,
65*4882a593Smuzhiyun 						    DMARD09_REG_STAT,
66*4882a593Smuzhiyun 						    DMARD09_BUF_LEN, buf);
67*4882a593Smuzhiyun 		if (ret < 0) {
68*4882a593Smuzhiyun 			dev_err(&data->client->dev, "Error reading reg %d\n",
69*4882a593Smuzhiyun 				DMARD09_REG_STAT);
70*4882a593Smuzhiyun 			return ret;
71*4882a593Smuzhiyun 		}
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 		accel = get_unaligned_le16(&buf[chan->address]);
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 		/* Remove lower 3 bits and sign extend */
76*4882a593Smuzhiyun 		accel <<= 4;
77*4882a593Smuzhiyun 		accel >>= 7;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 		*val = accel;
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun 		return IIO_VAL_INT;
82*4882a593Smuzhiyun 	default:
83*4882a593Smuzhiyun 		return -EINVAL;
84*4882a593Smuzhiyun 	}
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun static const struct iio_info dmard09_info = {
88*4882a593Smuzhiyun 	.read_raw	= dmard09_read_raw,
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun 
dmard09_probe(struct i2c_client * client,const struct i2c_device_id * id)91*4882a593Smuzhiyun static int dmard09_probe(struct i2c_client *client,
92*4882a593Smuzhiyun 			const struct i2c_device_id *id)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun 	int ret;
95*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
96*4882a593Smuzhiyun 	struct dmard09_data *data;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
99*4882a593Smuzhiyun 	if (!indio_dev) {
100*4882a593Smuzhiyun 		dev_err(&client->dev, "iio allocation failed\n");
101*4882a593Smuzhiyun 		return -ENOMEM;
102*4882a593Smuzhiyun 	}
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	data = iio_priv(indio_dev);
105*4882a593Smuzhiyun 	data->client = client;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(data->client, DMARD09_REG_CHIPID);
108*4882a593Smuzhiyun 	if (ret < 0) {
109*4882a593Smuzhiyun 		dev_err(&client->dev, "Error reading chip id %d\n", ret);
110*4882a593Smuzhiyun 		return ret;
111*4882a593Smuzhiyun 	}
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	if (ret != DMARD09_CHIPID) {
114*4882a593Smuzhiyun 		dev_err(&client->dev, "Invalid chip id %d\n", ret);
115*4882a593Smuzhiyun 		return -ENODEV;
116*4882a593Smuzhiyun 	}
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	i2c_set_clientdata(client, indio_dev);
119*4882a593Smuzhiyun 	indio_dev->name = DMARD09_DRV_NAME;
120*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
121*4882a593Smuzhiyun 	indio_dev->channels = dmard09_channels;
122*4882a593Smuzhiyun 	indio_dev->num_channels = ARRAY_SIZE(dmard09_channels);
123*4882a593Smuzhiyun 	indio_dev->info = &dmard09_info;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	return devm_iio_device_register(&client->dev, indio_dev);
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun static const struct i2c_device_id dmard09_id[] = {
129*4882a593Smuzhiyun 	{ "dmard09", 0},
130*4882a593Smuzhiyun 	{ },
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, dmard09_id);
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun static struct i2c_driver dmard09_driver = {
136*4882a593Smuzhiyun 	.driver = {
137*4882a593Smuzhiyun 		.name = DMARD09_DRV_NAME
138*4882a593Smuzhiyun 	},
139*4882a593Smuzhiyun 	.probe = dmard09_probe,
140*4882a593Smuzhiyun 	.id_table = dmard09_id,
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun module_i2c_driver(dmard09_driver);
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun MODULE_AUTHOR("Jelle van der Waa <jelle@vdwaa.nl>");
146*4882a593Smuzhiyun MODULE_DESCRIPTION("DMARD09 3-axis accelerometer driver");
147*4882a593Smuzhiyun MODULE_LICENSE("GPL");
148