xref: /OK3568_Linux_fs/kernel/drivers/iio/accel/dmard06.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * IIO driver for Domintech DMARD06 accelerometer
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2016 Aleksei Mamlin <mamlinav@gmail.com>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
10*4882a593Smuzhiyun #include <linux/i2c.h>
11*4882a593Smuzhiyun #include <linux/iio/iio.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define DMARD06_DRV_NAME		"dmard06"
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun /* Device data registers */
16*4882a593Smuzhiyun #define DMARD06_CHIP_ID_REG		0x0f
17*4882a593Smuzhiyun #define DMARD06_TOUT_REG		0x40
18*4882a593Smuzhiyun #define DMARD06_XOUT_REG		0x41
19*4882a593Smuzhiyun #define DMARD06_YOUT_REG		0x42
20*4882a593Smuzhiyun #define DMARD06_ZOUT_REG		0x43
21*4882a593Smuzhiyun #define DMARD06_CTRL1_REG		0x44
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun /* Device ID value */
24*4882a593Smuzhiyun #define DMARD05_CHIP_ID			0x05
25*4882a593Smuzhiyun #define DMARD06_CHIP_ID			0x06
26*4882a593Smuzhiyun #define DMARD07_CHIP_ID			0x07
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /* Device values */
29*4882a593Smuzhiyun #define DMARD05_AXIS_SCALE_VAL		15625
30*4882a593Smuzhiyun #define DMARD06_AXIS_SCALE_VAL		31250
31*4882a593Smuzhiyun #define DMARD06_TEMP_CENTER_VAL		25
32*4882a593Smuzhiyun #define DMARD06_SIGN_BIT		7
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /* Device power modes */
35*4882a593Smuzhiyun #define DMARD06_MODE_NORMAL		0x27
36*4882a593Smuzhiyun #define DMARD06_MODE_POWERDOWN		0x00
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun /* Device channels */
39*4882a593Smuzhiyun #define DMARD06_ACCEL_CHANNEL(_axis, _reg) {			\
40*4882a593Smuzhiyun 	.type = IIO_ACCEL,					\
41*4882a593Smuzhiyun 	.address = _reg,					\
42*4882a593Smuzhiyun 	.channel2 = IIO_MOD_##_axis,				\
43*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
44*4882a593Smuzhiyun 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
45*4882a593Smuzhiyun 	.modified = 1,						\
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #define DMARD06_TEMP_CHANNEL(_reg) {				\
49*4882a593Smuzhiyun 	.type = IIO_TEMP,					\
50*4882a593Smuzhiyun 	.address = _reg,					\
51*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
52*4882a593Smuzhiyun 			      BIT(IIO_CHAN_INFO_OFFSET),	\
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun struct dmard06_data {
56*4882a593Smuzhiyun 	struct i2c_client *client;
57*4882a593Smuzhiyun 	u8 chip_id;
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun static const struct iio_chan_spec dmard06_channels[] = {
61*4882a593Smuzhiyun 	DMARD06_ACCEL_CHANNEL(X, DMARD06_XOUT_REG),
62*4882a593Smuzhiyun 	DMARD06_ACCEL_CHANNEL(Y, DMARD06_YOUT_REG),
63*4882a593Smuzhiyun 	DMARD06_ACCEL_CHANNEL(Z, DMARD06_ZOUT_REG),
64*4882a593Smuzhiyun 	DMARD06_TEMP_CHANNEL(DMARD06_TOUT_REG),
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun 
dmard06_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)67*4882a593Smuzhiyun static int dmard06_read_raw(struct iio_dev *indio_dev,
68*4882a593Smuzhiyun 			    struct iio_chan_spec const *chan,
69*4882a593Smuzhiyun 			    int *val, int *val2, long mask)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun 	struct dmard06_data *dmard06 = iio_priv(indio_dev);
72*4882a593Smuzhiyun 	int ret;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	switch (mask) {
75*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
76*4882a593Smuzhiyun 		ret = i2c_smbus_read_byte_data(dmard06->client,
77*4882a593Smuzhiyun 					       chan->address);
78*4882a593Smuzhiyun 		if (ret < 0) {
79*4882a593Smuzhiyun 			dev_err(&dmard06->client->dev,
80*4882a593Smuzhiyun 				"Error reading data: %d\n", ret);
81*4882a593Smuzhiyun 			return ret;
82*4882a593Smuzhiyun 		}
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun 		*val = sign_extend32(ret, DMARD06_SIGN_BIT);
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 		if (dmard06->chip_id == DMARD06_CHIP_ID)
87*4882a593Smuzhiyun 			*val = *val >> 1;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 		switch (chan->type) {
90*4882a593Smuzhiyun 		case IIO_ACCEL:
91*4882a593Smuzhiyun 			return IIO_VAL_INT;
92*4882a593Smuzhiyun 		case IIO_TEMP:
93*4882a593Smuzhiyun 			if (dmard06->chip_id != DMARD06_CHIP_ID)
94*4882a593Smuzhiyun 				*val = *val / 2;
95*4882a593Smuzhiyun 			return IIO_VAL_INT;
96*4882a593Smuzhiyun 		default:
97*4882a593Smuzhiyun 			return -EINVAL;
98*4882a593Smuzhiyun 		}
99*4882a593Smuzhiyun 	case IIO_CHAN_INFO_OFFSET:
100*4882a593Smuzhiyun 		switch (chan->type) {
101*4882a593Smuzhiyun 		case IIO_TEMP:
102*4882a593Smuzhiyun 			*val = DMARD06_TEMP_CENTER_VAL;
103*4882a593Smuzhiyun 			return IIO_VAL_INT;
104*4882a593Smuzhiyun 		default:
105*4882a593Smuzhiyun 			return -EINVAL;
106*4882a593Smuzhiyun 		}
107*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
108*4882a593Smuzhiyun 		switch (chan->type) {
109*4882a593Smuzhiyun 		case IIO_ACCEL:
110*4882a593Smuzhiyun 			*val = 0;
111*4882a593Smuzhiyun 			if (dmard06->chip_id == DMARD06_CHIP_ID)
112*4882a593Smuzhiyun 				*val2 = DMARD06_AXIS_SCALE_VAL;
113*4882a593Smuzhiyun 			else
114*4882a593Smuzhiyun 				*val2 = DMARD05_AXIS_SCALE_VAL;
115*4882a593Smuzhiyun 			return IIO_VAL_INT_PLUS_MICRO;
116*4882a593Smuzhiyun 		default:
117*4882a593Smuzhiyun 			return -EINVAL;
118*4882a593Smuzhiyun 		}
119*4882a593Smuzhiyun 	default:
120*4882a593Smuzhiyun 		return -EINVAL;
121*4882a593Smuzhiyun 	}
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun static const struct iio_info dmard06_info = {
125*4882a593Smuzhiyun 	.read_raw	= dmard06_read_raw,
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun 
dmard06_probe(struct i2c_client * client,const struct i2c_device_id * id)128*4882a593Smuzhiyun static int dmard06_probe(struct i2c_client *client,
129*4882a593Smuzhiyun 			const struct i2c_device_id *id)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun 	int ret;
132*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
133*4882a593Smuzhiyun 	struct dmard06_data *dmard06;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
136*4882a593Smuzhiyun 		dev_err(&client->dev, "I2C check functionality failed\n");
137*4882a593Smuzhiyun 		return -ENXIO;
138*4882a593Smuzhiyun 	}
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*dmard06));
141*4882a593Smuzhiyun 	if (!indio_dev) {
142*4882a593Smuzhiyun 		dev_err(&client->dev, "Failed to allocate iio device\n");
143*4882a593Smuzhiyun 		return -ENOMEM;
144*4882a593Smuzhiyun 	}
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	dmard06 = iio_priv(indio_dev);
147*4882a593Smuzhiyun 	dmard06->client = client;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(dmard06->client, DMARD06_CHIP_ID_REG);
150*4882a593Smuzhiyun 	if (ret < 0) {
151*4882a593Smuzhiyun 		dev_err(&client->dev, "Error reading chip id: %d\n", ret);
152*4882a593Smuzhiyun 		return ret;
153*4882a593Smuzhiyun 	}
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	if (ret != DMARD05_CHIP_ID && ret != DMARD06_CHIP_ID &&
156*4882a593Smuzhiyun 	    ret != DMARD07_CHIP_ID) {
157*4882a593Smuzhiyun 		dev_err(&client->dev, "Invalid chip id: %02d\n", ret);
158*4882a593Smuzhiyun 		return -ENODEV;
159*4882a593Smuzhiyun 	}
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	dmard06->chip_id = ret;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	i2c_set_clientdata(client, indio_dev);
164*4882a593Smuzhiyun 	indio_dev->name = DMARD06_DRV_NAME;
165*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
166*4882a593Smuzhiyun 	indio_dev->channels = dmard06_channels;
167*4882a593Smuzhiyun 	indio_dev->num_channels = ARRAY_SIZE(dmard06_channels);
168*4882a593Smuzhiyun 	indio_dev->info = &dmard06_info;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun 	return devm_iio_device_register(&client->dev, indio_dev);
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
dmard06_suspend(struct device * dev)174*4882a593Smuzhiyun static int dmard06_suspend(struct device *dev)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
177*4882a593Smuzhiyun 	struct dmard06_data *dmard06 = iio_priv(indio_dev);
178*4882a593Smuzhiyun 	int ret;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	ret = i2c_smbus_write_byte_data(dmard06->client, DMARD06_CTRL1_REG,
181*4882a593Smuzhiyun 					DMARD06_MODE_POWERDOWN);
182*4882a593Smuzhiyun 	if (ret < 0)
183*4882a593Smuzhiyun 		return ret;
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	return 0;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun 
dmard06_resume(struct device * dev)188*4882a593Smuzhiyun static int dmard06_resume(struct device *dev)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
191*4882a593Smuzhiyun 	struct dmard06_data *dmard06 = iio_priv(indio_dev);
192*4882a593Smuzhiyun 	int ret;
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	ret = i2c_smbus_write_byte_data(dmard06->client, DMARD06_CTRL1_REG,
195*4882a593Smuzhiyun 					DMARD06_MODE_NORMAL);
196*4882a593Smuzhiyun 	if (ret < 0)
197*4882a593Smuzhiyun 		return ret;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	return 0;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(dmard06_pm_ops, dmard06_suspend, dmard06_resume);
203*4882a593Smuzhiyun #define DMARD06_PM_OPS (&dmard06_pm_ops)
204*4882a593Smuzhiyun #else
205*4882a593Smuzhiyun #define DMARD06_PM_OPS NULL
206*4882a593Smuzhiyun #endif
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun static const struct i2c_device_id dmard06_id[] = {
209*4882a593Smuzhiyun 	{ "dmard05", 0 },
210*4882a593Smuzhiyun 	{ "dmard06", 0 },
211*4882a593Smuzhiyun 	{ "dmard07", 0 },
212*4882a593Smuzhiyun 	{ }
213*4882a593Smuzhiyun };
214*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, dmard06_id);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun static const struct of_device_id dmard06_of_match[] = {
217*4882a593Smuzhiyun 	{ .compatible = "domintech,dmard05" },
218*4882a593Smuzhiyun 	{ .compatible = "domintech,dmard06" },
219*4882a593Smuzhiyun 	{ .compatible = "domintech,dmard07" },
220*4882a593Smuzhiyun 	{ }
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, dmard06_of_match);
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun static struct i2c_driver dmard06_driver = {
225*4882a593Smuzhiyun 	.probe = dmard06_probe,
226*4882a593Smuzhiyun 	.id_table = dmard06_id,
227*4882a593Smuzhiyun 	.driver = {
228*4882a593Smuzhiyun 		.name = DMARD06_DRV_NAME,
229*4882a593Smuzhiyun 		.of_match_table = dmard06_of_match,
230*4882a593Smuzhiyun 		.pm = DMARD06_PM_OPS,
231*4882a593Smuzhiyun 	},
232*4882a593Smuzhiyun };
233*4882a593Smuzhiyun module_i2c_driver(dmard06_driver);
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun MODULE_AUTHOR("Aleksei Mamlin <mamlinav@gmail.com>");
236*4882a593Smuzhiyun MODULE_DESCRIPTION("Domintech DMARD06 accelerometer driver");
237*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
238