1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /**
3*4882a593Smuzhiyun * IIO driver for the MiraMEMS DA311 3-axis accelerometer
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2016 Hans de Goede <hdegoede@redhat.com>
6*4882a593Smuzhiyun * Copyright (c) 2011-2013 MiraMEMS Sensing Technology Co., Ltd.
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/i2c.h>
11*4882a593Smuzhiyun #include <linux/iio/iio.h>
12*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
13*4882a593Smuzhiyun #include <linux/byteorder/generic.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define DA311_CHIP_ID 0x13
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun * Note register addressed go from 0 - 0x3f and then wrap.
19*4882a593Smuzhiyun * For some reason there are 2 banks with 0 - 0x3f addresses,
20*4882a593Smuzhiyun * rather then a single 0-0x7f bank.
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* Bank 0 regs */
24*4882a593Smuzhiyun #define DA311_REG_BANK 0x0000
25*4882a593Smuzhiyun #define DA311_REG_LDO_REG 0x0006
26*4882a593Smuzhiyun #define DA311_REG_CHIP_ID 0x000f
27*4882a593Smuzhiyun #define DA311_REG_TEMP_CFG_REG 0x001f
28*4882a593Smuzhiyun #define DA311_REG_CTRL_REG1 0x0020
29*4882a593Smuzhiyun #define DA311_REG_CTRL_REG3 0x0022
30*4882a593Smuzhiyun #define DA311_REG_CTRL_REG4 0x0023
31*4882a593Smuzhiyun #define DA311_REG_CTRL_REG5 0x0024
32*4882a593Smuzhiyun #define DA311_REG_CTRL_REG6 0x0025
33*4882a593Smuzhiyun #define DA311_REG_STATUS_REG 0x0027
34*4882a593Smuzhiyun #define DA311_REG_OUT_X_L 0x0028
35*4882a593Smuzhiyun #define DA311_REG_OUT_X_H 0x0029
36*4882a593Smuzhiyun #define DA311_REG_OUT_Y_L 0x002a
37*4882a593Smuzhiyun #define DA311_REG_OUT_Y_H 0x002b
38*4882a593Smuzhiyun #define DA311_REG_OUT_Z_L 0x002c
39*4882a593Smuzhiyun #define DA311_REG_OUT_Z_H 0x002d
40*4882a593Smuzhiyun #define DA311_REG_INT1_CFG 0x0030
41*4882a593Smuzhiyun #define DA311_REG_INT1_SRC 0x0031
42*4882a593Smuzhiyun #define DA311_REG_INT1_THS 0x0032
43*4882a593Smuzhiyun #define DA311_REG_INT1_DURATION 0x0033
44*4882a593Smuzhiyun #define DA311_REG_INT2_CFG 0x0034
45*4882a593Smuzhiyun #define DA311_REG_INT2_SRC 0x0035
46*4882a593Smuzhiyun #define DA311_REG_INT2_THS 0x0036
47*4882a593Smuzhiyun #define DA311_REG_INT2_DURATION 0x0037
48*4882a593Smuzhiyun #define DA311_REG_CLICK_CFG 0x0038
49*4882a593Smuzhiyun #define DA311_REG_CLICK_SRC 0x0039
50*4882a593Smuzhiyun #define DA311_REG_CLICK_THS 0x003a
51*4882a593Smuzhiyun #define DA311_REG_TIME_LIMIT 0x003b
52*4882a593Smuzhiyun #define DA311_REG_TIME_LATENCY 0x003c
53*4882a593Smuzhiyun #define DA311_REG_TIME_WINDOW 0x003d
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* Bank 1 regs */
56*4882a593Smuzhiyun #define DA311_REG_SOFT_RESET 0x0105
57*4882a593Smuzhiyun #define DA311_REG_OTP_XOFF_L 0x0110
58*4882a593Smuzhiyun #define DA311_REG_OTP_XOFF_H 0x0111
59*4882a593Smuzhiyun #define DA311_REG_OTP_YOFF_L 0x0112
60*4882a593Smuzhiyun #define DA311_REG_OTP_YOFF_H 0x0113
61*4882a593Smuzhiyun #define DA311_REG_OTP_ZOFF_L 0x0114
62*4882a593Smuzhiyun #define DA311_REG_OTP_ZOFF_H 0x0115
63*4882a593Smuzhiyun #define DA311_REG_OTP_XSO 0x0116
64*4882a593Smuzhiyun #define DA311_REG_OTP_YSO 0x0117
65*4882a593Smuzhiyun #define DA311_REG_OTP_ZSO 0x0118
66*4882a593Smuzhiyun #define DA311_REG_OTP_TRIM_OSC 0x011b
67*4882a593Smuzhiyun #define DA311_REG_LPF_ABSOLUTE 0x011c
68*4882a593Smuzhiyun #define DA311_REG_TEMP_OFF1 0x0127
69*4882a593Smuzhiyun #define DA311_REG_TEMP_OFF2 0x0128
70*4882a593Smuzhiyun #define DA311_REG_TEMP_OFF3 0x0129
71*4882a593Smuzhiyun #define DA311_REG_OTP_TRIM_THERM_H 0x011a
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /*
74*4882a593Smuzhiyun * a value of + or -1024 corresponds to + or - 1G
75*4882a593Smuzhiyun * scale = 9.81 / 1024 = 0.009580078
76*4882a593Smuzhiyun */
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun static const int da311_nscale = 9580078;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun #define DA311_CHANNEL(reg, axis) { \
81*4882a593Smuzhiyun .type = IIO_ACCEL, \
82*4882a593Smuzhiyun .address = reg, \
83*4882a593Smuzhiyun .modified = 1, \
84*4882a593Smuzhiyun .channel2 = IIO_MOD_##axis, \
85*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
86*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static const struct iio_chan_spec da311_channels[] = {
90*4882a593Smuzhiyun /* | 0x80 comes from the android driver */
91*4882a593Smuzhiyun DA311_CHANNEL(DA311_REG_OUT_X_L | 0x80, X),
92*4882a593Smuzhiyun DA311_CHANNEL(DA311_REG_OUT_Y_L | 0x80, Y),
93*4882a593Smuzhiyun DA311_CHANNEL(DA311_REG_OUT_Z_L | 0x80, Z),
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun struct da311_data {
97*4882a593Smuzhiyun struct i2c_client *client;
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
da311_register_mask_write(struct i2c_client * client,u16 addr,u8 mask,u8 data)100*4882a593Smuzhiyun static int da311_register_mask_write(struct i2c_client *client, u16 addr,
101*4882a593Smuzhiyun u8 mask, u8 data)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun int ret;
104*4882a593Smuzhiyun u8 tmp_data = 0;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun if (addr & 0xff00) {
107*4882a593Smuzhiyun /* Select bank 1 */
108*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(client, DA311_REG_BANK, 0x01);
109*4882a593Smuzhiyun if (ret < 0)
110*4882a593Smuzhiyun return ret;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun if (mask != 0xff) {
114*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(client, addr);
115*4882a593Smuzhiyun if (ret < 0)
116*4882a593Smuzhiyun return ret;
117*4882a593Smuzhiyun tmp_data = ret;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun tmp_data &= ~mask;
121*4882a593Smuzhiyun tmp_data |= data & mask;
122*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(client, addr & 0xff, tmp_data);
123*4882a593Smuzhiyun if (ret < 0)
124*4882a593Smuzhiyun return ret;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun if (addr & 0xff00) {
127*4882a593Smuzhiyun /* Back to bank 0 */
128*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(client, DA311_REG_BANK, 0x00);
129*4882a593Smuzhiyun if (ret < 0)
130*4882a593Smuzhiyun return ret;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun return 0;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun /* Init sequence taken from the android driver */
da311_reset(struct i2c_client * client)137*4882a593Smuzhiyun static int da311_reset(struct i2c_client *client)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun static const struct {
140*4882a593Smuzhiyun u16 addr;
141*4882a593Smuzhiyun u8 mask;
142*4882a593Smuzhiyun u8 data;
143*4882a593Smuzhiyun } init_data[] = {
144*4882a593Smuzhiyun { DA311_REG_TEMP_CFG_REG, 0xff, 0x08 },
145*4882a593Smuzhiyun { DA311_REG_CTRL_REG5, 0xff, 0x80 },
146*4882a593Smuzhiyun { DA311_REG_CTRL_REG4, 0x30, 0x00 },
147*4882a593Smuzhiyun { DA311_REG_CTRL_REG1, 0xff, 0x6f },
148*4882a593Smuzhiyun { DA311_REG_TEMP_CFG_REG, 0xff, 0x88 },
149*4882a593Smuzhiyun { DA311_REG_LDO_REG, 0xff, 0x02 },
150*4882a593Smuzhiyun { DA311_REG_OTP_TRIM_OSC, 0xff, 0x27 },
151*4882a593Smuzhiyun { DA311_REG_LPF_ABSOLUTE, 0xff, 0x30 },
152*4882a593Smuzhiyun { DA311_REG_TEMP_OFF1, 0xff, 0x3f },
153*4882a593Smuzhiyun { DA311_REG_TEMP_OFF2, 0xff, 0xff },
154*4882a593Smuzhiyun { DA311_REG_TEMP_OFF3, 0xff, 0x0f },
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun int i, ret;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun /* Reset */
159*4882a593Smuzhiyun ret = da311_register_mask_write(client, DA311_REG_SOFT_RESET,
160*4882a593Smuzhiyun 0xff, 0xaa);
161*4882a593Smuzhiyun if (ret < 0)
162*4882a593Smuzhiyun return ret;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(init_data); i++) {
165*4882a593Smuzhiyun ret = da311_register_mask_write(client,
166*4882a593Smuzhiyun init_data[i].addr,
167*4882a593Smuzhiyun init_data[i].mask,
168*4882a593Smuzhiyun init_data[i].data);
169*4882a593Smuzhiyun if (ret < 0)
170*4882a593Smuzhiyun return ret;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun return 0;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
da311_enable(struct i2c_client * client,bool enable)176*4882a593Smuzhiyun static int da311_enable(struct i2c_client *client, bool enable)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun u8 data = enable ? 0x00 : 0x20;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun return da311_register_mask_write(client, DA311_REG_TEMP_CFG_REG,
181*4882a593Smuzhiyun 0x20, data);
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
da311_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)184*4882a593Smuzhiyun static int da311_read_raw(struct iio_dev *indio_dev,
185*4882a593Smuzhiyun struct iio_chan_spec const *chan,
186*4882a593Smuzhiyun int *val, int *val2, long mask)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun struct da311_data *data = iio_priv(indio_dev);
189*4882a593Smuzhiyun int ret;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun switch (mask) {
192*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
193*4882a593Smuzhiyun ret = i2c_smbus_read_word_data(data->client, chan->address);
194*4882a593Smuzhiyun if (ret < 0)
195*4882a593Smuzhiyun return ret;
196*4882a593Smuzhiyun /*
197*4882a593Smuzhiyun * Values are 12 bits, stored as 16 bits with the 4
198*4882a593Smuzhiyun * least significant bits always 0.
199*4882a593Smuzhiyun */
200*4882a593Smuzhiyun *val = (short)ret >> 4;
201*4882a593Smuzhiyun return IIO_VAL_INT;
202*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
203*4882a593Smuzhiyun *val = 0;
204*4882a593Smuzhiyun *val2 = da311_nscale;
205*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_NANO;
206*4882a593Smuzhiyun default:
207*4882a593Smuzhiyun return -EINVAL;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun static const struct iio_info da311_info = {
212*4882a593Smuzhiyun .read_raw = da311_read_raw,
213*4882a593Smuzhiyun };
214*4882a593Smuzhiyun
da311_probe(struct i2c_client * client,const struct i2c_device_id * id)215*4882a593Smuzhiyun static int da311_probe(struct i2c_client *client,
216*4882a593Smuzhiyun const struct i2c_device_id *id)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun int ret;
219*4882a593Smuzhiyun struct iio_dev *indio_dev;
220*4882a593Smuzhiyun struct da311_data *data;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(client, DA311_REG_CHIP_ID);
223*4882a593Smuzhiyun if (ret != DA311_CHIP_ID)
224*4882a593Smuzhiyun return (ret < 0) ? ret : -ENODEV;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
227*4882a593Smuzhiyun if (!indio_dev)
228*4882a593Smuzhiyun return -ENOMEM;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun data = iio_priv(indio_dev);
231*4882a593Smuzhiyun data->client = client;
232*4882a593Smuzhiyun i2c_set_clientdata(client, indio_dev);
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun indio_dev->info = &da311_info;
235*4882a593Smuzhiyun indio_dev->name = "da311";
236*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
237*4882a593Smuzhiyun indio_dev->channels = da311_channels;
238*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(da311_channels);
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun ret = da311_reset(client);
241*4882a593Smuzhiyun if (ret < 0)
242*4882a593Smuzhiyun return ret;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun ret = da311_enable(client, true);
245*4882a593Smuzhiyun if (ret < 0)
246*4882a593Smuzhiyun return ret;
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
249*4882a593Smuzhiyun if (ret < 0) {
250*4882a593Smuzhiyun dev_err(&client->dev, "device_register failed\n");
251*4882a593Smuzhiyun da311_enable(client, false);
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun return ret;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
da311_remove(struct i2c_client * client)257*4882a593Smuzhiyun static int da311_remove(struct i2c_client *client)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(client);
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun iio_device_unregister(indio_dev);
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun return da311_enable(client, false);
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
da311_suspend(struct device * dev)267*4882a593Smuzhiyun static int da311_suspend(struct device *dev)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun return da311_enable(to_i2c_client(dev), false);
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun
da311_resume(struct device * dev)272*4882a593Smuzhiyun static int da311_resume(struct device *dev)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun return da311_enable(to_i2c_client(dev), true);
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun #endif
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(da311_pm_ops, da311_suspend, da311_resume);
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun static const struct i2c_device_id da311_i2c_id[] = {
281*4882a593Smuzhiyun {"da311", 0},
282*4882a593Smuzhiyun {}
283*4882a593Smuzhiyun };
284*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, da311_i2c_id);
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun static struct i2c_driver da311_driver = {
287*4882a593Smuzhiyun .driver = {
288*4882a593Smuzhiyun .name = "da311",
289*4882a593Smuzhiyun .pm = &da311_pm_ops,
290*4882a593Smuzhiyun },
291*4882a593Smuzhiyun .probe = da311_probe,
292*4882a593Smuzhiyun .remove = da311_remove,
293*4882a593Smuzhiyun .id_table = da311_i2c_id,
294*4882a593Smuzhiyun };
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun module_i2c_driver(da311_driver);
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun MODULE_AUTHOR("Hans de Goede <hdegoede@redhat.com>");
299*4882a593Smuzhiyun MODULE_DESCRIPTION("MiraMEMS DA311 3-Axis Accelerometer driver");
300*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
301