1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Register constants and other forward declarations needed by the bma400 4*4882a593Smuzhiyun * sources. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright 2019 Dan Robertson <dan@dlrobertson.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef _BMA400_H_ 10*4882a593Smuzhiyun #define _BMA400_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/bits.h> 13*4882a593Smuzhiyun #include <linux/regmap.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * Read-Only Registers 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Status and ID registers */ 20*4882a593Smuzhiyun #define BMA400_CHIP_ID_REG 0x00 21*4882a593Smuzhiyun #define BMA400_ERR_REG 0x02 22*4882a593Smuzhiyun #define BMA400_STATUS_REG 0x03 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* Acceleration registers */ 25*4882a593Smuzhiyun #define BMA400_X_AXIS_LSB_REG 0x04 26*4882a593Smuzhiyun #define BMA400_X_AXIS_MSB_REG 0x05 27*4882a593Smuzhiyun #define BMA400_Y_AXIS_LSB_REG 0x06 28*4882a593Smuzhiyun #define BMA400_Y_AXIS_MSB_REG 0x07 29*4882a593Smuzhiyun #define BMA400_Z_AXIS_LSB_REG 0x08 30*4882a593Smuzhiyun #define BMA400_Z_AXIS_MSB_REG 0x09 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Sensor time registers */ 33*4882a593Smuzhiyun #define BMA400_SENSOR_TIME0 0x0a 34*4882a593Smuzhiyun #define BMA400_SENSOR_TIME1 0x0b 35*4882a593Smuzhiyun #define BMA400_SENSOR_TIME2 0x0c 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Event and interrupt registers */ 38*4882a593Smuzhiyun #define BMA400_EVENT_REG 0x0d 39*4882a593Smuzhiyun #define BMA400_INT_STAT0_REG 0x0e 40*4882a593Smuzhiyun #define BMA400_INT_STAT1_REG 0x0f 41*4882a593Smuzhiyun #define BMA400_INT_STAT2_REG 0x10 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Temperature register */ 44*4882a593Smuzhiyun #define BMA400_TEMP_DATA_REG 0x11 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* FIFO length and data registers */ 47*4882a593Smuzhiyun #define BMA400_FIFO_LENGTH0_REG 0x12 48*4882a593Smuzhiyun #define BMA400_FIFO_LENGTH1_REG 0x13 49*4882a593Smuzhiyun #define BMA400_FIFO_DATA_REG 0x14 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Step count registers */ 52*4882a593Smuzhiyun #define BMA400_STEP_CNT0_REG 0x15 53*4882a593Smuzhiyun #define BMA400_STEP_CNT1_REG 0x16 54*4882a593Smuzhiyun #define BMA400_STEP_CNT3_REG 0x17 55*4882a593Smuzhiyun #define BMA400_STEP_STAT_REG 0x18 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * Read-write configuration registers 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define BMA400_ACC_CONFIG0_REG 0x19 61*4882a593Smuzhiyun #define BMA400_ACC_CONFIG1_REG 0x1a 62*4882a593Smuzhiyun #define BMA400_ACC_CONFIG2_REG 0x1b 63*4882a593Smuzhiyun #define BMA400_CMD_REG 0x7e 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Chip ID of BMA 400 devices found in the chip ID register. */ 66*4882a593Smuzhiyun #define BMA400_ID_REG_VAL 0x90 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define BMA400_LP_OSR_SHIFT 5 69*4882a593Smuzhiyun #define BMA400_NP_OSR_SHIFT 4 70*4882a593Smuzhiyun #define BMA400_SCALE_SHIFT 6 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define BMA400_TWO_BITS_MASK GENMASK(1, 0) 73*4882a593Smuzhiyun #define BMA400_LP_OSR_MASK GENMASK(6, 5) 74*4882a593Smuzhiyun #define BMA400_NP_OSR_MASK GENMASK(5, 4) 75*4882a593Smuzhiyun #define BMA400_ACC_ODR_MASK GENMASK(3, 0) 76*4882a593Smuzhiyun #define BMA400_ACC_SCALE_MASK GENMASK(7, 6) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #define BMA400_ACC_ODR_MIN_RAW 0x05 79*4882a593Smuzhiyun #define BMA400_ACC_ODR_LP_RAW 0x06 80*4882a593Smuzhiyun #define BMA400_ACC_ODR_MAX_RAW 0x0b 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define BMA400_ACC_ODR_MAX_HZ 800 83*4882a593Smuzhiyun #define BMA400_ACC_ODR_MIN_WHOLE_HZ 25 84*4882a593Smuzhiyun #define BMA400_ACC_ODR_MIN_HZ 12 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* 87*4882a593Smuzhiyun * BMA400_SCALE_MIN macro value represents m/s^2 for 1 LSB before 88*4882a593Smuzhiyun * converting to micro values for +-2g range. 89*4882a593Smuzhiyun * 90*4882a593Smuzhiyun * For +-2g - 1 LSB = 0.976562 milli g = 0.009576 m/s^2 91*4882a593Smuzhiyun * For +-4g - 1 LSB = 1.953125 milli g = 0.019153 m/s^2 92*4882a593Smuzhiyun * For +-16g - 1 LSB = 7.8125 milli g = 0.076614 m/s^2 93*4882a593Smuzhiyun * 94*4882a593Smuzhiyun * The raw value which is used to select the different ranges is determined 95*4882a593Smuzhiyun * by the first bit set position from the scale value, so BMA400_SCALE_MIN 96*4882a593Smuzhiyun * should be odd. 97*4882a593Smuzhiyun * 98*4882a593Smuzhiyun * Scale values for +-2g, +-4g, +-8g and +-16g are populated into bma400_scales 99*4882a593Smuzhiyun * array by left shifting BMA400_SCALE_MIN. 100*4882a593Smuzhiyun * e.g.: 101*4882a593Smuzhiyun * To select +-2g = 9577 << 0 = raw value to write is 0. 102*4882a593Smuzhiyun * To select +-8g = 9577 << 2 = raw value to write is 2. 103*4882a593Smuzhiyun * To select +-16g = 9577 << 3 = raw value to write is 3. 104*4882a593Smuzhiyun */ 105*4882a593Smuzhiyun #define BMA400_SCALE_MIN 9577 106*4882a593Smuzhiyun #define BMA400_SCALE_MAX 76617 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define BMA400_NUM_REGULATORS 2 109*4882a593Smuzhiyun #define BMA400_VDD_REGULATOR 0 110*4882a593Smuzhiyun #define BMA400_VDDIO_REGULATOR 1 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun extern const struct regmap_config bma400_regmap_config; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun int bma400_probe(struct device *dev, struct regmap *regmap, const char *name); 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun int bma400_remove(struct device *dev); 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #endif 119