1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /**
3*4882a593Smuzhiyun * BMA220 Digital triaxial acceleration sensor driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2016,2020 Intel Corporation.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/bits.h>
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/spi/spi.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/iio/buffer.h>
15*4882a593Smuzhiyun #include <linux/iio/iio.h>
16*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
17*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
18*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define BMA220_REG_ID 0x00
21*4882a593Smuzhiyun #define BMA220_REG_ACCEL_X 0x02
22*4882a593Smuzhiyun #define BMA220_REG_ACCEL_Y 0x03
23*4882a593Smuzhiyun #define BMA220_REG_ACCEL_Z 0x04
24*4882a593Smuzhiyun #define BMA220_REG_RANGE 0x11
25*4882a593Smuzhiyun #define BMA220_REG_SUSPEND 0x18
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define BMA220_CHIP_ID 0xDD
28*4882a593Smuzhiyun #define BMA220_READ_MASK BIT(7)
29*4882a593Smuzhiyun #define BMA220_RANGE_MASK GENMASK(1, 0)
30*4882a593Smuzhiyun #define BMA220_DATA_SHIFT 2
31*4882a593Smuzhiyun #define BMA220_SUSPEND_SLEEP 0xFF
32*4882a593Smuzhiyun #define BMA220_SUSPEND_WAKE 0x00
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define BMA220_DEVICE_NAME "bma220"
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define BMA220_ACCEL_CHANNEL(index, reg, axis) { \
37*4882a593Smuzhiyun .type = IIO_ACCEL, \
38*4882a593Smuzhiyun .address = reg, \
39*4882a593Smuzhiyun .modified = 1, \
40*4882a593Smuzhiyun .channel2 = IIO_MOD_##axis, \
41*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
42*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
43*4882a593Smuzhiyun .scan_index = index, \
44*4882a593Smuzhiyun .scan_type = { \
45*4882a593Smuzhiyun .sign = 's', \
46*4882a593Smuzhiyun .realbits = 6, \
47*4882a593Smuzhiyun .storagebits = 8, \
48*4882a593Smuzhiyun .shift = BMA220_DATA_SHIFT, \
49*4882a593Smuzhiyun .endianness = IIO_CPU, \
50*4882a593Smuzhiyun }, \
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun enum bma220_axis {
54*4882a593Smuzhiyun AXIS_X,
55*4882a593Smuzhiyun AXIS_Y,
56*4882a593Smuzhiyun AXIS_Z,
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static const int bma220_scale_table[][2] = {
60*4882a593Smuzhiyun {0, 623000}, {1, 248000}, {2, 491000}, {4, 983000},
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun struct bma220_data {
64*4882a593Smuzhiyun struct spi_device *spi_device;
65*4882a593Smuzhiyun struct mutex lock;
66*4882a593Smuzhiyun struct {
67*4882a593Smuzhiyun s8 chans[3];
68*4882a593Smuzhiyun /* Ensure timestamp is naturally aligned. */
69*4882a593Smuzhiyun s64 timestamp __aligned(8);
70*4882a593Smuzhiyun } scan;
71*4882a593Smuzhiyun u8 tx_buf[2] ____cacheline_aligned;
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun static const struct iio_chan_spec bma220_channels[] = {
75*4882a593Smuzhiyun BMA220_ACCEL_CHANNEL(0, BMA220_REG_ACCEL_X, X),
76*4882a593Smuzhiyun BMA220_ACCEL_CHANNEL(1, BMA220_REG_ACCEL_Y, Y),
77*4882a593Smuzhiyun BMA220_ACCEL_CHANNEL(2, BMA220_REG_ACCEL_Z, Z),
78*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(3),
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
bma220_read_reg(struct spi_device * spi,u8 reg)81*4882a593Smuzhiyun static inline int bma220_read_reg(struct spi_device *spi, u8 reg)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun return spi_w8r8(spi, reg | BMA220_READ_MASK);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun static const unsigned long bma220_accel_scan_masks[] = {
87*4882a593Smuzhiyun BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
88*4882a593Smuzhiyun 0
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
bma220_trigger_handler(int irq,void * p)91*4882a593Smuzhiyun static irqreturn_t bma220_trigger_handler(int irq, void *p)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun int ret;
94*4882a593Smuzhiyun struct iio_poll_func *pf = p;
95*4882a593Smuzhiyun struct iio_dev *indio_dev = pf->indio_dev;
96*4882a593Smuzhiyun struct bma220_data *data = iio_priv(indio_dev);
97*4882a593Smuzhiyun struct spi_device *spi = data->spi_device;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun mutex_lock(&data->lock);
100*4882a593Smuzhiyun data->tx_buf[0] = BMA220_REG_ACCEL_X | BMA220_READ_MASK;
101*4882a593Smuzhiyun ret = spi_write_then_read(spi, data->tx_buf, 1, &data->scan.chans,
102*4882a593Smuzhiyun ARRAY_SIZE(bma220_channels) - 1);
103*4882a593Smuzhiyun if (ret < 0)
104*4882a593Smuzhiyun goto err;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
107*4882a593Smuzhiyun pf->timestamp);
108*4882a593Smuzhiyun err:
109*4882a593Smuzhiyun mutex_unlock(&data->lock);
110*4882a593Smuzhiyun iio_trigger_notify_done(indio_dev->trig);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun return IRQ_HANDLED;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
bma220_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)115*4882a593Smuzhiyun static int bma220_read_raw(struct iio_dev *indio_dev,
116*4882a593Smuzhiyun struct iio_chan_spec const *chan,
117*4882a593Smuzhiyun int *val, int *val2, long mask)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun int ret;
120*4882a593Smuzhiyun u8 range_idx;
121*4882a593Smuzhiyun struct bma220_data *data = iio_priv(indio_dev);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun switch (mask) {
124*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
125*4882a593Smuzhiyun ret = bma220_read_reg(data->spi_device, chan->address);
126*4882a593Smuzhiyun if (ret < 0)
127*4882a593Smuzhiyun return -EINVAL;
128*4882a593Smuzhiyun *val = sign_extend32(ret >> BMA220_DATA_SHIFT, 5);
129*4882a593Smuzhiyun return IIO_VAL_INT;
130*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
131*4882a593Smuzhiyun ret = bma220_read_reg(data->spi_device, BMA220_REG_RANGE);
132*4882a593Smuzhiyun if (ret < 0)
133*4882a593Smuzhiyun return ret;
134*4882a593Smuzhiyun range_idx = ret & BMA220_RANGE_MASK;
135*4882a593Smuzhiyun *val = bma220_scale_table[range_idx][0];
136*4882a593Smuzhiyun *val2 = bma220_scale_table[range_idx][1];
137*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun return -EINVAL;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
bma220_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)143*4882a593Smuzhiyun static int bma220_write_raw(struct iio_dev *indio_dev,
144*4882a593Smuzhiyun struct iio_chan_spec const *chan,
145*4882a593Smuzhiyun int val, int val2, long mask)
146*4882a593Smuzhiyun {
147*4882a593Smuzhiyun int i;
148*4882a593Smuzhiyun int ret;
149*4882a593Smuzhiyun int index = -1;
150*4882a593Smuzhiyun struct bma220_data *data = iio_priv(indio_dev);
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun switch (mask) {
153*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
154*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(bma220_scale_table); i++)
155*4882a593Smuzhiyun if (val == bma220_scale_table[i][0] &&
156*4882a593Smuzhiyun val2 == bma220_scale_table[i][1]) {
157*4882a593Smuzhiyun index = i;
158*4882a593Smuzhiyun break;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun if (index < 0)
161*4882a593Smuzhiyun return -EINVAL;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun mutex_lock(&data->lock);
164*4882a593Smuzhiyun data->tx_buf[0] = BMA220_REG_RANGE;
165*4882a593Smuzhiyun data->tx_buf[1] = index;
166*4882a593Smuzhiyun ret = spi_write(data->spi_device, data->tx_buf,
167*4882a593Smuzhiyun sizeof(data->tx_buf));
168*4882a593Smuzhiyun if (ret < 0)
169*4882a593Smuzhiyun dev_err(&data->spi_device->dev,
170*4882a593Smuzhiyun "failed to set measurement range\n");
171*4882a593Smuzhiyun mutex_unlock(&data->lock);
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun return 0;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun return -EINVAL;
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
bma220_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)179*4882a593Smuzhiyun static int bma220_read_avail(struct iio_dev *indio_dev,
180*4882a593Smuzhiyun struct iio_chan_spec const *chan,
181*4882a593Smuzhiyun const int **vals, int *type, int *length,
182*4882a593Smuzhiyun long mask)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun switch (mask) {
185*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
186*4882a593Smuzhiyun *vals = (int *)bma220_scale_table;
187*4882a593Smuzhiyun *type = IIO_VAL_INT_PLUS_MICRO;
188*4882a593Smuzhiyun *length = ARRAY_SIZE(bma220_scale_table) * 2;
189*4882a593Smuzhiyun return IIO_AVAIL_LIST;
190*4882a593Smuzhiyun default:
191*4882a593Smuzhiyun return -EINVAL;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun static const struct iio_info bma220_info = {
196*4882a593Smuzhiyun .read_raw = bma220_read_raw,
197*4882a593Smuzhiyun .write_raw = bma220_write_raw,
198*4882a593Smuzhiyun .read_avail = bma220_read_avail,
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun
bma220_init(struct spi_device * spi)201*4882a593Smuzhiyun static int bma220_init(struct spi_device *spi)
202*4882a593Smuzhiyun {
203*4882a593Smuzhiyun int ret;
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun ret = bma220_read_reg(spi, BMA220_REG_ID);
206*4882a593Smuzhiyun if (ret != BMA220_CHIP_ID)
207*4882a593Smuzhiyun return -ENODEV;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun /* Make sure the chip is powered on */
210*4882a593Smuzhiyun ret = bma220_read_reg(spi, BMA220_REG_SUSPEND);
211*4882a593Smuzhiyun if (ret == BMA220_SUSPEND_WAKE)
212*4882a593Smuzhiyun ret = bma220_read_reg(spi, BMA220_REG_SUSPEND);
213*4882a593Smuzhiyun if (ret < 0)
214*4882a593Smuzhiyun return ret;
215*4882a593Smuzhiyun if (ret == BMA220_SUSPEND_WAKE)
216*4882a593Smuzhiyun return -EBUSY;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun return 0;
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun
bma220_deinit(struct spi_device * spi)221*4882a593Smuzhiyun static int bma220_deinit(struct spi_device *spi)
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun int ret;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun /* Make sure the chip is powered off */
226*4882a593Smuzhiyun ret = bma220_read_reg(spi, BMA220_REG_SUSPEND);
227*4882a593Smuzhiyun if (ret == BMA220_SUSPEND_SLEEP)
228*4882a593Smuzhiyun ret = bma220_read_reg(spi, BMA220_REG_SUSPEND);
229*4882a593Smuzhiyun if (ret < 0)
230*4882a593Smuzhiyun return ret;
231*4882a593Smuzhiyun if (ret == BMA220_SUSPEND_SLEEP)
232*4882a593Smuzhiyun return -EBUSY;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun return 0;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
bma220_probe(struct spi_device * spi)237*4882a593Smuzhiyun static int bma220_probe(struct spi_device *spi)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun int ret;
240*4882a593Smuzhiyun struct iio_dev *indio_dev;
241*4882a593Smuzhiyun struct bma220_data *data;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*data));
244*4882a593Smuzhiyun if (!indio_dev) {
245*4882a593Smuzhiyun dev_err(&spi->dev, "iio allocation failed!\n");
246*4882a593Smuzhiyun return -ENOMEM;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun data = iio_priv(indio_dev);
250*4882a593Smuzhiyun data->spi_device = spi;
251*4882a593Smuzhiyun spi_set_drvdata(spi, indio_dev);
252*4882a593Smuzhiyun mutex_init(&data->lock);
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun indio_dev->info = &bma220_info;
255*4882a593Smuzhiyun indio_dev->name = BMA220_DEVICE_NAME;
256*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
257*4882a593Smuzhiyun indio_dev->channels = bma220_channels;
258*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(bma220_channels);
259*4882a593Smuzhiyun indio_dev->available_scan_masks = bma220_accel_scan_masks;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun ret = bma220_init(data->spi_device);
262*4882a593Smuzhiyun if (ret)
263*4882a593Smuzhiyun return ret;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun ret = iio_triggered_buffer_setup(indio_dev, iio_pollfunc_store_time,
266*4882a593Smuzhiyun bma220_trigger_handler, NULL);
267*4882a593Smuzhiyun if (ret < 0) {
268*4882a593Smuzhiyun dev_err(&spi->dev, "iio triggered buffer setup failed\n");
269*4882a593Smuzhiyun goto err_suspend;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
273*4882a593Smuzhiyun if (ret < 0) {
274*4882a593Smuzhiyun dev_err(&spi->dev, "iio_device_register failed\n");
275*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
276*4882a593Smuzhiyun goto err_suspend;
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun return 0;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun err_suspend:
282*4882a593Smuzhiyun return bma220_deinit(spi);
283*4882a593Smuzhiyun }
284*4882a593Smuzhiyun
bma220_remove(struct spi_device * spi)285*4882a593Smuzhiyun static int bma220_remove(struct spi_device *spi)
286*4882a593Smuzhiyun {
287*4882a593Smuzhiyun struct iio_dev *indio_dev = spi_get_drvdata(spi);
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun iio_device_unregister(indio_dev);
290*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun return bma220_deinit(spi);
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
bma220_suspend(struct device * dev)295*4882a593Smuzhiyun static __maybe_unused int bma220_suspend(struct device *dev)
296*4882a593Smuzhiyun {
297*4882a593Smuzhiyun struct bma220_data *data = iio_priv(dev_get_drvdata(dev));
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun /* The chip can be suspended/woken up by a simple register read. */
300*4882a593Smuzhiyun return bma220_read_reg(data->spi_device, BMA220_REG_SUSPEND);
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
bma220_resume(struct device * dev)303*4882a593Smuzhiyun static __maybe_unused int bma220_resume(struct device *dev)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun struct bma220_data *data = iio_priv(dev_get_drvdata(dev));
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun return bma220_read_reg(data->spi_device, BMA220_REG_SUSPEND);
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(bma220_pm_ops, bma220_suspend, bma220_resume);
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun static const struct spi_device_id bma220_spi_id[] = {
312*4882a593Smuzhiyun {"bma220", 0},
313*4882a593Smuzhiyun {}
314*4882a593Smuzhiyun };
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun static const struct acpi_device_id bma220_acpi_id[] = {
317*4882a593Smuzhiyun {"BMA0220", 0},
318*4882a593Smuzhiyun {}
319*4882a593Smuzhiyun };
320*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, bma220_spi_id);
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun static struct spi_driver bma220_driver = {
323*4882a593Smuzhiyun .driver = {
324*4882a593Smuzhiyun .name = "bma220_spi",
325*4882a593Smuzhiyun .pm = &bma220_pm_ops,
326*4882a593Smuzhiyun .acpi_match_table = bma220_acpi_id,
327*4882a593Smuzhiyun },
328*4882a593Smuzhiyun .probe = bma220_probe,
329*4882a593Smuzhiyun .remove = bma220_remove,
330*4882a593Smuzhiyun .id_table = bma220_spi_id,
331*4882a593Smuzhiyun };
332*4882a593Smuzhiyun module_spi_driver(bma220_driver);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun MODULE_AUTHOR("Tiberiu Breana <tiberiu.a.breana@intel.com>");
335*4882a593Smuzhiyun MODULE_DESCRIPTION("BMA220 acceleration sensor driver");
336*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
337