xref: /OK3568_Linux_fs/kernel/drivers/iio/accel/bma180.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * bma180.c - IIO driver for Bosch BMA180 triaxial acceleration sensor
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2013 Oleksandr Kravchenko <x0199363@ti.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Support for BMA250 (c) Peter Meerwald <pmeerw@pmeerw.net>
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * SPI is not supported by driver
10*4882a593Smuzhiyun  * BMA023/BMA150/SMB380: 7-bit I2C slave address 0x38
11*4882a593Smuzhiyun  * BMA180: 7-bit I2C slave address 0x40 or 0x41
12*4882a593Smuzhiyun  * BMA250: 7-bit I2C slave address 0x18 or 0x19
13*4882a593Smuzhiyun  * BMA254: 7-bit I2C slave address 0x18 or 0x19
14*4882a593Smuzhiyun  */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/i2c.h>
18*4882a593Smuzhiyun #include <linux/interrupt.h>
19*4882a593Smuzhiyun #include <linux/delay.h>
20*4882a593Smuzhiyun #include <linux/of_device.h>
21*4882a593Smuzhiyun #include <linux/of.h>
22*4882a593Smuzhiyun #include <linux/bitops.h>
23*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
24*4882a593Smuzhiyun #include <linux/slab.h>
25*4882a593Smuzhiyun #include <linux/string.h>
26*4882a593Smuzhiyun #include <linux/iio/iio.h>
27*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
28*4882a593Smuzhiyun #include <linux/iio/buffer.h>
29*4882a593Smuzhiyun #include <linux/iio/trigger.h>
30*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
31*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define BMA180_DRV_NAME "bma180"
34*4882a593Smuzhiyun #define BMA180_IRQ_NAME "bma180_event"
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun enum chip_ids {
37*4882a593Smuzhiyun 	BMA023,
38*4882a593Smuzhiyun 	BMA150,
39*4882a593Smuzhiyun 	BMA180,
40*4882a593Smuzhiyun 	BMA250,
41*4882a593Smuzhiyun 	BMA254,
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun struct bma180_data;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun struct bma180_part_info {
47*4882a593Smuzhiyun 	u8 chip_id;
48*4882a593Smuzhiyun 	const struct iio_chan_spec *channels;
49*4882a593Smuzhiyun 	unsigned int num_channels;
50*4882a593Smuzhiyun 	const int *scale_table;
51*4882a593Smuzhiyun 	unsigned int num_scales;
52*4882a593Smuzhiyun 	const int *bw_table;
53*4882a593Smuzhiyun 	unsigned int num_bw;
54*4882a593Smuzhiyun 	int temp_offset;
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun 	u8 int_reset_reg, int_reset_mask;
57*4882a593Smuzhiyun 	u8 sleep_reg, sleep_mask;
58*4882a593Smuzhiyun 	u8 bw_reg, bw_mask, bw_offset;
59*4882a593Smuzhiyun 	u8 scale_reg, scale_mask;
60*4882a593Smuzhiyun 	u8 power_reg, power_mask, lowpower_val;
61*4882a593Smuzhiyun 	u8 int_enable_reg, int_enable_mask;
62*4882a593Smuzhiyun 	u8 int_map_reg, int_enable_dataready_int1_mask;
63*4882a593Smuzhiyun 	u8 softreset_reg, softreset_val;
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun 	int (*chip_config)(struct bma180_data *data);
66*4882a593Smuzhiyun 	void (*chip_disable)(struct bma180_data *data);
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun /* Register set */
70*4882a593Smuzhiyun #define BMA023_CTRL_REG0	0x0a
71*4882a593Smuzhiyun #define BMA023_CTRL_REG1	0x0b
72*4882a593Smuzhiyun #define BMA023_CTRL_REG2	0x14
73*4882a593Smuzhiyun #define BMA023_CTRL_REG3	0x15
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun #define BMA023_RANGE_MASK	GENMASK(4, 3) /* Range of accel values */
76*4882a593Smuzhiyun #define BMA023_BW_MASK		GENMASK(2, 0) /* Accel bandwidth */
77*4882a593Smuzhiyun #define BMA023_SLEEP		BIT(0)
78*4882a593Smuzhiyun #define BMA023_INT_RESET_MASK	BIT(6)
79*4882a593Smuzhiyun #define BMA023_NEW_DATA_INT	BIT(5) /* Intr every new accel data is ready */
80*4882a593Smuzhiyun #define BMA023_RESET_VAL	BIT(1)
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun #define BMA180_CHIP_ID		0x00 /* Need to distinguish BMA180 from other */
83*4882a593Smuzhiyun #define BMA180_ACC_X_LSB	0x02 /* First of 6 registers of accel data */
84*4882a593Smuzhiyun #define BMA180_TEMP		0x08
85*4882a593Smuzhiyun #define BMA180_CTRL_REG0	0x0d
86*4882a593Smuzhiyun #define BMA180_RESET		0x10
87*4882a593Smuzhiyun #define BMA180_BW_TCS		0x20
88*4882a593Smuzhiyun #define BMA180_CTRL_REG3	0x21
89*4882a593Smuzhiyun #define BMA180_TCO_Z		0x30
90*4882a593Smuzhiyun #define BMA180_OFFSET_LSB1	0x35
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun /* BMA180_CTRL_REG0 bits */
93*4882a593Smuzhiyun #define BMA180_DIS_WAKE_UP	BIT(0) /* Disable wake up mode */
94*4882a593Smuzhiyun #define BMA180_SLEEP		BIT(1) /* 1 - chip will sleep */
95*4882a593Smuzhiyun #define BMA180_EE_W		BIT(4) /* Unlock writing to addr from 0x20 */
96*4882a593Smuzhiyun #define BMA180_RESET_INT	BIT(6) /* Reset pending interrupts */
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun /* BMA180_CTRL_REG3 bits */
99*4882a593Smuzhiyun #define BMA180_NEW_DATA_INT	BIT(1) /* Intr every new accel data is ready */
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /* BMA180_OFFSET_LSB1 skipping mode bit */
102*4882a593Smuzhiyun #define BMA180_SMP_SKIP		BIT(0)
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun /* Bit masks for registers bit fields */
105*4882a593Smuzhiyun #define BMA180_RANGE		0x0e /* Range of measured accel values */
106*4882a593Smuzhiyun #define BMA180_BW		0xf0 /* Accel bandwidth */
107*4882a593Smuzhiyun #define BMA180_MODE_CONFIG	0x03 /* Config operation modes */
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun /* We have to write this value in reset register to do soft reset */
110*4882a593Smuzhiyun #define BMA180_RESET_VAL	0xb6
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun #define BMA023_ID_REG_VAL	0x02
113*4882a593Smuzhiyun #define BMA180_ID_REG_VAL	0x03
114*4882a593Smuzhiyun #define BMA250_ID_REG_VAL	0x03
115*4882a593Smuzhiyun #define BMA254_ID_REG_VAL	0xfa /* 250 decimal */
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun /* Chip power modes */
118*4882a593Smuzhiyun #define BMA180_LOW_POWER	0x03
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun #define BMA250_RANGE_REG	0x0f
121*4882a593Smuzhiyun #define BMA250_BW_REG		0x10
122*4882a593Smuzhiyun #define BMA250_POWER_REG	0x11
123*4882a593Smuzhiyun #define BMA250_RESET_REG	0x14
124*4882a593Smuzhiyun #define BMA250_INT_ENABLE_REG	0x17
125*4882a593Smuzhiyun #define BMA250_INT_MAP_REG	0x1a
126*4882a593Smuzhiyun #define BMA250_INT_RESET_REG	0x21
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun #define BMA250_RANGE_MASK	GENMASK(3, 0) /* Range of accel values */
129*4882a593Smuzhiyun #define BMA250_BW_MASK		GENMASK(4, 0) /* Accel bandwidth */
130*4882a593Smuzhiyun #define BMA250_BW_OFFSET	8
131*4882a593Smuzhiyun #define BMA250_SUSPEND_MASK	BIT(7) /* chip will sleep */
132*4882a593Smuzhiyun #define BMA250_LOWPOWER_MASK	BIT(6)
133*4882a593Smuzhiyun #define BMA250_DATA_INTEN_MASK	BIT(4)
134*4882a593Smuzhiyun #define BMA250_INT1_DATA_MASK	BIT(0)
135*4882a593Smuzhiyun #define BMA250_INT_RESET_MASK	BIT(7) /* Reset pending interrupts */
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun #define BMA254_RANGE_REG	0x0f
138*4882a593Smuzhiyun #define BMA254_BW_REG		0x10
139*4882a593Smuzhiyun #define BMA254_POWER_REG	0x11
140*4882a593Smuzhiyun #define BMA254_RESET_REG	0x14
141*4882a593Smuzhiyun #define BMA254_INT_ENABLE_REG	0x17
142*4882a593Smuzhiyun #define BMA254_INT_MAP_REG	0x1a
143*4882a593Smuzhiyun #define BMA254_INT_RESET_REG	0x21
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun #define BMA254_RANGE_MASK	GENMASK(3, 0) /* Range of accel values */
146*4882a593Smuzhiyun #define BMA254_BW_MASK		GENMASK(4, 0) /* Accel bandwidth */
147*4882a593Smuzhiyun #define BMA254_BW_OFFSET	8
148*4882a593Smuzhiyun #define BMA254_SUSPEND_MASK	BIT(7) /* chip will sleep */
149*4882a593Smuzhiyun #define BMA254_LOWPOWER_MASK	BIT(6)
150*4882a593Smuzhiyun #define BMA254_DATA_INTEN_MASK	BIT(4)
151*4882a593Smuzhiyun #define BMA254_INT2_DATA_MASK	BIT(7)
152*4882a593Smuzhiyun #define BMA254_INT1_DATA_MASK	BIT(0)
153*4882a593Smuzhiyun #define BMA254_INT_RESET_MASK	BIT(7) /* Reset pending interrupts */
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun struct bma180_data {
156*4882a593Smuzhiyun 	struct regulator *vdd_supply;
157*4882a593Smuzhiyun 	struct regulator *vddio_supply;
158*4882a593Smuzhiyun 	struct i2c_client *client;
159*4882a593Smuzhiyun 	struct iio_trigger *trig;
160*4882a593Smuzhiyun 	const struct bma180_part_info *part_info;
161*4882a593Smuzhiyun 	struct iio_mount_matrix orientation;
162*4882a593Smuzhiyun 	struct mutex mutex;
163*4882a593Smuzhiyun 	bool sleep_state;
164*4882a593Smuzhiyun 	int scale;
165*4882a593Smuzhiyun 	int bw;
166*4882a593Smuzhiyun 	bool pmode;
167*4882a593Smuzhiyun 	/* Ensure timestamp is naturally aligned */
168*4882a593Smuzhiyun 	struct {
169*4882a593Smuzhiyun 		s16 chan[4];
170*4882a593Smuzhiyun 		s64 timestamp __aligned(8);
171*4882a593Smuzhiyun 	} scan;
172*4882a593Smuzhiyun };
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun enum bma180_chan {
175*4882a593Smuzhiyun 	AXIS_X,
176*4882a593Smuzhiyun 	AXIS_Y,
177*4882a593Smuzhiyun 	AXIS_Z,
178*4882a593Smuzhiyun 	TEMP
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun static int bma023_bw_table[] = { 25, 50, 100, 190, 375, 750, 1500 }; /* Hz */
182*4882a593Smuzhiyun static int bma023_scale_table[] = { 2452, 4903, 9709, };
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun static int bma180_bw_table[] = { 10, 20, 40, 75, 150, 300 }; /* Hz */
185*4882a593Smuzhiyun static int bma180_scale_table[] = { 1275, 1863, 2452, 3727, 4903, 9709, 19417 };
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun static int bma25x_bw_table[] = { 8, 16, 31, 63, 125, 250 }; /* Hz */
188*4882a593Smuzhiyun static int bma25x_scale_table[] = { 0, 0, 0, 38344, 0, 76590, 0, 0, 153180, 0,
189*4882a593Smuzhiyun 	0, 0, 306458 };
190*4882a593Smuzhiyun 
bma180_get_data_reg(struct bma180_data * data,enum bma180_chan chan)191*4882a593Smuzhiyun static int bma180_get_data_reg(struct bma180_data *data, enum bma180_chan chan)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun 	int ret;
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	if (data->sleep_state)
196*4882a593Smuzhiyun 		return -EBUSY;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	switch (chan) {
199*4882a593Smuzhiyun 	case TEMP:
200*4882a593Smuzhiyun 		ret = i2c_smbus_read_byte_data(data->client, BMA180_TEMP);
201*4882a593Smuzhiyun 		if (ret < 0)
202*4882a593Smuzhiyun 			dev_err(&data->client->dev, "failed to read temp register\n");
203*4882a593Smuzhiyun 		break;
204*4882a593Smuzhiyun 	default:
205*4882a593Smuzhiyun 		ret = i2c_smbus_read_word_data(data->client,
206*4882a593Smuzhiyun 			BMA180_ACC_X_LSB + chan * 2);
207*4882a593Smuzhiyun 		if (ret < 0)
208*4882a593Smuzhiyun 			dev_err(&data->client->dev,
209*4882a593Smuzhiyun 				"failed to read accel_%c register\n",
210*4882a593Smuzhiyun 				'x' + chan);
211*4882a593Smuzhiyun 	}
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	return ret;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun 
bma180_set_bits(struct bma180_data * data,u8 reg,u8 mask,u8 val)216*4882a593Smuzhiyun static int bma180_set_bits(struct bma180_data *data, u8 reg, u8 mask, u8 val)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun 	int ret = i2c_smbus_read_byte_data(data->client, reg);
219*4882a593Smuzhiyun 	u8 reg_val = (ret & ~mask) | (val << (ffs(mask) - 1));
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	if (ret < 0)
222*4882a593Smuzhiyun 		return ret;
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	return i2c_smbus_write_byte_data(data->client, reg, reg_val);
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun 
bma180_reset_intr(struct bma180_data * data)227*4882a593Smuzhiyun static int bma180_reset_intr(struct bma180_data *data)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun 	int ret = bma180_set_bits(data, data->part_info->int_reset_reg,
230*4882a593Smuzhiyun 		data->part_info->int_reset_mask, 1);
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	if (ret)
233*4882a593Smuzhiyun 		dev_err(&data->client->dev, "failed to reset interrupt\n");
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	return ret;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun 
bma180_set_new_data_intr_state(struct bma180_data * data,bool state)238*4882a593Smuzhiyun static int bma180_set_new_data_intr_state(struct bma180_data *data, bool state)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun 	int ret = bma180_set_bits(data, data->part_info->int_enable_reg,
241*4882a593Smuzhiyun 			data->part_info->int_enable_mask, state);
242*4882a593Smuzhiyun 	if (ret)
243*4882a593Smuzhiyun 		goto err;
244*4882a593Smuzhiyun 	ret = bma180_reset_intr(data);
245*4882a593Smuzhiyun 	if (ret)
246*4882a593Smuzhiyun 		goto err;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	return 0;
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun err:
251*4882a593Smuzhiyun 	dev_err(&data->client->dev,
252*4882a593Smuzhiyun 		"failed to set new data interrupt state %d\n", state);
253*4882a593Smuzhiyun 	return ret;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun 
bma180_set_sleep_state(struct bma180_data * data,bool state)256*4882a593Smuzhiyun static int bma180_set_sleep_state(struct bma180_data *data, bool state)
257*4882a593Smuzhiyun {
258*4882a593Smuzhiyun 	int ret = bma180_set_bits(data, data->part_info->sleep_reg,
259*4882a593Smuzhiyun 		data->part_info->sleep_mask, state);
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	if (ret) {
262*4882a593Smuzhiyun 		dev_err(&data->client->dev,
263*4882a593Smuzhiyun 			"failed to set sleep state %d\n", state);
264*4882a593Smuzhiyun 		return ret;
265*4882a593Smuzhiyun 	}
266*4882a593Smuzhiyun 	data->sleep_state = state;
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	return 0;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun 
bma180_set_ee_writing_state(struct bma180_data * data,bool state)271*4882a593Smuzhiyun static int bma180_set_ee_writing_state(struct bma180_data *data, bool state)
272*4882a593Smuzhiyun {
273*4882a593Smuzhiyun 	int ret = bma180_set_bits(data, BMA180_CTRL_REG0, BMA180_EE_W, state);
274*4882a593Smuzhiyun 
275*4882a593Smuzhiyun 	if (ret)
276*4882a593Smuzhiyun 		dev_err(&data->client->dev,
277*4882a593Smuzhiyun 			"failed to set ee writing state %d\n", state);
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	return ret;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun 
bma180_set_bw(struct bma180_data * data,int val)282*4882a593Smuzhiyun static int bma180_set_bw(struct bma180_data *data, int val)
283*4882a593Smuzhiyun {
284*4882a593Smuzhiyun 	int ret, i;
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	if (data->sleep_state)
287*4882a593Smuzhiyun 		return -EBUSY;
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun 	for (i = 0; i < data->part_info->num_bw; ++i) {
290*4882a593Smuzhiyun 		if (data->part_info->bw_table[i] == val) {
291*4882a593Smuzhiyun 			ret = bma180_set_bits(data, data->part_info->bw_reg,
292*4882a593Smuzhiyun 				data->part_info->bw_mask,
293*4882a593Smuzhiyun 				i + data->part_info->bw_offset);
294*4882a593Smuzhiyun 			if (ret) {
295*4882a593Smuzhiyun 				dev_err(&data->client->dev,
296*4882a593Smuzhiyun 					"failed to set bandwidth\n");
297*4882a593Smuzhiyun 				return ret;
298*4882a593Smuzhiyun 			}
299*4882a593Smuzhiyun 			data->bw = val;
300*4882a593Smuzhiyun 			return 0;
301*4882a593Smuzhiyun 		}
302*4882a593Smuzhiyun 	}
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	return -EINVAL;
305*4882a593Smuzhiyun }
306*4882a593Smuzhiyun 
bma180_set_scale(struct bma180_data * data,int val)307*4882a593Smuzhiyun static int bma180_set_scale(struct bma180_data *data, int val)
308*4882a593Smuzhiyun {
309*4882a593Smuzhiyun 	int ret, i;
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	if (data->sleep_state)
312*4882a593Smuzhiyun 		return -EBUSY;
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun 	for (i = 0; i < data->part_info->num_scales; ++i)
315*4882a593Smuzhiyun 		if (data->part_info->scale_table[i] == val) {
316*4882a593Smuzhiyun 			ret = bma180_set_bits(data, data->part_info->scale_reg,
317*4882a593Smuzhiyun 				data->part_info->scale_mask, i);
318*4882a593Smuzhiyun 			if (ret) {
319*4882a593Smuzhiyun 				dev_err(&data->client->dev,
320*4882a593Smuzhiyun 					"failed to set scale\n");
321*4882a593Smuzhiyun 				return ret;
322*4882a593Smuzhiyun 			}
323*4882a593Smuzhiyun 			data->scale = val;
324*4882a593Smuzhiyun 			return 0;
325*4882a593Smuzhiyun 		}
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	return -EINVAL;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun 
bma180_set_pmode(struct bma180_data * data,bool mode)330*4882a593Smuzhiyun static int bma180_set_pmode(struct bma180_data *data, bool mode)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun 	u8 reg_val = mode ? data->part_info->lowpower_val : 0;
333*4882a593Smuzhiyun 	int ret = bma180_set_bits(data, data->part_info->power_reg,
334*4882a593Smuzhiyun 		data->part_info->power_mask, reg_val);
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	if (ret) {
337*4882a593Smuzhiyun 		dev_err(&data->client->dev, "failed to set power mode\n");
338*4882a593Smuzhiyun 		return ret;
339*4882a593Smuzhiyun 	}
340*4882a593Smuzhiyun 	data->pmode = mode;
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun 	return 0;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun 
bma180_soft_reset(struct bma180_data * data)345*4882a593Smuzhiyun static int bma180_soft_reset(struct bma180_data *data)
346*4882a593Smuzhiyun {
347*4882a593Smuzhiyun 	int ret = i2c_smbus_write_byte_data(data->client,
348*4882a593Smuzhiyun 		data->part_info->softreset_reg,
349*4882a593Smuzhiyun 		data->part_info->softreset_val);
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 	if (ret)
352*4882a593Smuzhiyun 		dev_err(&data->client->dev, "failed to reset the chip\n");
353*4882a593Smuzhiyun 
354*4882a593Smuzhiyun 	return ret;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun 
bma180_chip_init(struct bma180_data * data)357*4882a593Smuzhiyun static int bma180_chip_init(struct bma180_data *data)
358*4882a593Smuzhiyun {
359*4882a593Smuzhiyun 	/* Try to read chip_id register. It must return 0x03. */
360*4882a593Smuzhiyun 	int ret = i2c_smbus_read_byte_data(data->client, BMA180_CHIP_ID);
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	if (ret < 0)
363*4882a593Smuzhiyun 		return ret;
364*4882a593Smuzhiyun 	if (ret != data->part_info->chip_id) {
365*4882a593Smuzhiyun 		dev_err(&data->client->dev, "wrong chip ID %d expected %d\n",
366*4882a593Smuzhiyun 			ret, data->part_info->chip_id);
367*4882a593Smuzhiyun 		return -ENODEV;
368*4882a593Smuzhiyun 	}
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun 	ret = bma180_soft_reset(data);
371*4882a593Smuzhiyun 	if (ret)
372*4882a593Smuzhiyun 		return ret;
373*4882a593Smuzhiyun 	/*
374*4882a593Smuzhiyun 	 * No serial transaction should occur within minimum 10 us
375*4882a593Smuzhiyun 	 * after soft_reset command
376*4882a593Smuzhiyun 	 */
377*4882a593Smuzhiyun 	msleep(20);
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	return bma180_set_new_data_intr_state(data, false);
380*4882a593Smuzhiyun }
381*4882a593Smuzhiyun 
bma023_chip_config(struct bma180_data * data)382*4882a593Smuzhiyun static int bma023_chip_config(struct bma180_data *data)
383*4882a593Smuzhiyun {
384*4882a593Smuzhiyun 	int ret = bma180_chip_init(data);
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 	if (ret)
387*4882a593Smuzhiyun 		goto err;
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun 	ret = bma180_set_bw(data, 50); /* 50 Hz */
390*4882a593Smuzhiyun 	if (ret)
391*4882a593Smuzhiyun 		goto err;
392*4882a593Smuzhiyun 	ret = bma180_set_scale(data, 2452); /* 2 G */
393*4882a593Smuzhiyun 	if (ret)
394*4882a593Smuzhiyun 		goto err;
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	return 0;
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun err:
399*4882a593Smuzhiyun 	dev_err(&data->client->dev, "failed to config the chip\n");
400*4882a593Smuzhiyun 	return ret;
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun 
bma180_chip_config(struct bma180_data * data)403*4882a593Smuzhiyun static int bma180_chip_config(struct bma180_data *data)
404*4882a593Smuzhiyun {
405*4882a593Smuzhiyun 	int ret = bma180_chip_init(data);
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	if (ret)
408*4882a593Smuzhiyun 		goto err;
409*4882a593Smuzhiyun 	ret = bma180_set_pmode(data, false);
410*4882a593Smuzhiyun 	if (ret)
411*4882a593Smuzhiyun 		goto err;
412*4882a593Smuzhiyun 	ret = bma180_set_bits(data, BMA180_CTRL_REG0, BMA180_DIS_WAKE_UP, 1);
413*4882a593Smuzhiyun 	if (ret)
414*4882a593Smuzhiyun 		goto err;
415*4882a593Smuzhiyun 	ret = bma180_set_ee_writing_state(data, true);
416*4882a593Smuzhiyun 	if (ret)
417*4882a593Smuzhiyun 		goto err;
418*4882a593Smuzhiyun 	ret = bma180_set_bits(data, BMA180_OFFSET_LSB1, BMA180_SMP_SKIP, 1);
419*4882a593Smuzhiyun 	if (ret)
420*4882a593Smuzhiyun 		goto err;
421*4882a593Smuzhiyun 	ret = bma180_set_bw(data, 20); /* 20 Hz */
422*4882a593Smuzhiyun 	if (ret)
423*4882a593Smuzhiyun 		goto err;
424*4882a593Smuzhiyun 	ret = bma180_set_scale(data, 2452); /* 2 G */
425*4882a593Smuzhiyun 	if (ret)
426*4882a593Smuzhiyun 		goto err;
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun 	return 0;
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun err:
431*4882a593Smuzhiyun 	dev_err(&data->client->dev, "failed to config the chip\n");
432*4882a593Smuzhiyun 	return ret;
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun 
bma25x_chip_config(struct bma180_data * data)435*4882a593Smuzhiyun static int bma25x_chip_config(struct bma180_data *data)
436*4882a593Smuzhiyun {
437*4882a593Smuzhiyun 	int ret = bma180_chip_init(data);
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun 	if (ret)
440*4882a593Smuzhiyun 		goto err;
441*4882a593Smuzhiyun 	ret = bma180_set_pmode(data, false);
442*4882a593Smuzhiyun 	if (ret)
443*4882a593Smuzhiyun 		goto err;
444*4882a593Smuzhiyun 	ret = bma180_set_bw(data, 16); /* 16 Hz */
445*4882a593Smuzhiyun 	if (ret)
446*4882a593Smuzhiyun 		goto err;
447*4882a593Smuzhiyun 	ret = bma180_set_scale(data, 38344); /* 2 G */
448*4882a593Smuzhiyun 	if (ret)
449*4882a593Smuzhiyun 		goto err;
450*4882a593Smuzhiyun 	/*
451*4882a593Smuzhiyun 	 * This enables dataready interrupt on the INT1 pin
452*4882a593Smuzhiyun 	 * FIXME: support using the INT2 pin
453*4882a593Smuzhiyun 	 */
454*4882a593Smuzhiyun 	ret = bma180_set_bits(data, data->part_info->int_map_reg,
455*4882a593Smuzhiyun 		data->part_info->int_enable_dataready_int1_mask, 1);
456*4882a593Smuzhiyun 	if (ret)
457*4882a593Smuzhiyun 		goto err;
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	return 0;
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun err:
462*4882a593Smuzhiyun 	dev_err(&data->client->dev, "failed to config the chip\n");
463*4882a593Smuzhiyun 	return ret;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun 
bma023_chip_disable(struct bma180_data * data)466*4882a593Smuzhiyun static void bma023_chip_disable(struct bma180_data *data)
467*4882a593Smuzhiyun {
468*4882a593Smuzhiyun 	if (bma180_set_sleep_state(data, true))
469*4882a593Smuzhiyun 		goto err;
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	return;
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun err:
474*4882a593Smuzhiyun 	dev_err(&data->client->dev, "failed to disable the chip\n");
475*4882a593Smuzhiyun }
476*4882a593Smuzhiyun 
bma180_chip_disable(struct bma180_data * data)477*4882a593Smuzhiyun static void bma180_chip_disable(struct bma180_data *data)
478*4882a593Smuzhiyun {
479*4882a593Smuzhiyun 	if (bma180_set_new_data_intr_state(data, false))
480*4882a593Smuzhiyun 		goto err;
481*4882a593Smuzhiyun 	if (bma180_set_ee_writing_state(data, false))
482*4882a593Smuzhiyun 		goto err;
483*4882a593Smuzhiyun 	if (bma180_set_sleep_state(data, true))
484*4882a593Smuzhiyun 		goto err;
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 	return;
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun err:
489*4882a593Smuzhiyun 	dev_err(&data->client->dev, "failed to disable the chip\n");
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun 
bma25x_chip_disable(struct bma180_data * data)492*4882a593Smuzhiyun static void bma25x_chip_disable(struct bma180_data *data)
493*4882a593Smuzhiyun {
494*4882a593Smuzhiyun 	if (bma180_set_new_data_intr_state(data, false))
495*4882a593Smuzhiyun 		goto err;
496*4882a593Smuzhiyun 	if (bma180_set_sleep_state(data, true))
497*4882a593Smuzhiyun 		goto err;
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 	return;
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun err:
502*4882a593Smuzhiyun 	dev_err(&data->client->dev, "failed to disable the chip\n");
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun 
bma180_show_avail(char * buf,const int * vals,unsigned int n,bool micros)505*4882a593Smuzhiyun static ssize_t bma180_show_avail(char *buf, const int *vals, unsigned int n,
506*4882a593Smuzhiyun 				 bool micros)
507*4882a593Smuzhiyun {
508*4882a593Smuzhiyun 	size_t len = 0;
509*4882a593Smuzhiyun 	int i;
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun 	for (i = 0; i < n; i++) {
512*4882a593Smuzhiyun 		if (!vals[i])
513*4882a593Smuzhiyun 			continue;
514*4882a593Smuzhiyun 		len += scnprintf(buf + len, PAGE_SIZE - len,
515*4882a593Smuzhiyun 			micros ? "0.%06d " : "%d ", vals[i]);
516*4882a593Smuzhiyun 	}
517*4882a593Smuzhiyun 	buf[len - 1] = '\n';
518*4882a593Smuzhiyun 
519*4882a593Smuzhiyun 	return len;
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun 
bma180_show_filter_freq_avail(struct device * dev,struct device_attribute * attr,char * buf)522*4882a593Smuzhiyun static ssize_t bma180_show_filter_freq_avail(struct device *dev,
523*4882a593Smuzhiyun 				struct device_attribute *attr, char *buf)
524*4882a593Smuzhiyun {
525*4882a593Smuzhiyun 	struct bma180_data *data = iio_priv(dev_to_iio_dev(dev));
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun 	return bma180_show_avail(buf, data->part_info->bw_table,
528*4882a593Smuzhiyun 		data->part_info->num_bw, false);
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun 
bma180_show_scale_avail(struct device * dev,struct device_attribute * attr,char * buf)531*4882a593Smuzhiyun static ssize_t bma180_show_scale_avail(struct device *dev,
532*4882a593Smuzhiyun 				struct device_attribute *attr, char *buf)
533*4882a593Smuzhiyun {
534*4882a593Smuzhiyun 	struct bma180_data *data = iio_priv(dev_to_iio_dev(dev));
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun 	return bma180_show_avail(buf, data->part_info->scale_table,
537*4882a593Smuzhiyun 		data->part_info->num_scales, true);
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available,
541*4882a593Smuzhiyun 	S_IRUGO, bma180_show_filter_freq_avail, NULL, 0);
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun static IIO_DEVICE_ATTR(in_accel_scale_available,
544*4882a593Smuzhiyun 	S_IRUGO, bma180_show_scale_avail, NULL, 0);
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun static struct attribute *bma180_attributes[] = {
547*4882a593Smuzhiyun 	&iio_dev_attr_in_accel_filter_low_pass_3db_frequency_available.
548*4882a593Smuzhiyun 		dev_attr.attr,
549*4882a593Smuzhiyun 	&iio_dev_attr_in_accel_scale_available.dev_attr.attr,
550*4882a593Smuzhiyun 	NULL,
551*4882a593Smuzhiyun };
552*4882a593Smuzhiyun 
553*4882a593Smuzhiyun static const struct attribute_group bma180_attrs_group = {
554*4882a593Smuzhiyun 	.attrs = bma180_attributes,
555*4882a593Smuzhiyun };
556*4882a593Smuzhiyun 
bma180_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)557*4882a593Smuzhiyun static int bma180_read_raw(struct iio_dev *indio_dev,
558*4882a593Smuzhiyun 		struct iio_chan_spec const *chan, int *val, int *val2,
559*4882a593Smuzhiyun 		long mask)
560*4882a593Smuzhiyun {
561*4882a593Smuzhiyun 	struct bma180_data *data = iio_priv(indio_dev);
562*4882a593Smuzhiyun 	int ret;
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun 	switch (mask) {
565*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
566*4882a593Smuzhiyun 		ret = iio_device_claim_direct_mode(indio_dev);
567*4882a593Smuzhiyun 		if (ret)
568*4882a593Smuzhiyun 			return ret;
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 		mutex_lock(&data->mutex);
571*4882a593Smuzhiyun 		ret = bma180_get_data_reg(data, chan->scan_index);
572*4882a593Smuzhiyun 		mutex_unlock(&data->mutex);
573*4882a593Smuzhiyun 		iio_device_release_direct_mode(indio_dev);
574*4882a593Smuzhiyun 		if (ret < 0)
575*4882a593Smuzhiyun 			return ret;
576*4882a593Smuzhiyun 		if (chan->scan_type.sign == 's') {
577*4882a593Smuzhiyun 			*val = sign_extend32(ret >> chan->scan_type.shift,
578*4882a593Smuzhiyun 				chan->scan_type.realbits - 1);
579*4882a593Smuzhiyun 		} else {
580*4882a593Smuzhiyun 			*val = ret;
581*4882a593Smuzhiyun 		}
582*4882a593Smuzhiyun 		return IIO_VAL_INT;
583*4882a593Smuzhiyun 	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
584*4882a593Smuzhiyun 		*val = data->bw;
585*4882a593Smuzhiyun 		return IIO_VAL_INT;
586*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
587*4882a593Smuzhiyun 		switch (chan->type) {
588*4882a593Smuzhiyun 		case IIO_ACCEL:
589*4882a593Smuzhiyun 			*val = 0;
590*4882a593Smuzhiyun 			*val2 = data->scale;
591*4882a593Smuzhiyun 			return IIO_VAL_INT_PLUS_MICRO;
592*4882a593Smuzhiyun 		case IIO_TEMP:
593*4882a593Smuzhiyun 			*val = 500;
594*4882a593Smuzhiyun 			return IIO_VAL_INT;
595*4882a593Smuzhiyun 		default:
596*4882a593Smuzhiyun 			return -EINVAL;
597*4882a593Smuzhiyun 		}
598*4882a593Smuzhiyun 	case IIO_CHAN_INFO_OFFSET:
599*4882a593Smuzhiyun 		*val = data->part_info->temp_offset;
600*4882a593Smuzhiyun 		return IIO_VAL_INT;
601*4882a593Smuzhiyun 	default:
602*4882a593Smuzhiyun 		return -EINVAL;
603*4882a593Smuzhiyun 	}
604*4882a593Smuzhiyun }
605*4882a593Smuzhiyun 
bma180_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)606*4882a593Smuzhiyun static int bma180_write_raw(struct iio_dev *indio_dev,
607*4882a593Smuzhiyun 		struct iio_chan_spec const *chan, int val, int val2, long mask)
608*4882a593Smuzhiyun {
609*4882a593Smuzhiyun 	struct bma180_data *data = iio_priv(indio_dev);
610*4882a593Smuzhiyun 	int ret;
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun 	switch (mask) {
613*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
614*4882a593Smuzhiyun 		if (val)
615*4882a593Smuzhiyun 			return -EINVAL;
616*4882a593Smuzhiyun 		mutex_lock(&data->mutex);
617*4882a593Smuzhiyun 		ret = bma180_set_scale(data, val2);
618*4882a593Smuzhiyun 		mutex_unlock(&data->mutex);
619*4882a593Smuzhiyun 		return ret;
620*4882a593Smuzhiyun 	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
621*4882a593Smuzhiyun 		if (val2)
622*4882a593Smuzhiyun 			return -EINVAL;
623*4882a593Smuzhiyun 		mutex_lock(&data->mutex);
624*4882a593Smuzhiyun 		ret = bma180_set_bw(data, val);
625*4882a593Smuzhiyun 		mutex_unlock(&data->mutex);
626*4882a593Smuzhiyun 		return ret;
627*4882a593Smuzhiyun 	default:
628*4882a593Smuzhiyun 		return -EINVAL;
629*4882a593Smuzhiyun 	}
630*4882a593Smuzhiyun }
631*4882a593Smuzhiyun 
632*4882a593Smuzhiyun static const struct iio_info bma180_info = {
633*4882a593Smuzhiyun 	.attrs			= &bma180_attrs_group,
634*4882a593Smuzhiyun 	.read_raw		= bma180_read_raw,
635*4882a593Smuzhiyun 	.write_raw		= bma180_write_raw,
636*4882a593Smuzhiyun };
637*4882a593Smuzhiyun 
638*4882a593Smuzhiyun static const char * const bma180_power_modes[] = { "low_noise", "low_power" };
639*4882a593Smuzhiyun 
bma180_get_power_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)640*4882a593Smuzhiyun static int bma180_get_power_mode(struct iio_dev *indio_dev,
641*4882a593Smuzhiyun 		const struct iio_chan_spec *chan)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun 	struct bma180_data *data = iio_priv(indio_dev);
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	return data->pmode;
646*4882a593Smuzhiyun }
647*4882a593Smuzhiyun 
bma180_set_power_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)648*4882a593Smuzhiyun static int bma180_set_power_mode(struct iio_dev *indio_dev,
649*4882a593Smuzhiyun 		const struct iio_chan_spec *chan, unsigned int mode)
650*4882a593Smuzhiyun {
651*4882a593Smuzhiyun 	struct bma180_data *data = iio_priv(indio_dev);
652*4882a593Smuzhiyun 	int ret;
653*4882a593Smuzhiyun 
654*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
655*4882a593Smuzhiyun 	ret = bma180_set_pmode(data, mode);
656*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
657*4882a593Smuzhiyun 
658*4882a593Smuzhiyun 	return ret;
659*4882a593Smuzhiyun }
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun static const struct iio_mount_matrix *
bma180_accel_get_mount_matrix(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)662*4882a593Smuzhiyun bma180_accel_get_mount_matrix(const struct iio_dev *indio_dev,
663*4882a593Smuzhiyun 				const struct iio_chan_spec *chan)
664*4882a593Smuzhiyun {
665*4882a593Smuzhiyun 	struct bma180_data *data = iio_priv(indio_dev);
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun 	return &data->orientation;
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun static const struct iio_enum bma180_power_mode_enum = {
671*4882a593Smuzhiyun 	.items = bma180_power_modes,
672*4882a593Smuzhiyun 	.num_items = ARRAY_SIZE(bma180_power_modes),
673*4882a593Smuzhiyun 	.get = bma180_get_power_mode,
674*4882a593Smuzhiyun 	.set = bma180_set_power_mode,
675*4882a593Smuzhiyun };
676*4882a593Smuzhiyun 
677*4882a593Smuzhiyun static const struct iio_chan_spec_ext_info bma023_ext_info[] = {
678*4882a593Smuzhiyun 	IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bma180_accel_get_mount_matrix),
679*4882a593Smuzhiyun 	{ }
680*4882a593Smuzhiyun };
681*4882a593Smuzhiyun 
682*4882a593Smuzhiyun static const struct iio_chan_spec_ext_info bma180_ext_info[] = {
683*4882a593Smuzhiyun 	IIO_ENUM("power_mode", IIO_SHARED_BY_TYPE, &bma180_power_mode_enum),
684*4882a593Smuzhiyun 	IIO_ENUM_AVAILABLE("power_mode", &bma180_power_mode_enum),
685*4882a593Smuzhiyun 	IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bma180_accel_get_mount_matrix),
686*4882a593Smuzhiyun 	{ }
687*4882a593Smuzhiyun };
688*4882a593Smuzhiyun 
689*4882a593Smuzhiyun #define BMA023_ACC_CHANNEL(_axis, _bits) {				\
690*4882a593Smuzhiyun 	.type = IIO_ACCEL,						\
691*4882a593Smuzhiyun 	.modified = 1,							\
692*4882a593Smuzhiyun 	.channel2 = IIO_MOD_##_axis,					\
693*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\
694*4882a593Smuzhiyun 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |		\
695*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),	\
696*4882a593Smuzhiyun 	.scan_index = AXIS_##_axis,					\
697*4882a593Smuzhiyun 	.scan_type = {							\
698*4882a593Smuzhiyun 		.sign = 's',						\
699*4882a593Smuzhiyun 		.realbits = _bits,					\
700*4882a593Smuzhiyun 		.storagebits = 16,					\
701*4882a593Smuzhiyun 		.shift = 16 - _bits,					\
702*4882a593Smuzhiyun 	},								\
703*4882a593Smuzhiyun 	.ext_info = bma023_ext_info,					\
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun #define BMA150_TEMP_CHANNEL {						\
707*4882a593Smuzhiyun 	.type = IIO_TEMP,						\
708*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |			\
709*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET),	\
710*4882a593Smuzhiyun 	.scan_index = TEMP,						\
711*4882a593Smuzhiyun 	.scan_type = {							\
712*4882a593Smuzhiyun 		.sign = 'u',						\
713*4882a593Smuzhiyun 		.realbits = 8,						\
714*4882a593Smuzhiyun 		.storagebits = 16,					\
715*4882a593Smuzhiyun 	},								\
716*4882a593Smuzhiyun }
717*4882a593Smuzhiyun 
718*4882a593Smuzhiyun #define BMA180_ACC_CHANNEL(_axis, _bits) {				\
719*4882a593Smuzhiyun 	.type = IIO_ACCEL,						\
720*4882a593Smuzhiyun 	.modified = 1,							\
721*4882a593Smuzhiyun 	.channel2 = IIO_MOD_##_axis,					\
722*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\
723*4882a593Smuzhiyun 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |		\
724*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),	\
725*4882a593Smuzhiyun 	.scan_index = AXIS_##_axis,					\
726*4882a593Smuzhiyun 	.scan_type = {							\
727*4882a593Smuzhiyun 		.sign = 's',						\
728*4882a593Smuzhiyun 		.realbits = _bits,					\
729*4882a593Smuzhiyun 		.storagebits = 16,					\
730*4882a593Smuzhiyun 		.shift = 16 - _bits,					\
731*4882a593Smuzhiyun 	},								\
732*4882a593Smuzhiyun 	.ext_info = bma180_ext_info,					\
733*4882a593Smuzhiyun }
734*4882a593Smuzhiyun 
735*4882a593Smuzhiyun #define BMA180_TEMP_CHANNEL {						\
736*4882a593Smuzhiyun 	.type = IIO_TEMP,						\
737*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |			\
738*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET),	\
739*4882a593Smuzhiyun 	.scan_index = TEMP,						\
740*4882a593Smuzhiyun 	.scan_type = {							\
741*4882a593Smuzhiyun 		.sign = 's',						\
742*4882a593Smuzhiyun 		.realbits = 8,						\
743*4882a593Smuzhiyun 		.storagebits = 16,					\
744*4882a593Smuzhiyun 	},								\
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun 
747*4882a593Smuzhiyun static const struct iio_chan_spec bma023_channels[] = {
748*4882a593Smuzhiyun 	BMA023_ACC_CHANNEL(X, 10),
749*4882a593Smuzhiyun 	BMA023_ACC_CHANNEL(Y, 10),
750*4882a593Smuzhiyun 	BMA023_ACC_CHANNEL(Z, 10),
751*4882a593Smuzhiyun 	IIO_CHAN_SOFT_TIMESTAMP(4),
752*4882a593Smuzhiyun };
753*4882a593Smuzhiyun 
754*4882a593Smuzhiyun static const struct iio_chan_spec bma150_channels[] = {
755*4882a593Smuzhiyun 	BMA023_ACC_CHANNEL(X, 10),
756*4882a593Smuzhiyun 	BMA023_ACC_CHANNEL(Y, 10),
757*4882a593Smuzhiyun 	BMA023_ACC_CHANNEL(Z, 10),
758*4882a593Smuzhiyun 	BMA150_TEMP_CHANNEL,
759*4882a593Smuzhiyun 	IIO_CHAN_SOFT_TIMESTAMP(4),
760*4882a593Smuzhiyun };
761*4882a593Smuzhiyun 
762*4882a593Smuzhiyun static const struct iio_chan_spec bma180_channels[] = {
763*4882a593Smuzhiyun 	BMA180_ACC_CHANNEL(X, 14),
764*4882a593Smuzhiyun 	BMA180_ACC_CHANNEL(Y, 14),
765*4882a593Smuzhiyun 	BMA180_ACC_CHANNEL(Z, 14),
766*4882a593Smuzhiyun 	BMA180_TEMP_CHANNEL,
767*4882a593Smuzhiyun 	IIO_CHAN_SOFT_TIMESTAMP(4),
768*4882a593Smuzhiyun };
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun static const struct iio_chan_spec bma250_channels[] = {
771*4882a593Smuzhiyun 	BMA180_ACC_CHANNEL(X, 10),
772*4882a593Smuzhiyun 	BMA180_ACC_CHANNEL(Y, 10),
773*4882a593Smuzhiyun 	BMA180_ACC_CHANNEL(Z, 10),
774*4882a593Smuzhiyun 	BMA180_TEMP_CHANNEL,
775*4882a593Smuzhiyun 	IIO_CHAN_SOFT_TIMESTAMP(4),
776*4882a593Smuzhiyun };
777*4882a593Smuzhiyun 
778*4882a593Smuzhiyun static const struct iio_chan_spec bma254_channels[] = {
779*4882a593Smuzhiyun 	BMA180_ACC_CHANNEL(X, 12),
780*4882a593Smuzhiyun 	BMA180_ACC_CHANNEL(Y, 12),
781*4882a593Smuzhiyun 	BMA180_ACC_CHANNEL(Z, 12),
782*4882a593Smuzhiyun 	BMA180_TEMP_CHANNEL,
783*4882a593Smuzhiyun 	IIO_CHAN_SOFT_TIMESTAMP(4),
784*4882a593Smuzhiyun };
785*4882a593Smuzhiyun 
786*4882a593Smuzhiyun static const struct bma180_part_info bma180_part_info[] = {
787*4882a593Smuzhiyun 	[BMA023] = {
788*4882a593Smuzhiyun 		.chip_id = BMA023_ID_REG_VAL,
789*4882a593Smuzhiyun 		.channels = bma023_channels,
790*4882a593Smuzhiyun 		.num_channels = ARRAY_SIZE(bma023_channels),
791*4882a593Smuzhiyun 		.scale_table = bma023_scale_table,
792*4882a593Smuzhiyun 		.num_scales = ARRAY_SIZE(bma023_scale_table),
793*4882a593Smuzhiyun 		.bw_table = bma023_bw_table,
794*4882a593Smuzhiyun 		.num_bw = ARRAY_SIZE(bma023_bw_table),
795*4882a593Smuzhiyun 		/* No temperature channel */
796*4882a593Smuzhiyun 		.temp_offset = 0,
797*4882a593Smuzhiyun 		.int_reset_reg = BMA023_CTRL_REG0,
798*4882a593Smuzhiyun 		.int_reset_mask = BMA023_INT_RESET_MASK,
799*4882a593Smuzhiyun 		.sleep_reg = BMA023_CTRL_REG0,
800*4882a593Smuzhiyun 		.sleep_mask = BMA023_SLEEP,
801*4882a593Smuzhiyun 		.bw_reg = BMA023_CTRL_REG2,
802*4882a593Smuzhiyun 		.bw_mask = BMA023_BW_MASK,
803*4882a593Smuzhiyun 		.scale_reg = BMA023_CTRL_REG2,
804*4882a593Smuzhiyun 		.scale_mask = BMA023_RANGE_MASK,
805*4882a593Smuzhiyun 		/* No power mode on bma023 */
806*4882a593Smuzhiyun 		.power_reg = 0,
807*4882a593Smuzhiyun 		.power_mask = 0,
808*4882a593Smuzhiyun 		.lowpower_val = 0,
809*4882a593Smuzhiyun 		.int_enable_reg = BMA023_CTRL_REG3,
810*4882a593Smuzhiyun 		.int_enable_mask = BMA023_NEW_DATA_INT,
811*4882a593Smuzhiyun 		.softreset_reg = BMA023_CTRL_REG0,
812*4882a593Smuzhiyun 		.softreset_val = BMA023_RESET_VAL,
813*4882a593Smuzhiyun 		.chip_config = bma023_chip_config,
814*4882a593Smuzhiyun 		.chip_disable = bma023_chip_disable,
815*4882a593Smuzhiyun 	},
816*4882a593Smuzhiyun 	[BMA150] = {
817*4882a593Smuzhiyun 		.chip_id = BMA023_ID_REG_VAL,
818*4882a593Smuzhiyun 		.channels = bma150_channels,
819*4882a593Smuzhiyun 		.num_channels = ARRAY_SIZE(bma150_channels),
820*4882a593Smuzhiyun 		.scale_table = bma023_scale_table,
821*4882a593Smuzhiyun 		.num_scales = ARRAY_SIZE(bma023_scale_table),
822*4882a593Smuzhiyun 		.bw_table = bma023_bw_table,
823*4882a593Smuzhiyun 		.num_bw = ARRAY_SIZE(bma023_bw_table),
824*4882a593Smuzhiyun 		.temp_offset = -60, /* 0 LSB @ -30 degree C */
825*4882a593Smuzhiyun 		.int_reset_reg = BMA023_CTRL_REG0,
826*4882a593Smuzhiyun 		.int_reset_mask = BMA023_INT_RESET_MASK,
827*4882a593Smuzhiyun 		.sleep_reg = BMA023_CTRL_REG0,
828*4882a593Smuzhiyun 		.sleep_mask = BMA023_SLEEP,
829*4882a593Smuzhiyun 		.bw_reg = BMA023_CTRL_REG2,
830*4882a593Smuzhiyun 		.bw_mask = BMA023_BW_MASK,
831*4882a593Smuzhiyun 		.scale_reg = BMA023_CTRL_REG2,
832*4882a593Smuzhiyun 		.scale_mask = BMA023_RANGE_MASK,
833*4882a593Smuzhiyun 		/* No power mode on bma150 */
834*4882a593Smuzhiyun 		.power_reg = 0,
835*4882a593Smuzhiyun 		.power_mask = 0,
836*4882a593Smuzhiyun 		.lowpower_val = 0,
837*4882a593Smuzhiyun 		.int_enable_reg = BMA023_CTRL_REG3,
838*4882a593Smuzhiyun 		.int_enable_mask = BMA023_NEW_DATA_INT,
839*4882a593Smuzhiyun 		.softreset_reg = BMA023_CTRL_REG0,
840*4882a593Smuzhiyun 		.softreset_val = BMA023_RESET_VAL,
841*4882a593Smuzhiyun 		.chip_config = bma023_chip_config,
842*4882a593Smuzhiyun 		.chip_disable = bma023_chip_disable,
843*4882a593Smuzhiyun 	},
844*4882a593Smuzhiyun 	[BMA180] = {
845*4882a593Smuzhiyun 		.chip_id = BMA180_ID_REG_VAL,
846*4882a593Smuzhiyun 		.channels = bma180_channels,
847*4882a593Smuzhiyun 		.num_channels = ARRAY_SIZE(bma180_channels),
848*4882a593Smuzhiyun 		.scale_table = bma180_scale_table,
849*4882a593Smuzhiyun 		.num_scales = ARRAY_SIZE(bma180_scale_table),
850*4882a593Smuzhiyun 		.bw_table = bma180_bw_table,
851*4882a593Smuzhiyun 		.num_bw = ARRAY_SIZE(bma180_bw_table),
852*4882a593Smuzhiyun 		.temp_offset = 48, /* 0 LSB @ 24 degree C */
853*4882a593Smuzhiyun 		.int_reset_reg = BMA180_CTRL_REG0,
854*4882a593Smuzhiyun 		.int_reset_mask = BMA180_RESET_INT,
855*4882a593Smuzhiyun 		.sleep_reg = BMA180_CTRL_REG0,
856*4882a593Smuzhiyun 		.sleep_mask = BMA180_SLEEP,
857*4882a593Smuzhiyun 		.bw_reg = BMA180_BW_TCS,
858*4882a593Smuzhiyun 		.bw_mask = BMA180_BW,
859*4882a593Smuzhiyun 		.scale_reg = BMA180_OFFSET_LSB1,
860*4882a593Smuzhiyun 		.scale_mask = BMA180_RANGE,
861*4882a593Smuzhiyun 		.power_reg = BMA180_TCO_Z,
862*4882a593Smuzhiyun 		.power_mask = BMA180_MODE_CONFIG,
863*4882a593Smuzhiyun 		.lowpower_val = BMA180_LOW_POWER,
864*4882a593Smuzhiyun 		.int_enable_reg = BMA180_CTRL_REG3,
865*4882a593Smuzhiyun 		.int_enable_mask = BMA180_NEW_DATA_INT,
866*4882a593Smuzhiyun 		.softreset_reg = BMA180_RESET,
867*4882a593Smuzhiyun 		.softreset_val = BMA180_RESET_VAL,
868*4882a593Smuzhiyun 		.chip_config = bma180_chip_config,
869*4882a593Smuzhiyun 		.chip_disable = bma180_chip_disable,
870*4882a593Smuzhiyun 	},
871*4882a593Smuzhiyun 	[BMA250] = {
872*4882a593Smuzhiyun 		.chip_id = BMA250_ID_REG_VAL,
873*4882a593Smuzhiyun 		.channels = bma250_channels,
874*4882a593Smuzhiyun 		.num_channels = ARRAY_SIZE(bma250_channels),
875*4882a593Smuzhiyun 		.scale_table = bma25x_scale_table,
876*4882a593Smuzhiyun 		.num_scales = ARRAY_SIZE(bma25x_scale_table),
877*4882a593Smuzhiyun 		.bw_table = bma25x_bw_table,
878*4882a593Smuzhiyun 		.num_bw = ARRAY_SIZE(bma25x_bw_table),
879*4882a593Smuzhiyun 		.temp_offset = 48, /* 0 LSB @ 24 degree C */
880*4882a593Smuzhiyun 		.int_reset_reg = BMA250_INT_RESET_REG,
881*4882a593Smuzhiyun 		.int_reset_mask = BMA250_INT_RESET_MASK,
882*4882a593Smuzhiyun 		.sleep_reg = BMA250_POWER_REG,
883*4882a593Smuzhiyun 		.sleep_mask = BMA250_SUSPEND_MASK,
884*4882a593Smuzhiyun 		.bw_reg = BMA250_BW_REG,
885*4882a593Smuzhiyun 		.bw_mask = BMA250_BW_MASK,
886*4882a593Smuzhiyun 		.bw_offset = BMA250_BW_OFFSET,
887*4882a593Smuzhiyun 		.scale_reg = BMA250_RANGE_REG,
888*4882a593Smuzhiyun 		.scale_mask = BMA250_RANGE_MASK,
889*4882a593Smuzhiyun 		.power_reg = BMA250_POWER_REG,
890*4882a593Smuzhiyun 		.power_mask = BMA250_LOWPOWER_MASK,
891*4882a593Smuzhiyun 		.lowpower_val = 1,
892*4882a593Smuzhiyun 		.int_enable_reg = BMA250_INT_ENABLE_REG,
893*4882a593Smuzhiyun 		.int_enable_mask = BMA250_DATA_INTEN_MASK,
894*4882a593Smuzhiyun 		.int_map_reg = BMA250_INT_MAP_REG,
895*4882a593Smuzhiyun 		.int_enable_dataready_int1_mask = BMA250_INT1_DATA_MASK,
896*4882a593Smuzhiyun 		.softreset_reg = BMA250_RESET_REG,
897*4882a593Smuzhiyun 		.softreset_val = BMA180_RESET_VAL,
898*4882a593Smuzhiyun 		.chip_config = bma25x_chip_config,
899*4882a593Smuzhiyun 		.chip_disable = bma25x_chip_disable,
900*4882a593Smuzhiyun 	},
901*4882a593Smuzhiyun 	[BMA254] = {
902*4882a593Smuzhiyun 		.chip_id = BMA254_ID_REG_VAL,
903*4882a593Smuzhiyun 		.channels = bma254_channels,
904*4882a593Smuzhiyun 		.num_channels = ARRAY_SIZE(bma254_channels),
905*4882a593Smuzhiyun 		.scale_table = bma25x_scale_table,
906*4882a593Smuzhiyun 		.num_scales = ARRAY_SIZE(bma25x_scale_table),
907*4882a593Smuzhiyun 		.bw_table = bma25x_bw_table,
908*4882a593Smuzhiyun 		.num_bw = ARRAY_SIZE(bma25x_bw_table),
909*4882a593Smuzhiyun 		.temp_offset = 46, /* 0 LSB @ 23 degree C */
910*4882a593Smuzhiyun 		.int_reset_reg = BMA254_INT_RESET_REG,
911*4882a593Smuzhiyun 		.int_reset_mask = BMA254_INT_RESET_MASK,
912*4882a593Smuzhiyun 		.sleep_reg = BMA254_POWER_REG,
913*4882a593Smuzhiyun 		.sleep_mask = BMA254_SUSPEND_MASK,
914*4882a593Smuzhiyun 		.bw_reg = BMA254_BW_REG,
915*4882a593Smuzhiyun 		.bw_mask = BMA254_BW_MASK,
916*4882a593Smuzhiyun 		.bw_offset = BMA254_BW_OFFSET,
917*4882a593Smuzhiyun 		.scale_reg = BMA254_RANGE_REG,
918*4882a593Smuzhiyun 		.scale_mask = BMA254_RANGE_MASK,
919*4882a593Smuzhiyun 		.power_reg = BMA254_POWER_REG,
920*4882a593Smuzhiyun 		.power_mask = BMA254_LOWPOWER_MASK,
921*4882a593Smuzhiyun 		.lowpower_val = 1,
922*4882a593Smuzhiyun 		.int_enable_reg = BMA254_INT_ENABLE_REG,
923*4882a593Smuzhiyun 		.int_enable_mask = BMA254_DATA_INTEN_MASK,
924*4882a593Smuzhiyun 		.int_map_reg = BMA254_INT_MAP_REG,
925*4882a593Smuzhiyun 		.int_enable_dataready_int1_mask = BMA254_INT1_DATA_MASK,
926*4882a593Smuzhiyun 		.softreset_reg = BMA254_RESET_REG,
927*4882a593Smuzhiyun 		.softreset_val = BMA180_RESET_VAL,
928*4882a593Smuzhiyun 		.chip_config = bma25x_chip_config,
929*4882a593Smuzhiyun 		.chip_disable = bma25x_chip_disable,
930*4882a593Smuzhiyun 	},
931*4882a593Smuzhiyun };
932*4882a593Smuzhiyun 
bma180_trigger_handler(int irq,void * p)933*4882a593Smuzhiyun static irqreturn_t bma180_trigger_handler(int irq, void *p)
934*4882a593Smuzhiyun {
935*4882a593Smuzhiyun 	struct iio_poll_func *pf = p;
936*4882a593Smuzhiyun 	struct iio_dev *indio_dev = pf->indio_dev;
937*4882a593Smuzhiyun 	struct bma180_data *data = iio_priv(indio_dev);
938*4882a593Smuzhiyun 	s64 time_ns = iio_get_time_ns(indio_dev);
939*4882a593Smuzhiyun 	int bit, ret, i = 0;
940*4882a593Smuzhiyun 
941*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
942*4882a593Smuzhiyun 
943*4882a593Smuzhiyun 	for_each_set_bit(bit, indio_dev->active_scan_mask,
944*4882a593Smuzhiyun 			 indio_dev->masklength) {
945*4882a593Smuzhiyun 		ret = bma180_get_data_reg(data, bit);
946*4882a593Smuzhiyun 		if (ret < 0) {
947*4882a593Smuzhiyun 			mutex_unlock(&data->mutex);
948*4882a593Smuzhiyun 			goto err;
949*4882a593Smuzhiyun 		}
950*4882a593Smuzhiyun 		data->scan.chan[i++] = ret;
951*4882a593Smuzhiyun 	}
952*4882a593Smuzhiyun 
953*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
954*4882a593Smuzhiyun 
955*4882a593Smuzhiyun 	iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, time_ns);
956*4882a593Smuzhiyun err:
957*4882a593Smuzhiyun 	iio_trigger_notify_done(indio_dev->trig);
958*4882a593Smuzhiyun 
959*4882a593Smuzhiyun 	return IRQ_HANDLED;
960*4882a593Smuzhiyun }
961*4882a593Smuzhiyun 
bma180_data_rdy_trigger_set_state(struct iio_trigger * trig,bool state)962*4882a593Smuzhiyun static int bma180_data_rdy_trigger_set_state(struct iio_trigger *trig,
963*4882a593Smuzhiyun 		bool state)
964*4882a593Smuzhiyun {
965*4882a593Smuzhiyun 	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
966*4882a593Smuzhiyun 	struct bma180_data *data = iio_priv(indio_dev);
967*4882a593Smuzhiyun 
968*4882a593Smuzhiyun 	return bma180_set_new_data_intr_state(data, state);
969*4882a593Smuzhiyun }
970*4882a593Smuzhiyun 
bma180_trig_try_reen(struct iio_trigger * trig)971*4882a593Smuzhiyun static int bma180_trig_try_reen(struct iio_trigger *trig)
972*4882a593Smuzhiyun {
973*4882a593Smuzhiyun 	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
974*4882a593Smuzhiyun 	struct bma180_data *data = iio_priv(indio_dev);
975*4882a593Smuzhiyun 
976*4882a593Smuzhiyun 	return bma180_reset_intr(data);
977*4882a593Smuzhiyun }
978*4882a593Smuzhiyun 
979*4882a593Smuzhiyun static const struct iio_trigger_ops bma180_trigger_ops = {
980*4882a593Smuzhiyun 	.set_trigger_state = bma180_data_rdy_trigger_set_state,
981*4882a593Smuzhiyun 	.try_reenable = bma180_trig_try_reen,
982*4882a593Smuzhiyun };
983*4882a593Smuzhiyun 
bma180_probe(struct i2c_client * client,const struct i2c_device_id * id)984*4882a593Smuzhiyun static int bma180_probe(struct i2c_client *client,
985*4882a593Smuzhiyun 		const struct i2c_device_id *id)
986*4882a593Smuzhiyun {
987*4882a593Smuzhiyun 	struct device *dev = &client->dev;
988*4882a593Smuzhiyun 	struct bma180_data *data;
989*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
990*4882a593Smuzhiyun 	enum chip_ids chip;
991*4882a593Smuzhiyun 	int ret;
992*4882a593Smuzhiyun 
993*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
994*4882a593Smuzhiyun 	if (!indio_dev)
995*4882a593Smuzhiyun 		return -ENOMEM;
996*4882a593Smuzhiyun 
997*4882a593Smuzhiyun 	data = iio_priv(indio_dev);
998*4882a593Smuzhiyun 	i2c_set_clientdata(client, indio_dev);
999*4882a593Smuzhiyun 	data->client = client;
1000*4882a593Smuzhiyun 	if (client->dev.of_node)
1001*4882a593Smuzhiyun 		chip = (enum chip_ids)of_device_get_match_data(dev);
1002*4882a593Smuzhiyun 	else
1003*4882a593Smuzhiyun 		chip = id->driver_data;
1004*4882a593Smuzhiyun 	data->part_info = &bma180_part_info[chip];
1005*4882a593Smuzhiyun 
1006*4882a593Smuzhiyun 	ret = iio_read_mount_matrix(dev, "mount-matrix",
1007*4882a593Smuzhiyun 				&data->orientation);
1008*4882a593Smuzhiyun 	if (ret)
1009*4882a593Smuzhiyun 		return ret;
1010*4882a593Smuzhiyun 
1011*4882a593Smuzhiyun 	data->vdd_supply = devm_regulator_get(dev, "vdd");
1012*4882a593Smuzhiyun 	if (IS_ERR(data->vdd_supply))
1013*4882a593Smuzhiyun 		return dev_err_probe(dev, PTR_ERR(data->vdd_supply),
1014*4882a593Smuzhiyun 				     "Failed to get vdd regulator\n");
1015*4882a593Smuzhiyun 
1016*4882a593Smuzhiyun 	data->vddio_supply = devm_regulator_get(dev, "vddio");
1017*4882a593Smuzhiyun 	if (IS_ERR(data->vddio_supply))
1018*4882a593Smuzhiyun 		return dev_err_probe(dev, PTR_ERR(data->vddio_supply),
1019*4882a593Smuzhiyun 				     "Failed to get vddio regulator\n");
1020*4882a593Smuzhiyun 
1021*4882a593Smuzhiyun 	/* Typical voltage 2.4V these are min and max */
1022*4882a593Smuzhiyun 	ret = regulator_set_voltage(data->vdd_supply, 1620000, 3600000);
1023*4882a593Smuzhiyun 	if (ret)
1024*4882a593Smuzhiyun 		return ret;
1025*4882a593Smuzhiyun 	ret = regulator_set_voltage(data->vddio_supply, 1200000, 3600000);
1026*4882a593Smuzhiyun 	if (ret)
1027*4882a593Smuzhiyun 		return ret;
1028*4882a593Smuzhiyun 	ret = regulator_enable(data->vdd_supply);
1029*4882a593Smuzhiyun 	if (ret) {
1030*4882a593Smuzhiyun 		dev_err(dev, "Failed to enable vdd regulator: %d\n", ret);
1031*4882a593Smuzhiyun 		return ret;
1032*4882a593Smuzhiyun 	}
1033*4882a593Smuzhiyun 	ret = regulator_enable(data->vddio_supply);
1034*4882a593Smuzhiyun 	if (ret) {
1035*4882a593Smuzhiyun 		dev_err(dev, "Failed to enable vddio regulator: %d\n", ret);
1036*4882a593Smuzhiyun 		goto err_disable_vdd;
1037*4882a593Smuzhiyun 	}
1038*4882a593Smuzhiyun 	/* Wait to make sure we started up properly (3 ms at least) */
1039*4882a593Smuzhiyun 	usleep_range(3000, 5000);
1040*4882a593Smuzhiyun 
1041*4882a593Smuzhiyun 	ret = data->part_info->chip_config(data);
1042*4882a593Smuzhiyun 	if (ret < 0)
1043*4882a593Smuzhiyun 		goto err_chip_disable;
1044*4882a593Smuzhiyun 
1045*4882a593Smuzhiyun 	mutex_init(&data->mutex);
1046*4882a593Smuzhiyun 	indio_dev->channels = data->part_info->channels;
1047*4882a593Smuzhiyun 	indio_dev->num_channels = data->part_info->num_channels;
1048*4882a593Smuzhiyun 	indio_dev->name = id->name;
1049*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
1050*4882a593Smuzhiyun 	indio_dev->info = &bma180_info;
1051*4882a593Smuzhiyun 
1052*4882a593Smuzhiyun 	if (client->irq > 0) {
1053*4882a593Smuzhiyun 		data->trig = iio_trigger_alloc("%s-dev%d", indio_dev->name,
1054*4882a593Smuzhiyun 			indio_dev->id);
1055*4882a593Smuzhiyun 		if (!data->trig) {
1056*4882a593Smuzhiyun 			ret = -ENOMEM;
1057*4882a593Smuzhiyun 			goto err_chip_disable;
1058*4882a593Smuzhiyun 		}
1059*4882a593Smuzhiyun 
1060*4882a593Smuzhiyun 		ret = devm_request_irq(dev, client->irq,
1061*4882a593Smuzhiyun 			iio_trigger_generic_data_rdy_poll, IRQF_TRIGGER_RISING,
1062*4882a593Smuzhiyun 			"bma180_event", data->trig);
1063*4882a593Smuzhiyun 		if (ret) {
1064*4882a593Smuzhiyun 			dev_err(dev, "unable to request IRQ\n");
1065*4882a593Smuzhiyun 			goto err_trigger_free;
1066*4882a593Smuzhiyun 		}
1067*4882a593Smuzhiyun 
1068*4882a593Smuzhiyun 		data->trig->dev.parent = dev;
1069*4882a593Smuzhiyun 		data->trig->ops = &bma180_trigger_ops;
1070*4882a593Smuzhiyun 		iio_trigger_set_drvdata(data->trig, indio_dev);
1071*4882a593Smuzhiyun 
1072*4882a593Smuzhiyun 		ret = iio_trigger_register(data->trig);
1073*4882a593Smuzhiyun 		if (ret)
1074*4882a593Smuzhiyun 			goto err_trigger_free;
1075*4882a593Smuzhiyun 
1076*4882a593Smuzhiyun 		indio_dev->trig = iio_trigger_get(data->trig);
1077*4882a593Smuzhiyun 	}
1078*4882a593Smuzhiyun 
1079*4882a593Smuzhiyun 	ret = iio_triggered_buffer_setup(indio_dev, NULL,
1080*4882a593Smuzhiyun 			bma180_trigger_handler, NULL);
1081*4882a593Smuzhiyun 	if (ret < 0) {
1082*4882a593Smuzhiyun 		dev_err(dev, "unable to setup iio triggered buffer\n");
1083*4882a593Smuzhiyun 		goto err_trigger_unregister;
1084*4882a593Smuzhiyun 	}
1085*4882a593Smuzhiyun 
1086*4882a593Smuzhiyun 	ret = iio_device_register(indio_dev);
1087*4882a593Smuzhiyun 	if (ret < 0) {
1088*4882a593Smuzhiyun 		dev_err(dev, "unable to register iio device\n");
1089*4882a593Smuzhiyun 		goto err_buffer_cleanup;
1090*4882a593Smuzhiyun 	}
1091*4882a593Smuzhiyun 
1092*4882a593Smuzhiyun 	return 0;
1093*4882a593Smuzhiyun 
1094*4882a593Smuzhiyun err_buffer_cleanup:
1095*4882a593Smuzhiyun 	iio_triggered_buffer_cleanup(indio_dev);
1096*4882a593Smuzhiyun err_trigger_unregister:
1097*4882a593Smuzhiyun 	if (data->trig)
1098*4882a593Smuzhiyun 		iio_trigger_unregister(data->trig);
1099*4882a593Smuzhiyun err_trigger_free:
1100*4882a593Smuzhiyun 	iio_trigger_free(data->trig);
1101*4882a593Smuzhiyun err_chip_disable:
1102*4882a593Smuzhiyun 	data->part_info->chip_disable(data);
1103*4882a593Smuzhiyun 	regulator_disable(data->vddio_supply);
1104*4882a593Smuzhiyun err_disable_vdd:
1105*4882a593Smuzhiyun 	regulator_disable(data->vdd_supply);
1106*4882a593Smuzhiyun 
1107*4882a593Smuzhiyun 	return ret;
1108*4882a593Smuzhiyun }
1109*4882a593Smuzhiyun 
bma180_remove(struct i2c_client * client)1110*4882a593Smuzhiyun static int bma180_remove(struct i2c_client *client)
1111*4882a593Smuzhiyun {
1112*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
1113*4882a593Smuzhiyun 	struct bma180_data *data = iio_priv(indio_dev);
1114*4882a593Smuzhiyun 
1115*4882a593Smuzhiyun 	iio_device_unregister(indio_dev);
1116*4882a593Smuzhiyun 	iio_triggered_buffer_cleanup(indio_dev);
1117*4882a593Smuzhiyun 	if (data->trig) {
1118*4882a593Smuzhiyun 		iio_trigger_unregister(data->trig);
1119*4882a593Smuzhiyun 		iio_trigger_free(data->trig);
1120*4882a593Smuzhiyun 	}
1121*4882a593Smuzhiyun 
1122*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
1123*4882a593Smuzhiyun 	data->part_info->chip_disable(data);
1124*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
1125*4882a593Smuzhiyun 	regulator_disable(data->vddio_supply);
1126*4882a593Smuzhiyun 	regulator_disable(data->vdd_supply);
1127*4882a593Smuzhiyun 
1128*4882a593Smuzhiyun 	return 0;
1129*4882a593Smuzhiyun }
1130*4882a593Smuzhiyun 
1131*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
bma180_suspend(struct device * dev)1132*4882a593Smuzhiyun static int bma180_suspend(struct device *dev)
1133*4882a593Smuzhiyun {
1134*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1135*4882a593Smuzhiyun 	struct bma180_data *data = iio_priv(indio_dev);
1136*4882a593Smuzhiyun 	int ret;
1137*4882a593Smuzhiyun 
1138*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
1139*4882a593Smuzhiyun 	ret = bma180_set_sleep_state(data, true);
1140*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
1141*4882a593Smuzhiyun 
1142*4882a593Smuzhiyun 	return ret;
1143*4882a593Smuzhiyun }
1144*4882a593Smuzhiyun 
bma180_resume(struct device * dev)1145*4882a593Smuzhiyun static int bma180_resume(struct device *dev)
1146*4882a593Smuzhiyun {
1147*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1148*4882a593Smuzhiyun 	struct bma180_data *data = iio_priv(indio_dev);
1149*4882a593Smuzhiyun 	int ret;
1150*4882a593Smuzhiyun 
1151*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
1152*4882a593Smuzhiyun 	ret = bma180_set_sleep_state(data, false);
1153*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
1154*4882a593Smuzhiyun 
1155*4882a593Smuzhiyun 	return ret;
1156*4882a593Smuzhiyun }
1157*4882a593Smuzhiyun 
1158*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(bma180_pm_ops, bma180_suspend, bma180_resume);
1159*4882a593Smuzhiyun #define BMA180_PM_OPS (&bma180_pm_ops)
1160*4882a593Smuzhiyun #else
1161*4882a593Smuzhiyun #define BMA180_PM_OPS NULL
1162*4882a593Smuzhiyun #endif
1163*4882a593Smuzhiyun 
1164*4882a593Smuzhiyun static const struct i2c_device_id bma180_ids[] = {
1165*4882a593Smuzhiyun 	{ "bma023", BMA023 },
1166*4882a593Smuzhiyun 	{ "bma150", BMA150 },
1167*4882a593Smuzhiyun 	{ "bma180", BMA180 },
1168*4882a593Smuzhiyun 	{ "bma250", BMA250 },
1169*4882a593Smuzhiyun 	{ "bma254", BMA254 },
1170*4882a593Smuzhiyun 	{ "smb380", BMA150 },
1171*4882a593Smuzhiyun 	{ }
1172*4882a593Smuzhiyun };
1173*4882a593Smuzhiyun 
1174*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, bma180_ids);
1175*4882a593Smuzhiyun 
1176*4882a593Smuzhiyun static const struct of_device_id bma180_of_match[] = {
1177*4882a593Smuzhiyun 	{
1178*4882a593Smuzhiyun 		.compatible = "bosch,bma023",
1179*4882a593Smuzhiyun 		.data = (void *)BMA023
1180*4882a593Smuzhiyun 	},
1181*4882a593Smuzhiyun 	{
1182*4882a593Smuzhiyun 		.compatible = "bosch,bma150",
1183*4882a593Smuzhiyun 		.data = (void *)BMA150
1184*4882a593Smuzhiyun 	},
1185*4882a593Smuzhiyun 	{
1186*4882a593Smuzhiyun 		.compatible = "bosch,bma180",
1187*4882a593Smuzhiyun 		.data = (void *)BMA180
1188*4882a593Smuzhiyun 	},
1189*4882a593Smuzhiyun 	{
1190*4882a593Smuzhiyun 		.compatible = "bosch,bma250",
1191*4882a593Smuzhiyun 		.data = (void *)BMA250
1192*4882a593Smuzhiyun 	},
1193*4882a593Smuzhiyun 	{
1194*4882a593Smuzhiyun 		.compatible = "bosch,bma254",
1195*4882a593Smuzhiyun 		.data = (void *)BMA254
1196*4882a593Smuzhiyun 	},
1197*4882a593Smuzhiyun 	{
1198*4882a593Smuzhiyun 		.compatible = "bosch,smb380",
1199*4882a593Smuzhiyun 		.data = (void *)BMA150
1200*4882a593Smuzhiyun 	},
1201*4882a593Smuzhiyun 	{ }
1202*4882a593Smuzhiyun };
1203*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, bma180_of_match);
1204*4882a593Smuzhiyun 
1205*4882a593Smuzhiyun static struct i2c_driver bma180_driver = {
1206*4882a593Smuzhiyun 	.driver = {
1207*4882a593Smuzhiyun 		.name	= "bma180",
1208*4882a593Smuzhiyun 		.pm	= BMA180_PM_OPS,
1209*4882a593Smuzhiyun 		.of_match_table = bma180_of_match,
1210*4882a593Smuzhiyun 	},
1211*4882a593Smuzhiyun 	.probe		= bma180_probe,
1212*4882a593Smuzhiyun 	.remove		= bma180_remove,
1213*4882a593Smuzhiyun 	.id_table	= bma180_ids,
1214*4882a593Smuzhiyun };
1215*4882a593Smuzhiyun 
1216*4882a593Smuzhiyun module_i2c_driver(bma180_driver);
1217*4882a593Smuzhiyun 
1218*4882a593Smuzhiyun MODULE_AUTHOR("Kravchenko Oleksandr <x0199363@ti.com>");
1219*4882a593Smuzhiyun MODULE_AUTHOR("Texas Instruments, Inc.");
1220*4882a593Smuzhiyun MODULE_DESCRIPTION("Bosch BMA023/BMA1x0/BMA25x triaxial acceleration sensor");
1221*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1222