xref: /OK3568_Linux_fs/kernel/drivers/ide/ide-dma.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  *  IDE DMA support (including IDE PCI BM-DMA).
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  *  Copyright (C) 1995-1998   Mark Lord
5*4882a593Smuzhiyun  *  Copyright (C) 1999-2000   Andre Hedrick <andre@linux-ide.org>
6*4882a593Smuzhiyun  *  Copyright (C) 2004, 2007  Bartlomiej Zolnierkiewicz
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  *  May be copied or modified under the terms of the GNU General Public License
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  *  DMA is supported for all IDE devices (disk drives, cdroms, tapes, floppies).
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun  *  Special Thanks to Mark for his Six years of work.
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun /*
18*4882a593Smuzhiyun  * Thanks to "Christopher J. Reimer" <reimer@doe.carleton.ca> for
19*4882a593Smuzhiyun  * fixing the problem with the BIOS on some Acer motherboards.
20*4882a593Smuzhiyun  *
21*4882a593Smuzhiyun  * Thanks to "Benoit Poulot-Cazajous" <poulot@chorus.fr> for testing
22*4882a593Smuzhiyun  * "TX" chipset compatibility and for providing patches for the "TX" chipset.
23*4882a593Smuzhiyun  *
24*4882a593Smuzhiyun  * Thanks to Christian Brunner <chb@muc.de> for taking a good first crack
25*4882a593Smuzhiyun  * at generic DMA -- his patches were referred to when preparing this code.
26*4882a593Smuzhiyun  *
27*4882a593Smuzhiyun  * Most importantly, thanks to Robert Bringman <rob@mars.trion.com>
28*4882a593Smuzhiyun  * for supplying a Promise UDMA board & WD UDMA drive for this work!
29*4882a593Smuzhiyun  */
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #include <linux/types.h>
32*4882a593Smuzhiyun #include <linux/gfp.h>
33*4882a593Smuzhiyun #include <linux/kernel.h>
34*4882a593Smuzhiyun #include <linux/export.h>
35*4882a593Smuzhiyun #include <linux/ide.h>
36*4882a593Smuzhiyun #include <linux/scatterlist.h>
37*4882a593Smuzhiyun #include <linux/dma-mapping.h>
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun static const struct drive_list_entry drive_whitelist[] = {
40*4882a593Smuzhiyun 	{ "Micropolis 2112A"	,       NULL		},
41*4882a593Smuzhiyun 	{ "CONNER CTMA 4000"	,       NULL		},
42*4882a593Smuzhiyun 	{ "CONNER CTT8000-A"	,       NULL		},
43*4882a593Smuzhiyun 	{ "ST34342A"		,	NULL		},
44*4882a593Smuzhiyun 	{ NULL			,	NULL		}
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun static const struct drive_list_entry drive_blacklist[] = {
48*4882a593Smuzhiyun 	{ "WDC AC11000H"	,	NULL 		},
49*4882a593Smuzhiyun 	{ "WDC AC22100H"	,	NULL 		},
50*4882a593Smuzhiyun 	{ "WDC AC32500H"	,	NULL 		},
51*4882a593Smuzhiyun 	{ "WDC AC33100H"	,	NULL 		},
52*4882a593Smuzhiyun 	{ "WDC AC31600H"	,	NULL 		},
53*4882a593Smuzhiyun 	{ "WDC AC32100H"	,	"24.09P07"	},
54*4882a593Smuzhiyun 	{ "WDC AC23200L"	,	"21.10N21"	},
55*4882a593Smuzhiyun 	{ "Compaq CRD-8241B"	,	NULL 		},
56*4882a593Smuzhiyun 	{ "CRD-8400B"		,	NULL 		},
57*4882a593Smuzhiyun 	{ "CRD-8480B",			NULL 		},
58*4882a593Smuzhiyun 	{ "CRD-8482B",			NULL 		},
59*4882a593Smuzhiyun 	{ "CRD-84"		,	NULL 		},
60*4882a593Smuzhiyun 	{ "SanDisk SDP3B"	,	NULL 		},
61*4882a593Smuzhiyun 	{ "SanDisk SDP3B-64"	,	NULL 		},
62*4882a593Smuzhiyun 	{ "SANYO CD-ROM CRD"	,	NULL 		},
63*4882a593Smuzhiyun 	{ "HITACHI CDR-8"	,	NULL 		},
64*4882a593Smuzhiyun 	{ "HITACHI CDR-8335"	,	NULL 		},
65*4882a593Smuzhiyun 	{ "HITACHI CDR-8435"	,	NULL 		},
66*4882a593Smuzhiyun 	{ "Toshiba CD-ROM XM-6202B"	,	NULL 		},
67*4882a593Smuzhiyun 	{ "TOSHIBA CD-ROM XM-1702BC",	NULL 		},
68*4882a593Smuzhiyun 	{ "CD-532E-A"		,	NULL 		},
69*4882a593Smuzhiyun 	{ "E-IDE CD-ROM CR-840",	NULL 		},
70*4882a593Smuzhiyun 	{ "CD-ROM Drive/F5A",	NULL 		},
71*4882a593Smuzhiyun 	{ "WPI CDD-820",		NULL 		},
72*4882a593Smuzhiyun 	{ "SAMSUNG CD-ROM SC-148C",	NULL 		},
73*4882a593Smuzhiyun 	{ "SAMSUNG CD-ROM SC",	NULL 		},
74*4882a593Smuzhiyun 	{ "ATAPI CD-ROM DRIVE 40X MAXIMUM",	NULL 		},
75*4882a593Smuzhiyun 	{ "_NEC DV5800A",               NULL            },
76*4882a593Smuzhiyun 	{ "SAMSUNG CD-ROM SN-124",	"N001" },
77*4882a593Smuzhiyun 	{ "Seagate STT20000A",		NULL  },
78*4882a593Smuzhiyun 	{ "CD-ROM CDR_U200",		"1.09" },
79*4882a593Smuzhiyun 	{ NULL			,	NULL		}
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun /**
84*4882a593Smuzhiyun  *	ide_dma_intr	-	IDE DMA interrupt handler
85*4882a593Smuzhiyun  *	@drive: the drive the interrupt is for
86*4882a593Smuzhiyun  *
87*4882a593Smuzhiyun  *	Handle an interrupt completing a read/write DMA transfer on an
88*4882a593Smuzhiyun  *	IDE device
89*4882a593Smuzhiyun  */
90*4882a593Smuzhiyun 
ide_dma_intr(ide_drive_t * drive)91*4882a593Smuzhiyun ide_startstop_t ide_dma_intr(ide_drive_t *drive)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun 	ide_hwif_t *hwif = drive->hwif;
94*4882a593Smuzhiyun 	struct ide_cmd *cmd = &hwif->cmd;
95*4882a593Smuzhiyun 	u8 stat = 0, dma_stat = 0;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 	drive->waiting_for_dma = 0;
98*4882a593Smuzhiyun 	dma_stat = hwif->dma_ops->dma_end(drive);
99*4882a593Smuzhiyun 	ide_dma_unmap_sg(drive, cmd);
100*4882a593Smuzhiyun 	stat = hwif->tp_ops->read_status(hwif);
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	if (OK_STAT(stat, DRIVE_READY, drive->bad_wstat | ATA_DRQ)) {
103*4882a593Smuzhiyun 		if (!dma_stat) {
104*4882a593Smuzhiyun 			if ((cmd->tf_flags & IDE_TFLAG_FS) == 0)
105*4882a593Smuzhiyun 				ide_finish_cmd(drive, cmd, stat);
106*4882a593Smuzhiyun 			else
107*4882a593Smuzhiyun 				ide_complete_rq(drive, BLK_STS_OK,
108*4882a593Smuzhiyun 						blk_rq_sectors(cmd->rq) << 9);
109*4882a593Smuzhiyun 			return ide_stopped;
110*4882a593Smuzhiyun 		}
111*4882a593Smuzhiyun 		printk(KERN_ERR "%s: %s: bad DMA status (0x%02x)\n",
112*4882a593Smuzhiyun 			drive->name, __func__, dma_stat);
113*4882a593Smuzhiyun 	}
114*4882a593Smuzhiyun 	return ide_error(drive, "dma_intr", stat);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun 
ide_dma_good_drive(ide_drive_t * drive)117*4882a593Smuzhiyun int ide_dma_good_drive(ide_drive_t *drive)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun 	return ide_in_drive_list(drive->id, drive_whitelist);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun /**
123*4882a593Smuzhiyun  *	ide_dma_map_sg	-	map IDE scatter gather for DMA I/O
124*4882a593Smuzhiyun  *	@drive: the drive to map the DMA table for
125*4882a593Smuzhiyun  *	@cmd: command
126*4882a593Smuzhiyun  *
127*4882a593Smuzhiyun  *	Perform the DMA mapping magic necessary to access the source or
128*4882a593Smuzhiyun  *	target buffers of a request via DMA.  The lower layers of the
129*4882a593Smuzhiyun  *	kernel provide the necessary cache management so that we can
130*4882a593Smuzhiyun  *	operate in a portable fashion.
131*4882a593Smuzhiyun  */
132*4882a593Smuzhiyun 
ide_dma_map_sg(ide_drive_t * drive,struct ide_cmd * cmd)133*4882a593Smuzhiyun static int ide_dma_map_sg(ide_drive_t *drive, struct ide_cmd *cmd)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun 	ide_hwif_t *hwif = drive->hwif;
136*4882a593Smuzhiyun 	struct scatterlist *sg = hwif->sg_table;
137*4882a593Smuzhiyun 	int i;
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	if (cmd->tf_flags & IDE_TFLAG_WRITE)
140*4882a593Smuzhiyun 		cmd->sg_dma_direction = DMA_TO_DEVICE;
141*4882a593Smuzhiyun 	else
142*4882a593Smuzhiyun 		cmd->sg_dma_direction = DMA_FROM_DEVICE;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	i = dma_map_sg(hwif->dev, sg, cmd->sg_nents, cmd->sg_dma_direction);
145*4882a593Smuzhiyun 	if (i) {
146*4882a593Smuzhiyun 		cmd->orig_sg_nents = cmd->sg_nents;
147*4882a593Smuzhiyun 		cmd->sg_nents = i;
148*4882a593Smuzhiyun 	}
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	return i;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun /**
154*4882a593Smuzhiyun  *	ide_dma_unmap_sg	-	clean up DMA mapping
155*4882a593Smuzhiyun  *	@drive: The drive to unmap
156*4882a593Smuzhiyun  *
157*4882a593Smuzhiyun  *	Teardown mappings after DMA has completed. This must be called
158*4882a593Smuzhiyun  *	after the completion of each use of ide_build_dmatable and before
159*4882a593Smuzhiyun  *	the next use of ide_build_dmatable. Failure to do so will cause
160*4882a593Smuzhiyun  *	an oops as only one mapping can be live for each target at a given
161*4882a593Smuzhiyun  *	time.
162*4882a593Smuzhiyun  */
163*4882a593Smuzhiyun 
ide_dma_unmap_sg(ide_drive_t * drive,struct ide_cmd * cmd)164*4882a593Smuzhiyun void ide_dma_unmap_sg(ide_drive_t *drive, struct ide_cmd *cmd)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	ide_hwif_t *hwif = drive->hwif;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	dma_unmap_sg(hwif->dev, hwif->sg_table, cmd->orig_sg_nents,
169*4882a593Smuzhiyun 		     cmd->sg_dma_direction);
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ide_dma_unmap_sg);
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun /**
174*4882a593Smuzhiyun  *	ide_dma_off_quietly	-	Generic DMA kill
175*4882a593Smuzhiyun  *	@drive: drive to control
176*4882a593Smuzhiyun  *
177*4882a593Smuzhiyun  *	Turn off the current DMA on this IDE controller.
178*4882a593Smuzhiyun  */
179*4882a593Smuzhiyun 
ide_dma_off_quietly(ide_drive_t * drive)180*4882a593Smuzhiyun void ide_dma_off_quietly(ide_drive_t *drive)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun 	drive->dev_flags &= ~IDE_DFLAG_USING_DMA;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	drive->hwif->dma_ops->dma_host_set(drive, 0);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun EXPORT_SYMBOL(ide_dma_off_quietly);
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun /**
189*4882a593Smuzhiyun  *	ide_dma_off	-	disable DMA on a device
190*4882a593Smuzhiyun  *	@drive: drive to disable DMA on
191*4882a593Smuzhiyun  *
192*4882a593Smuzhiyun  *	Disable IDE DMA for a device on this IDE controller.
193*4882a593Smuzhiyun  *	Inform the user that DMA has been disabled.
194*4882a593Smuzhiyun  */
195*4882a593Smuzhiyun 
ide_dma_off(ide_drive_t * drive)196*4882a593Smuzhiyun void ide_dma_off(ide_drive_t *drive)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun 	printk(KERN_INFO "%s: DMA disabled\n", drive->name);
199*4882a593Smuzhiyun 	ide_dma_off_quietly(drive);
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun EXPORT_SYMBOL(ide_dma_off);
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun /**
204*4882a593Smuzhiyun  *	ide_dma_on		-	Enable DMA on a device
205*4882a593Smuzhiyun  *	@drive: drive to enable DMA on
206*4882a593Smuzhiyun  *
207*4882a593Smuzhiyun  *	Enable IDE DMA for a device on this IDE controller.
208*4882a593Smuzhiyun  */
209*4882a593Smuzhiyun 
ide_dma_on(ide_drive_t * drive)210*4882a593Smuzhiyun void ide_dma_on(ide_drive_t *drive)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun 	drive->dev_flags |= IDE_DFLAG_USING_DMA;
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun 	drive->hwif->dma_ops->dma_host_set(drive, 1);
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun 
__ide_dma_bad_drive(ide_drive_t * drive)217*4882a593Smuzhiyun int __ide_dma_bad_drive(ide_drive_t *drive)
218*4882a593Smuzhiyun {
219*4882a593Smuzhiyun 	u16 *id = drive->id;
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	int blacklist = ide_in_drive_list(id, drive_blacklist);
222*4882a593Smuzhiyun 	if (blacklist) {
223*4882a593Smuzhiyun 		printk(KERN_WARNING "%s: Disabling (U)DMA for %s (blacklisted)\n",
224*4882a593Smuzhiyun 				    drive->name, (char *)&id[ATA_ID_PROD]);
225*4882a593Smuzhiyun 		return blacklist;
226*4882a593Smuzhiyun 	}
227*4882a593Smuzhiyun 	return 0;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun EXPORT_SYMBOL(__ide_dma_bad_drive);
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun static const u8 xfer_mode_bases[] = {
232*4882a593Smuzhiyun 	XFER_UDMA_0,
233*4882a593Smuzhiyun 	XFER_MW_DMA_0,
234*4882a593Smuzhiyun 	XFER_SW_DMA_0,
235*4882a593Smuzhiyun };
236*4882a593Smuzhiyun 
ide_get_mode_mask(ide_drive_t * drive,u8 base,u8 req_mode)237*4882a593Smuzhiyun static unsigned int ide_get_mode_mask(ide_drive_t *drive, u8 base, u8 req_mode)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun 	u16 *id = drive->id;
240*4882a593Smuzhiyun 	ide_hwif_t *hwif = drive->hwif;
241*4882a593Smuzhiyun 	const struct ide_port_ops *port_ops = hwif->port_ops;
242*4882a593Smuzhiyun 	unsigned int mask = 0;
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	switch (base) {
245*4882a593Smuzhiyun 	case XFER_UDMA_0:
246*4882a593Smuzhiyun 		if ((id[ATA_ID_FIELD_VALID] & 4) == 0)
247*4882a593Smuzhiyun 			break;
248*4882a593Smuzhiyun 		mask = id[ATA_ID_UDMA_MODES];
249*4882a593Smuzhiyun 		if (port_ops && port_ops->udma_filter)
250*4882a593Smuzhiyun 			mask &= port_ops->udma_filter(drive);
251*4882a593Smuzhiyun 		else
252*4882a593Smuzhiyun 			mask &= hwif->ultra_mask;
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 		/*
255*4882a593Smuzhiyun 		 * avoid false cable warning from eighty_ninty_three()
256*4882a593Smuzhiyun 		 */
257*4882a593Smuzhiyun 		if (req_mode > XFER_UDMA_2) {
258*4882a593Smuzhiyun 			if ((mask & 0x78) && (eighty_ninty_three(drive) == 0))
259*4882a593Smuzhiyun 				mask &= 0x07;
260*4882a593Smuzhiyun 		}
261*4882a593Smuzhiyun 		break;
262*4882a593Smuzhiyun 	case XFER_MW_DMA_0:
263*4882a593Smuzhiyun 		mask = id[ATA_ID_MWDMA_MODES];
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 		/* Also look for the CF specific MWDMA modes... */
266*4882a593Smuzhiyun 		if (ata_id_is_cfa(id) && (id[ATA_ID_CFA_MODES] & 0x38)) {
267*4882a593Smuzhiyun 			u8 mode = ((id[ATA_ID_CFA_MODES] & 0x38) >> 3) - 1;
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 			mask |= ((2 << mode) - 1) << 3;
270*4882a593Smuzhiyun 		}
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 		if (port_ops && port_ops->mdma_filter)
273*4882a593Smuzhiyun 			mask &= port_ops->mdma_filter(drive);
274*4882a593Smuzhiyun 		else
275*4882a593Smuzhiyun 			mask &= hwif->mwdma_mask;
276*4882a593Smuzhiyun 		break;
277*4882a593Smuzhiyun 	case XFER_SW_DMA_0:
278*4882a593Smuzhiyun 		mask = id[ATA_ID_SWDMA_MODES];
279*4882a593Smuzhiyun 		if (!(mask & ATA_SWDMA2) && (id[ATA_ID_OLD_DMA_MODES] >> 8)) {
280*4882a593Smuzhiyun 			u8 mode = id[ATA_ID_OLD_DMA_MODES] >> 8;
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 			/*
283*4882a593Smuzhiyun 			 * if the mode is valid convert it to the mask
284*4882a593Smuzhiyun 			 * (the maximum allowed mode is XFER_SW_DMA_2)
285*4882a593Smuzhiyun 			 */
286*4882a593Smuzhiyun 			if (mode <= 2)
287*4882a593Smuzhiyun 				mask = (2 << mode) - 1;
288*4882a593Smuzhiyun 		}
289*4882a593Smuzhiyun 		mask &= hwif->swdma_mask;
290*4882a593Smuzhiyun 		break;
291*4882a593Smuzhiyun 	default:
292*4882a593Smuzhiyun 		BUG();
293*4882a593Smuzhiyun 		break;
294*4882a593Smuzhiyun 	}
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	return mask;
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun 
299*4882a593Smuzhiyun /**
300*4882a593Smuzhiyun  *	ide_find_dma_mode	-	compute DMA speed
301*4882a593Smuzhiyun  *	@drive: IDE device
302*4882a593Smuzhiyun  *	@req_mode: requested mode
303*4882a593Smuzhiyun  *
304*4882a593Smuzhiyun  *	Checks the drive/host capabilities and finds the speed to use for
305*4882a593Smuzhiyun  *	the DMA transfer.  The speed is then limited by the requested mode.
306*4882a593Smuzhiyun  *
307*4882a593Smuzhiyun  *	Returns 0 if the drive/host combination is incapable of DMA transfers
308*4882a593Smuzhiyun  *	or if the requested mode is not a DMA mode.
309*4882a593Smuzhiyun  */
310*4882a593Smuzhiyun 
ide_find_dma_mode(ide_drive_t * drive,u8 req_mode)311*4882a593Smuzhiyun u8 ide_find_dma_mode(ide_drive_t *drive, u8 req_mode)
312*4882a593Smuzhiyun {
313*4882a593Smuzhiyun 	ide_hwif_t *hwif = drive->hwif;
314*4882a593Smuzhiyun 	unsigned int mask;
315*4882a593Smuzhiyun 	int x, i;
316*4882a593Smuzhiyun 	u8 mode = 0;
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun 	if (drive->media != ide_disk) {
319*4882a593Smuzhiyun 		if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA)
320*4882a593Smuzhiyun 			return 0;
321*4882a593Smuzhiyun 	}
322*4882a593Smuzhiyun 
323*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(xfer_mode_bases); i++) {
324*4882a593Smuzhiyun 		if (req_mode < xfer_mode_bases[i])
325*4882a593Smuzhiyun 			continue;
326*4882a593Smuzhiyun 		mask = ide_get_mode_mask(drive, xfer_mode_bases[i], req_mode);
327*4882a593Smuzhiyun 		x = fls(mask) - 1;
328*4882a593Smuzhiyun 		if (x >= 0) {
329*4882a593Smuzhiyun 			mode = xfer_mode_bases[i] + x;
330*4882a593Smuzhiyun 			break;
331*4882a593Smuzhiyun 		}
332*4882a593Smuzhiyun 	}
333*4882a593Smuzhiyun 
334*4882a593Smuzhiyun 	if (hwif->chipset == ide_acorn && mode == 0) {
335*4882a593Smuzhiyun 		/*
336*4882a593Smuzhiyun 		 * is this correct?
337*4882a593Smuzhiyun 		 */
338*4882a593Smuzhiyun 		if (ide_dma_good_drive(drive) &&
339*4882a593Smuzhiyun 		    drive->id[ATA_ID_EIDE_DMA_TIME] < 150)
340*4882a593Smuzhiyun 			mode = XFER_MW_DMA_1;
341*4882a593Smuzhiyun 	}
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	mode = min(mode, req_mode);
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	printk(KERN_INFO "%s: %s mode selected\n", drive->name,
346*4882a593Smuzhiyun 			  mode ? ide_xfer_verbose(mode) : "no DMA");
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	return mode;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun 
ide_tune_dma(ide_drive_t * drive)351*4882a593Smuzhiyun static int ide_tune_dma(ide_drive_t *drive)
352*4882a593Smuzhiyun {
353*4882a593Smuzhiyun 	ide_hwif_t *hwif = drive->hwif;
354*4882a593Smuzhiyun 	u8 speed;
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	if (ata_id_has_dma(drive->id) == 0 ||
357*4882a593Smuzhiyun 	    (drive->dev_flags & IDE_DFLAG_NODMA))
358*4882a593Smuzhiyun 		return 0;
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	/* consult the list of known "bad" drives */
361*4882a593Smuzhiyun 	if (__ide_dma_bad_drive(drive))
362*4882a593Smuzhiyun 		return 0;
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun 	if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA)
365*4882a593Smuzhiyun 		return config_drive_for_dma(drive);
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	speed = ide_max_dma_mode(drive);
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	if (!speed)
370*4882a593Smuzhiyun 		return 0;
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	if (ide_set_dma_mode(drive, speed))
373*4882a593Smuzhiyun 		return 0;
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun 	return 1;
376*4882a593Smuzhiyun }
377*4882a593Smuzhiyun 
ide_dma_check(ide_drive_t * drive)378*4882a593Smuzhiyun static int ide_dma_check(ide_drive_t *drive)
379*4882a593Smuzhiyun {
380*4882a593Smuzhiyun 	ide_hwif_t *hwif = drive->hwif;
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	if (ide_tune_dma(drive))
383*4882a593Smuzhiyun 		return 0;
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	/* TODO: always do PIO fallback */
386*4882a593Smuzhiyun 	if (hwif->host_flags & IDE_HFLAG_TRUST_BIOS_FOR_DMA)
387*4882a593Smuzhiyun 		return -1;
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun 	ide_set_max_pio(drive);
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 	return -1;
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun 
ide_set_dma(ide_drive_t * drive)394*4882a593Smuzhiyun int ide_set_dma(ide_drive_t *drive)
395*4882a593Smuzhiyun {
396*4882a593Smuzhiyun 	int rc;
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun 	/*
399*4882a593Smuzhiyun 	 * Force DMAing for the beginning of the check.
400*4882a593Smuzhiyun 	 * Some chipsets appear to do interesting
401*4882a593Smuzhiyun 	 * things, if not checked and cleared.
402*4882a593Smuzhiyun 	 *   PARANOIA!!!
403*4882a593Smuzhiyun 	 */
404*4882a593Smuzhiyun 	ide_dma_off_quietly(drive);
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun 	rc = ide_dma_check(drive);
407*4882a593Smuzhiyun 	if (rc)
408*4882a593Smuzhiyun 		return rc;
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	ide_dma_on(drive);
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	return 0;
413*4882a593Smuzhiyun }
414*4882a593Smuzhiyun 
ide_check_dma_crc(ide_drive_t * drive)415*4882a593Smuzhiyun void ide_check_dma_crc(ide_drive_t *drive)
416*4882a593Smuzhiyun {
417*4882a593Smuzhiyun 	u8 mode;
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	ide_dma_off_quietly(drive);
420*4882a593Smuzhiyun 	drive->crc_count = 0;
421*4882a593Smuzhiyun 	mode = drive->current_speed;
422*4882a593Smuzhiyun 	/*
423*4882a593Smuzhiyun 	 * Don't try non Ultra-DMA modes without iCRC's.  Force the
424*4882a593Smuzhiyun 	 * device to PIO and make the user enable SWDMA/MWDMA modes.
425*4882a593Smuzhiyun 	 */
426*4882a593Smuzhiyun 	if (mode > XFER_UDMA_0 && mode <= XFER_UDMA_7)
427*4882a593Smuzhiyun 		mode--;
428*4882a593Smuzhiyun 	else
429*4882a593Smuzhiyun 		mode = XFER_PIO_4;
430*4882a593Smuzhiyun 	ide_set_xfer_rate(drive, mode);
431*4882a593Smuzhiyun 	if (drive->current_speed >= XFER_SW_DMA_0)
432*4882a593Smuzhiyun 		ide_dma_on(drive);
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun 
ide_dma_lost_irq(ide_drive_t * drive)435*4882a593Smuzhiyun void ide_dma_lost_irq(ide_drive_t *drive)
436*4882a593Smuzhiyun {
437*4882a593Smuzhiyun 	printk(KERN_ERR "%s: DMA interrupt recovery\n", drive->name);
438*4882a593Smuzhiyun }
439*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ide_dma_lost_irq);
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun /*
442*4882a593Smuzhiyun  * un-busy the port etc, and clear any pending DMA status. we want to
443*4882a593Smuzhiyun  * retry the current request in pio mode instead of risking tossing it
444*4882a593Smuzhiyun  * all away
445*4882a593Smuzhiyun  */
ide_dma_timeout_retry(ide_drive_t * drive,int error)446*4882a593Smuzhiyun ide_startstop_t ide_dma_timeout_retry(ide_drive_t *drive, int error)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun 	ide_hwif_t *hwif = drive->hwif;
449*4882a593Smuzhiyun 	const struct ide_dma_ops *dma_ops = hwif->dma_ops;
450*4882a593Smuzhiyun 	struct ide_cmd *cmd = &hwif->cmd;
451*4882a593Smuzhiyun 	ide_startstop_t ret = ide_stopped;
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun 	/*
454*4882a593Smuzhiyun 	 * end current dma transaction
455*4882a593Smuzhiyun 	 */
456*4882a593Smuzhiyun 
457*4882a593Smuzhiyun 	if (error < 0) {
458*4882a593Smuzhiyun 		printk(KERN_WARNING "%s: DMA timeout error\n", drive->name);
459*4882a593Smuzhiyun 		drive->waiting_for_dma = 0;
460*4882a593Smuzhiyun 		(void)dma_ops->dma_end(drive);
461*4882a593Smuzhiyun 		ide_dma_unmap_sg(drive, cmd);
462*4882a593Smuzhiyun 		ret = ide_error(drive, "dma timeout error",
463*4882a593Smuzhiyun 				hwif->tp_ops->read_status(hwif));
464*4882a593Smuzhiyun 	} else {
465*4882a593Smuzhiyun 		printk(KERN_WARNING "%s: DMA timeout retry\n", drive->name);
466*4882a593Smuzhiyun 		if (dma_ops->dma_clear)
467*4882a593Smuzhiyun 			dma_ops->dma_clear(drive);
468*4882a593Smuzhiyun 		printk(KERN_ERR "%s: timeout waiting for DMA\n", drive->name);
469*4882a593Smuzhiyun 		if (dma_ops->dma_test_irq(drive) == 0) {
470*4882a593Smuzhiyun 			ide_dump_status(drive, "DMA timeout",
471*4882a593Smuzhiyun 					hwif->tp_ops->read_status(hwif));
472*4882a593Smuzhiyun 			drive->waiting_for_dma = 0;
473*4882a593Smuzhiyun 			(void)dma_ops->dma_end(drive);
474*4882a593Smuzhiyun 			ide_dma_unmap_sg(drive, cmd);
475*4882a593Smuzhiyun 		}
476*4882a593Smuzhiyun 	}
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun 	/*
479*4882a593Smuzhiyun 	 * disable dma for now, but remember that we did so because of
480*4882a593Smuzhiyun 	 * a timeout -- we'll reenable after we finish this next request
481*4882a593Smuzhiyun 	 * (or rather the first chunk of it) in pio.
482*4882a593Smuzhiyun 	 */
483*4882a593Smuzhiyun 	drive->dev_flags |= IDE_DFLAG_DMA_PIO_RETRY;
484*4882a593Smuzhiyun 	drive->retry_pio++;
485*4882a593Smuzhiyun 	ide_dma_off_quietly(drive);
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun 	/*
488*4882a593Smuzhiyun 	 * make sure request is sane
489*4882a593Smuzhiyun 	 */
490*4882a593Smuzhiyun 	if (hwif->rq)
491*4882a593Smuzhiyun 		scsi_req(hwif->rq)->result = 0;
492*4882a593Smuzhiyun 	return ret;
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun 
ide_release_dma_engine(ide_hwif_t * hwif)495*4882a593Smuzhiyun void ide_release_dma_engine(ide_hwif_t *hwif)
496*4882a593Smuzhiyun {
497*4882a593Smuzhiyun 	if (hwif->dmatable_cpu) {
498*4882a593Smuzhiyun 		int prd_size = hwif->prd_max_nents * hwif->prd_ent_size;
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun 		dma_free_coherent(hwif->dev, prd_size,
501*4882a593Smuzhiyun 				  hwif->dmatable_cpu, hwif->dmatable_dma);
502*4882a593Smuzhiyun 		hwif->dmatable_cpu = NULL;
503*4882a593Smuzhiyun 	}
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ide_release_dma_engine);
506*4882a593Smuzhiyun 
ide_allocate_dma_engine(ide_hwif_t * hwif)507*4882a593Smuzhiyun int ide_allocate_dma_engine(ide_hwif_t *hwif)
508*4882a593Smuzhiyun {
509*4882a593Smuzhiyun 	int prd_size;
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun 	if (hwif->prd_max_nents == 0)
512*4882a593Smuzhiyun 		hwif->prd_max_nents = PRD_ENTRIES;
513*4882a593Smuzhiyun 	if (hwif->prd_ent_size == 0)
514*4882a593Smuzhiyun 		hwif->prd_ent_size = PRD_BYTES;
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	prd_size = hwif->prd_max_nents * hwif->prd_ent_size;
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun 	hwif->dmatable_cpu = dma_alloc_coherent(hwif->dev, prd_size,
519*4882a593Smuzhiyun 						&hwif->dmatable_dma,
520*4882a593Smuzhiyun 						GFP_ATOMIC);
521*4882a593Smuzhiyun 	if (hwif->dmatable_cpu == NULL) {
522*4882a593Smuzhiyun 		printk(KERN_ERR "%s: unable to allocate PRD table\n",
523*4882a593Smuzhiyun 			hwif->name);
524*4882a593Smuzhiyun 		return -ENOMEM;
525*4882a593Smuzhiyun 	}
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun 	return 0;
528*4882a593Smuzhiyun }
529*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(ide_allocate_dma_engine);
530*4882a593Smuzhiyun 
ide_dma_prepare(ide_drive_t * drive,struct ide_cmd * cmd)531*4882a593Smuzhiyun int ide_dma_prepare(ide_drive_t *drive, struct ide_cmd *cmd)
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun 	const struct ide_dma_ops *dma_ops = drive->hwif->dma_ops;
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	if ((drive->dev_flags & IDE_DFLAG_USING_DMA) == 0 ||
536*4882a593Smuzhiyun 	    (dma_ops->dma_check && dma_ops->dma_check(drive, cmd)))
537*4882a593Smuzhiyun 		goto out;
538*4882a593Smuzhiyun 	ide_map_sg(drive, cmd);
539*4882a593Smuzhiyun 	if (ide_dma_map_sg(drive, cmd) == 0)
540*4882a593Smuzhiyun 		goto out_map;
541*4882a593Smuzhiyun 	if (dma_ops->dma_setup(drive, cmd))
542*4882a593Smuzhiyun 		goto out_dma_unmap;
543*4882a593Smuzhiyun 	drive->waiting_for_dma = 1;
544*4882a593Smuzhiyun 	return 0;
545*4882a593Smuzhiyun out_dma_unmap:
546*4882a593Smuzhiyun 	ide_dma_unmap_sg(drive, cmd);
547*4882a593Smuzhiyun out_map:
548*4882a593Smuzhiyun 	ide_map_sg(drive, cmd);
549*4882a593Smuzhiyun out:
550*4882a593Smuzhiyun 	return 1;
551*4882a593Smuzhiyun }
552