1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
4*4882a593Smuzhiyun * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
5*4882a593Smuzhiyun * Copyright (C) 2007-2011 Bartlomiej Zolnierkiewicz
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * CYPRESS CY82C693 chipset IDE controller
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/types.h>
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/ide.h>
16*4882a593Smuzhiyun #include <linux/init.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <asm/io.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define DRV_NAME "cy82c693"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun * NOTE: the value for busmaster timeout is tricky and I got it by
24*4882a593Smuzhiyun * trial and error! By using a to low value will cause DMA timeouts
25*4882a593Smuzhiyun * and drop IDE performance, and by using a to high value will cause
26*4882a593Smuzhiyun * audio playback to scatter.
27*4882a593Smuzhiyun * If you know a better value or how to calc it, please let me know.
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* twice the value written in cy82c693ub datasheet */
31*4882a593Smuzhiyun #define BUSMASTER_TIMEOUT 0x50
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun * the value above was tested on my machine and it seems to work okay
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* here are the offset definitions for the registers */
37*4882a593Smuzhiyun #define CY82_IDE_CMDREG 0x04
38*4882a593Smuzhiyun #define CY82_IDE_ADDRSETUP 0x48
39*4882a593Smuzhiyun #define CY82_IDE_MASTER_IOR 0x4C
40*4882a593Smuzhiyun #define CY82_IDE_MASTER_IOW 0x4D
41*4882a593Smuzhiyun #define CY82_IDE_SLAVE_IOR 0x4E
42*4882a593Smuzhiyun #define CY82_IDE_SLAVE_IOW 0x4F
43*4882a593Smuzhiyun #define CY82_IDE_MASTER_8BIT 0x50
44*4882a593Smuzhiyun #define CY82_IDE_SLAVE_8BIT 0x51
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #define CY82_INDEX_PORT 0x22
47*4882a593Smuzhiyun #define CY82_DATA_PORT 0x23
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #define CY82_INDEX_CHANNEL0 0x30
50*4882a593Smuzhiyun #define CY82_INDEX_CHANNEL1 0x31
51*4882a593Smuzhiyun #define CY82_INDEX_TIMEOUT 0x32
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /*
54*4882a593Smuzhiyun * set DMA mode a specific channel for CY82C693
55*4882a593Smuzhiyun */
56*4882a593Smuzhiyun
cy82c693_set_dma_mode(ide_hwif_t * hwif,ide_drive_t * drive)57*4882a593Smuzhiyun static void cy82c693_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun const u8 mode = drive->dma_mode;
60*4882a593Smuzhiyun u8 single = (mode & 0x10) >> 4, index = 0, data = 0;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun data = (mode & 3) | (single << 2);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun outb(index, CY82_INDEX_PORT);
67*4882a593Smuzhiyun outb(data, CY82_DATA_PORT);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /*
70*4882a593Smuzhiyun * note: below we set the value for Bus Master IDE TimeOut Register
71*4882a593Smuzhiyun * I'm not absolutely sure what this does, but it solved my problem
72*4882a593Smuzhiyun * with IDE DMA and sound, so I now can play sound and work with
73*4882a593Smuzhiyun * my IDE driver at the same time :-)
74*4882a593Smuzhiyun *
75*4882a593Smuzhiyun * If you know the correct (best) value for this register please
76*4882a593Smuzhiyun * let me know - ASK
77*4882a593Smuzhiyun */
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun data = BUSMASTER_TIMEOUT;
80*4882a593Smuzhiyun outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
81*4882a593Smuzhiyun outb(data, CY82_DATA_PORT);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
cy82c693_set_pio_mode(ide_hwif_t * hwif,ide_drive_t * drive)84*4882a593Smuzhiyun static void cy82c693_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun struct pci_dev *dev = to_pci_dev(hwif->dev);
87*4882a593Smuzhiyun int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
88*4882a593Smuzhiyun const unsigned long T = 1000000 / bus_speed;
89*4882a593Smuzhiyun unsigned int addrCtrl;
90*4882a593Smuzhiyun struct ide_timing t;
91*4882a593Smuzhiyun u8 time_16, time_8;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun /* select primary or secondary channel */
94*4882a593Smuzhiyun if (drive->dn > 1) { /* drive is on the secondary channel */
95*4882a593Smuzhiyun dev = pci_get_slot(dev->bus, dev->devfn+1);
96*4882a593Smuzhiyun if (!dev) {
97*4882a593Smuzhiyun printk(KERN_ERR "%s: tune_drive: "
98*4882a593Smuzhiyun "Cannot find secondary interface!\n",
99*4882a593Smuzhiyun drive->name);
100*4882a593Smuzhiyun return;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun ide_timing_compute(drive, drive->pio_mode, &t, T, 1);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun time_16 = clamp_val(t.recover - 1, 0, 15) |
107*4882a593Smuzhiyun (clamp_val(t.active - 1, 0, 15) << 4);
108*4882a593Smuzhiyun time_8 = clamp_val(t.act8b - 1, 0, 15) |
109*4882a593Smuzhiyun (clamp_val(t.rec8b - 1, 0, 15) << 4);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* now let's write the clocks registers */
112*4882a593Smuzhiyun if ((drive->dn & 1) == 0) {
113*4882a593Smuzhiyun /*
114*4882a593Smuzhiyun * set master drive
115*4882a593Smuzhiyun * address setup control register
116*4882a593Smuzhiyun * is 32 bit !!!
117*4882a593Smuzhiyun */
118*4882a593Smuzhiyun pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun addrCtrl &= (~0xF);
121*4882a593Smuzhiyun addrCtrl |= clamp_val(t.setup - 1, 0, 15);
122*4882a593Smuzhiyun pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun /* now let's set the remaining registers */
125*4882a593Smuzhiyun pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, time_16);
126*4882a593Smuzhiyun pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, time_16);
127*4882a593Smuzhiyun pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, time_8);
128*4882a593Smuzhiyun } else {
129*4882a593Smuzhiyun /*
130*4882a593Smuzhiyun * set slave drive
131*4882a593Smuzhiyun * address setup control register
132*4882a593Smuzhiyun * is 32 bit !!!
133*4882a593Smuzhiyun */
134*4882a593Smuzhiyun pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun addrCtrl &= (~0xF0);
137*4882a593Smuzhiyun addrCtrl |= (clamp_val(t.setup - 1, 0, 15) << 4);
138*4882a593Smuzhiyun pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /* now let's set the remaining registers */
141*4882a593Smuzhiyun pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, time_16);
142*4882a593Smuzhiyun pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, time_16);
143*4882a593Smuzhiyun pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, time_8);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun if (drive->dn > 1)
146*4882a593Smuzhiyun pci_dev_put(dev);
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
init_iops_cy82c693(ide_hwif_t * hwif)149*4882a593Smuzhiyun static void init_iops_cy82c693(ide_hwif_t *hwif)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun static ide_hwif_t *primary;
152*4882a593Smuzhiyun struct pci_dev *dev = to_pci_dev(hwif->dev);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun if (PCI_FUNC(dev->devfn) == 1)
155*4882a593Smuzhiyun primary = hwif;
156*4882a593Smuzhiyun else {
157*4882a593Smuzhiyun hwif->mate = primary;
158*4882a593Smuzhiyun hwif->channel = 1;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun static const struct ide_port_ops cy82c693_port_ops = {
163*4882a593Smuzhiyun .set_pio_mode = cy82c693_set_pio_mode,
164*4882a593Smuzhiyun .set_dma_mode = cy82c693_set_dma_mode,
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun static const struct ide_port_info cy82c693_chipset = {
168*4882a593Smuzhiyun .name = DRV_NAME,
169*4882a593Smuzhiyun .init_iops = init_iops_cy82c693,
170*4882a593Smuzhiyun .port_ops = &cy82c693_port_ops,
171*4882a593Smuzhiyun .host_flags = IDE_HFLAG_SINGLE,
172*4882a593Smuzhiyun .pio_mask = ATA_PIO4,
173*4882a593Smuzhiyun .swdma_mask = ATA_SWDMA2,
174*4882a593Smuzhiyun .mwdma_mask = ATA_MWDMA2,
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun
cy82c693_init_one(struct pci_dev * dev,const struct pci_device_id * id)177*4882a593Smuzhiyun static int cy82c693_init_one(struct pci_dev *dev,
178*4882a593Smuzhiyun const struct pci_device_id *id)
179*4882a593Smuzhiyun {
180*4882a593Smuzhiyun struct pci_dev *dev2;
181*4882a593Smuzhiyun int ret = -ENODEV;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun /* CY82C693 is more than only a IDE controller.
184*4882a593Smuzhiyun Function 1 is primary IDE channel, function 2 - secondary. */
185*4882a593Smuzhiyun if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
186*4882a593Smuzhiyun PCI_FUNC(dev->devfn) == 1) {
187*4882a593Smuzhiyun dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
188*4882a593Smuzhiyun ret = ide_pci_init_two(dev, dev2, &cy82c693_chipset, NULL);
189*4882a593Smuzhiyun if (ret)
190*4882a593Smuzhiyun pci_dev_put(dev2);
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun return ret;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
cy82c693_remove(struct pci_dev * dev)195*4882a593Smuzhiyun static void cy82c693_remove(struct pci_dev *dev)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun struct ide_host *host = pci_get_drvdata(dev);
198*4882a593Smuzhiyun struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun ide_pci_remove(dev);
201*4882a593Smuzhiyun pci_dev_put(dev2);
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun static const struct pci_device_id cy82c693_pci_tbl[] = {
205*4882a593Smuzhiyun { PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
206*4882a593Smuzhiyun { 0, },
207*4882a593Smuzhiyun };
208*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun static struct pci_driver cy82c693_pci_driver = {
211*4882a593Smuzhiyun .name = "Cypress_IDE",
212*4882a593Smuzhiyun .id_table = cy82c693_pci_tbl,
213*4882a593Smuzhiyun .probe = cy82c693_init_one,
214*4882a593Smuzhiyun .remove = cy82c693_remove,
215*4882a593Smuzhiyun .suspend = ide_pci_suspend,
216*4882a593Smuzhiyun .resume = ide_pci_resume,
217*4882a593Smuzhiyun };
218*4882a593Smuzhiyun
cy82c693_ide_init(void)219*4882a593Smuzhiyun static int __init cy82c693_ide_init(void)
220*4882a593Smuzhiyun {
221*4882a593Smuzhiyun return ide_pci_register_driver(&cy82c693_pci_driver);
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun
cy82c693_ide_exit(void)224*4882a593Smuzhiyun static void __exit cy82c693_ide_exit(void)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun pci_unregister_driver(&cy82c693_pci_driver);
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun module_init(cy82c693_ide_init);
230*4882a593Smuzhiyun module_exit(cy82c693_ide_exit);
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun MODULE_AUTHOR("Andreas Krebs, Andre Hedrick, Bartlomiej Zolnierkiewicz");
233*4882a593Smuzhiyun MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
234*4882a593Smuzhiyun MODULE_LICENSE("GPL");
235