xref: /OK3568_Linux_fs/kernel/drivers/ide/ali14xx.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  *  Copyright (C) 1996  Linus Torvalds & author (see below)
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun /*
7*4882a593Smuzhiyun  * ALI M14xx chipset EIDE controller
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Works for ALI M1439/1443/1445/1487/1489 chipsets.
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * Adapted from code developed by derekn@vw.ece.cmu.edu.  -ml
12*4882a593Smuzhiyun  * Derek's notes follow:
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * I think the code should be pretty understandable,
15*4882a593Smuzhiyun  * but I'll be happy to (try to) answer questions.
16*4882a593Smuzhiyun  *
17*4882a593Smuzhiyun  * The critical part is in the setupDrive function.  The initRegisters
18*4882a593Smuzhiyun  * function doesn't seem to be necessary, but the DOS driver does it, so
19*4882a593Smuzhiyun  * I threw it in.
20*4882a593Smuzhiyun  *
21*4882a593Smuzhiyun  * I've only tested this on my system, which only has one disk.  I posted
22*4882a593Smuzhiyun  * it to comp.sys.linux.hardware, so maybe some other people will try it
23*4882a593Smuzhiyun  * out.
24*4882a593Smuzhiyun  *
25*4882a593Smuzhiyun  * Derek Noonburg  (derekn@ece.cmu.edu)
26*4882a593Smuzhiyun  * 95-sep-26
27*4882a593Smuzhiyun  *
28*4882a593Smuzhiyun  * Update 96-jul-13:
29*4882a593Smuzhiyun  *
30*4882a593Smuzhiyun  * I've since upgraded to two disks and a CD-ROM, with no trouble, and
31*4882a593Smuzhiyun  * I've also heard from several others who have used it successfully.
32*4882a593Smuzhiyun  * This driver appears to work with both the 1443/1445 and the 1487/1489
33*4882a593Smuzhiyun  * chipsets.  I've added support for PIO mode 4 for the 1487.  This
34*4882a593Smuzhiyun  * seems to work just fine on the 1443 also, although I'm not sure it's
35*4882a593Smuzhiyun  * advertised as supporting mode 4.  (I've been running a WDC AC21200 in
36*4882a593Smuzhiyun  * mode 4 for a while now with no trouble.)  -Derek
37*4882a593Smuzhiyun  */
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #include <linux/module.h>
40*4882a593Smuzhiyun #include <linux/types.h>
41*4882a593Smuzhiyun #include <linux/kernel.h>
42*4882a593Smuzhiyun #include <linux/delay.h>
43*4882a593Smuzhiyun #include <linux/timer.h>
44*4882a593Smuzhiyun #include <linux/mm.h>
45*4882a593Smuzhiyun #include <linux/ioport.h>
46*4882a593Smuzhiyun #include <linux/blkdev.h>
47*4882a593Smuzhiyun #include <linux/ide.h>
48*4882a593Smuzhiyun #include <linux/init.h>
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun #include <asm/io.h>
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun #define DRV_NAME "ali14xx"
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun /* port addresses for auto-detection */
55*4882a593Smuzhiyun #define ALI_NUM_PORTS 4
56*4882a593Smuzhiyun static const int ports[ALI_NUM_PORTS] __initconst =
57*4882a593Smuzhiyun 	{ 0x074, 0x0f4, 0x034, 0x0e4 };
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun /* register initialization data */
60*4882a593Smuzhiyun typedef struct { u8 reg, data; } RegInitializer;
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun static const RegInitializer initData[] __initconst = {
63*4882a593Smuzhiyun 	{0x01, 0x0f}, {0x02, 0x00}, {0x03, 0x00}, {0x04, 0x00},
64*4882a593Smuzhiyun 	{0x05, 0x00}, {0x06, 0x00}, {0x07, 0x2b}, {0x0a, 0x0f},
65*4882a593Smuzhiyun 	{0x25, 0x00}, {0x26, 0x00}, {0x27, 0x00}, {0x28, 0x00},
66*4882a593Smuzhiyun 	{0x29, 0x00}, {0x2a, 0x00}, {0x2f, 0x00}, {0x2b, 0x00},
67*4882a593Smuzhiyun 	{0x2c, 0x00}, {0x2d, 0x00}, {0x2e, 0x00}, {0x30, 0x00},
68*4882a593Smuzhiyun 	{0x31, 0x00}, {0x32, 0x00}, {0x33, 0x00}, {0x34, 0xff},
69*4882a593Smuzhiyun 	{0x35, 0x03}, {0x00, 0x00}
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun /* timing parameter registers for each drive */
73*4882a593Smuzhiyun static struct { u8 reg1, reg2, reg3, reg4; } regTab[4] = {
74*4882a593Smuzhiyun 	{0x03, 0x26, 0x04, 0x27},     /* drive 0 */
75*4882a593Smuzhiyun 	{0x05, 0x28, 0x06, 0x29},     /* drive 1 */
76*4882a593Smuzhiyun 	{0x2b, 0x30, 0x2c, 0x31},     /* drive 2 */
77*4882a593Smuzhiyun 	{0x2d, 0x32, 0x2e, 0x33},     /* drive 3 */
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun static int basePort;	/* base port address */
81*4882a593Smuzhiyun static int regPort;	/* port for register number */
82*4882a593Smuzhiyun static int dataPort;	/* port for register data */
83*4882a593Smuzhiyun static u8 regOn;	/* output to base port to access registers */
84*4882a593Smuzhiyun static u8 regOff;	/* output to base port to close registers */
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun /*------------------------------------------------------------------------*/
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun /*
89*4882a593Smuzhiyun  * Read a controller register.
90*4882a593Smuzhiyun  */
inReg(u8 reg)91*4882a593Smuzhiyun static inline u8 inReg(u8 reg)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun 	outb_p(reg, regPort);
94*4882a593Smuzhiyun 	return inb(dataPort);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun /*
98*4882a593Smuzhiyun  * Write a controller register.
99*4882a593Smuzhiyun  */
outReg(u8 data,u8 reg)100*4882a593Smuzhiyun static void outReg(u8 data, u8 reg)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun 	outb_p(reg, regPort);
103*4882a593Smuzhiyun 	outb_p(data, dataPort);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun static DEFINE_SPINLOCK(ali14xx_lock);
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun /*
109*4882a593Smuzhiyun  * Set PIO mode for the specified drive.
110*4882a593Smuzhiyun  * This function computes timing parameters
111*4882a593Smuzhiyun  * and sets controller registers accordingly.
112*4882a593Smuzhiyun  */
ali14xx_set_pio_mode(ide_hwif_t * hwif,ide_drive_t * drive)113*4882a593Smuzhiyun static void ali14xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun 	int driveNum;
116*4882a593Smuzhiyun 	int time1, time2;
117*4882a593Smuzhiyun 	u8 param1, param2, param3, param4;
118*4882a593Smuzhiyun 	unsigned long flags;
119*4882a593Smuzhiyun 	int bus_speed = ide_vlb_clk ? ide_vlb_clk : 50;
120*4882a593Smuzhiyun 	const u8 pio = drive->pio_mode - XFER_PIO_0;
121*4882a593Smuzhiyun 	struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	/* calculate timing, according to PIO mode */
124*4882a593Smuzhiyun 	time1 = ide_pio_cycle_time(drive, pio);
125*4882a593Smuzhiyun 	time2 = t->active;
126*4882a593Smuzhiyun 	param3 = param1 = (time2 * bus_speed + 999) / 1000;
127*4882a593Smuzhiyun 	param4 = param2 = (time1 * bus_speed + 999) / 1000 - param1;
128*4882a593Smuzhiyun 	if (pio < 3) {
129*4882a593Smuzhiyun 		param3 += 8;
130*4882a593Smuzhiyun 		param4 += 8;
131*4882a593Smuzhiyun 	}
132*4882a593Smuzhiyun 	printk(KERN_DEBUG "%s: PIO mode%d, t1=%dns, t2=%dns, cycles = %d+%d, %d+%d\n",
133*4882a593Smuzhiyun 		drive->name, pio, time1, time2, param1, param2, param3, param4);
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	/* stuff timing parameters into controller registers */
136*4882a593Smuzhiyun 	driveNum = (drive->hwif->index << 1) + (drive->dn & 1);
137*4882a593Smuzhiyun 	spin_lock_irqsave(&ali14xx_lock, flags);
138*4882a593Smuzhiyun 	outb_p(regOn, basePort);
139*4882a593Smuzhiyun 	outReg(param1, regTab[driveNum].reg1);
140*4882a593Smuzhiyun 	outReg(param2, regTab[driveNum].reg2);
141*4882a593Smuzhiyun 	outReg(param3, regTab[driveNum].reg3);
142*4882a593Smuzhiyun 	outReg(param4, regTab[driveNum].reg4);
143*4882a593Smuzhiyun 	outb_p(regOff, basePort);
144*4882a593Smuzhiyun 	spin_unlock_irqrestore(&ali14xx_lock, flags);
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun /*
148*4882a593Smuzhiyun  * Auto-detect the IDE controller port.
149*4882a593Smuzhiyun  */
findPort(void)150*4882a593Smuzhiyun static int __init findPort(void)
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun 	int i;
153*4882a593Smuzhiyun 	u8 t;
154*4882a593Smuzhiyun 	unsigned long flags;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	local_irq_save(flags);
157*4882a593Smuzhiyun 	for (i = 0; i < ALI_NUM_PORTS; ++i) {
158*4882a593Smuzhiyun 		basePort = ports[i];
159*4882a593Smuzhiyun 		regOff = inb(basePort);
160*4882a593Smuzhiyun 		for (regOn = 0x30; regOn <= 0x33; ++regOn) {
161*4882a593Smuzhiyun 			outb_p(regOn, basePort);
162*4882a593Smuzhiyun 			if (inb(basePort) == regOn) {
163*4882a593Smuzhiyun 				regPort = basePort + 4;
164*4882a593Smuzhiyun 				dataPort = basePort + 8;
165*4882a593Smuzhiyun 				t = inReg(0) & 0xf0;
166*4882a593Smuzhiyun 				outb_p(regOff, basePort);
167*4882a593Smuzhiyun 				local_irq_restore(flags);
168*4882a593Smuzhiyun 				if (t != 0x50)
169*4882a593Smuzhiyun 					return 0;
170*4882a593Smuzhiyun 				return 1;  /* success */
171*4882a593Smuzhiyun 			}
172*4882a593Smuzhiyun 		}
173*4882a593Smuzhiyun 		outb_p(regOff, basePort);
174*4882a593Smuzhiyun 	}
175*4882a593Smuzhiyun 	local_irq_restore(flags);
176*4882a593Smuzhiyun 	return 0;
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun /*
180*4882a593Smuzhiyun  * Initialize controller registers with default values.
181*4882a593Smuzhiyun  */
initRegisters(void)182*4882a593Smuzhiyun static int __init initRegisters(void)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun 	const RegInitializer *p;
185*4882a593Smuzhiyun 	u8 t;
186*4882a593Smuzhiyun 	unsigned long flags;
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	local_irq_save(flags);
189*4882a593Smuzhiyun 	outb_p(regOn, basePort);
190*4882a593Smuzhiyun 	for (p = initData; p->reg != 0; ++p)
191*4882a593Smuzhiyun 		outReg(p->data, p->reg);
192*4882a593Smuzhiyun 	outb_p(0x01, regPort);
193*4882a593Smuzhiyun 	t = inb(regPort) & 0x01;
194*4882a593Smuzhiyun 	outb_p(regOff, basePort);
195*4882a593Smuzhiyun 	local_irq_restore(flags);
196*4882a593Smuzhiyun 	return t;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun static const struct ide_port_ops ali14xx_port_ops = {
200*4882a593Smuzhiyun 	.set_pio_mode		= ali14xx_set_pio_mode,
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun static const struct ide_port_info ali14xx_port_info = {
204*4882a593Smuzhiyun 	.name			= DRV_NAME,
205*4882a593Smuzhiyun 	.chipset		= ide_ali14xx,
206*4882a593Smuzhiyun 	.port_ops		= &ali14xx_port_ops,
207*4882a593Smuzhiyun 	.host_flags		= IDE_HFLAG_NO_DMA,
208*4882a593Smuzhiyun 	.pio_mask		= ATA_PIO4,
209*4882a593Smuzhiyun };
210*4882a593Smuzhiyun 
ali14xx_probe(void)211*4882a593Smuzhiyun static int __init ali14xx_probe(void)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun 	printk(KERN_DEBUG "ali14xx: base=0x%03x, regOn=0x%02x.\n",
214*4882a593Smuzhiyun 			  basePort, regOn);
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	/* initialize controller registers */
217*4882a593Smuzhiyun 	if (!initRegisters()) {
218*4882a593Smuzhiyun 		printk(KERN_ERR "ali14xx: Chip initialization failed.\n");
219*4882a593Smuzhiyun 		return 1;
220*4882a593Smuzhiyun 	}
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	return ide_legacy_device_add(&ali14xx_port_info, 0);
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun static bool probe_ali14xx;
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun module_param_named(probe, probe_ali14xx, bool, 0);
228*4882a593Smuzhiyun MODULE_PARM_DESC(probe, "probe for ALI M14xx chipsets");
229*4882a593Smuzhiyun 
ali14xx_init(void)230*4882a593Smuzhiyun static int __init ali14xx_init(void)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun 	if (probe_ali14xx == 0)
233*4882a593Smuzhiyun 		goto out;
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	/* auto-detect IDE controller port */
236*4882a593Smuzhiyun 	if (findPort()) {
237*4882a593Smuzhiyun 		if (ali14xx_probe())
238*4882a593Smuzhiyun 			return -ENODEV;
239*4882a593Smuzhiyun 		return 0;
240*4882a593Smuzhiyun 	}
241*4882a593Smuzhiyun 	printk(KERN_ERR "ali14xx: not found.\n");
242*4882a593Smuzhiyun out:
243*4882a593Smuzhiyun 	return -ENODEV;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun module_init(ali14xx_init);
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun MODULE_AUTHOR("see local file");
249*4882a593Smuzhiyun MODULE_DESCRIPTION("support of ALI 14XX IDE chipsets");
250*4882a593Smuzhiyun MODULE_LICENSE("GPL");
251